From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Brian Cain" <brian.cain@oss.qualcomm.com>,
sid.manning@oss.qualcomm.com
Subject: [PATCH 07/17] tests/tcg/hexagon: add bit interleave and convergent rounding tests
Date: Sat, 5 Sep 2026 11:09:39 -0700 [thread overview]
Message-ID: <20260905180949.1852673-8-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260905180949.1852673-1-brian.cain@oss.qualcomm.com>
Test the interleave/deinterleave 64-bit bit-manipulation instructions
and the cround instruction.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
tests/tcg/hexagon/test_bitops.c | 98 +++++++++++++++++++++++++++++++++
tests/tcg/hexagon/meson.build | 1 +
2 files changed, 99 insertions(+)
create mode 100644 tests/tcg/hexagon/test_bitops.c
diff --git a/tests/tcg/hexagon/test_bitops.c b/tests/tcg/hexagon/test_bitops.c
new file mode 100644
index 00000000000..3e9274ddddd
--- /dev/null
+++ b/tests/tcg/hexagon/test_bitops.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+/*
+ * Test bit interleave/deinterleave and convergent rounding.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <hexagon_protos.h>
+
+int err;
+
+#include "hex_test.h"
+
+static void check_interleave(void)
+{
+ uint64_t input;
+ uint64_t inter;
+ uint64_t deinter;
+
+ /*
+ * interleave takes the 32 even bits and 32 odd bits of Rss and
+ * interleaves them: even[0] goes to bit 0, odd[0] to bit 1,
+ * even[1] to bit 2, odd[1] to bit 3, etc.
+ *
+ * Input: low 32 bits (even half), high 32 bits (odd half)
+ * If low = 0xFFFFFFFF, high = 0x00000000:
+ * result has every even bit set, every odd bit clear
+ * = 0x5555555555555555
+ */
+ input = 0x00000000FFFFFFFFULL;
+ inter = Q6_P_interleave_P(input);
+ check64(inter, 0x5555555555555555ULL);
+
+ /* All ones should stay all ones */
+ input = 0xFFFFFFFFFFFFFFFFULL;
+ inter = Q6_P_interleave_P(input);
+ check64(inter, 0xFFFFFFFFFFFFFFFFULL);
+
+ /* All zeros should stay all zeros */
+ input = 0x0000000000000000ULL;
+ inter = Q6_P_interleave_P(input);
+ check64(inter, 0x0000000000000000ULL);
+
+ /*
+ * deinterleave is the inverse of interleave.
+ * deinterleave(interleave(x)) should equal x.
+ */
+ input = 0xDEADBEEFCAFEBABEULL;
+ inter = Q6_P_interleave_P(input);
+ deinter = Q6_P_deinterleave_P(inter);
+ check64(deinter, input);
+
+ /* deinterleave of 0x5555...5555 -> low half all 1s, high half all 0s */
+ deinter = Q6_P_deinterleave_P(0x5555555555555555ULL);
+ check64(deinter, 0x00000000FFFFFFFFULL);
+}
+
+static void check_cround(void)
+{
+ /*
+ * cround(0x300, #8) -> 3 (exact shift, no rounding needed).
+ * 0x300 >> 8 = 3
+ */
+ check32(Q6_R_cround_RI(0x300, 8), 3);
+
+ /*
+ * cround(0x380, #8) -> 4 (0x380 >> 8 = 3.5, rounds to even = 4)
+ */
+ check32(Q6_R_cround_RI(0x380, 8), 4);
+
+ /*
+ * cround(0x280, #8) -> 2 (0x280 >> 8 = 2.5, rounds to even = 2)
+ */
+ check32(Q6_R_cround_RI(0x280, 8), 2);
+
+ /*
+ * cround(0x3C0, #8) -> 4 (0x3C0 >> 8 = 3.75, rounds up to 4)
+ */
+ check32(Q6_R_cround_RI(0x3C0, 8), 4);
+
+ /*
+ * Shift by 0 -> return the input unchanged.
+ */
+ check32(Q6_R_cround_RI(42, 0), 42);
+}
+
+int main(void)
+{
+ check_interleave();
+ check_cround();
+
+ puts(err ? "FAIL" : "PASS");
+ return err ? 1 : 0;
+}
diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build
index 4a2826c4276..6c8e26876af 100644
--- a/tests/tcg/hexagon/meson.build
+++ b/tests/tcg/hexagon/meson.build
@@ -69,6 +69,7 @@ tests += {
'test_abs.S': {'cflags': asmflags},
'test_bitcnt.S': {'cflags': asmflags},
'test_bitsplit.S': {'cflags': asmflags},
+ 'test_bitops.c': {'cflags': cflags},
'test_call.S': {'cflags': asmflags},
'test_clobber.S': {'cflags': asmflags},
'test_cmp.S': {'cflags': asmflags},
--
2.34.1
next prev parent reply other threads:[~2026-09-05 18:11 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-05 18:09 [PATCH 00/17] hexagon: TCG test coverage + ubsan fixes Brian Cain
2026-09-05 18:09 ` [PATCH 01/17] tests/tcg/hexagon: fix undefined signed left shift in circ.c Brian Cain
2026-09-08 15:54 ` Sid Manning
2026-09-05 18:09 ` [PATCH 02/17] tests/tcg/hexagon: fix undefined signed left shift in brev.c Brian Cain
2026-09-09 14:43 ` Sid Manning
2026-09-05 18:09 ` [PATCH 03/17] tests/tcg/hexagon: fix undefined signed integer overflow in hvx_misc Brian Cain
2026-09-09 14:50 ` Sid Manning
2026-09-05 18:09 ` [PATCH 04/17] tests/tcg/hexagon: fix undefined integer overflow in v69_hvx.c Brian Cain
2026-09-09 14:51 ` Sid Manning
2026-09-05 18:09 ` [PATCH 05/17] tests/tcg/multiarch: suppress UBSan for float-to-int conversions Brian Cain
2026-09-14 19:43 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 06/17] tests/tcg/hexagon: add FP classification, conversion, and fixup tests Brian Cain
2026-09-14 19:43 ` Pierrick Bouvier
2026-09-05 18:09 ` Brian Cain [this message]
2026-09-10 17:54 ` [PATCH 07/17] tests/tcg/hexagon: add bit interleave and convergent rounding tests Sid Manning
2026-09-05 18:09 ` [PATCH 08/17] tests/tcg/hexagon: add cond call, tstbit-jump, and endloop01 tests Brian Cain
2026-09-14 19:44 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 09/17] tests/tcg/hexagon: add dczeroa cache line zero test Brian Cain
2026-09-10 18:14 ` Sid Manning
2026-09-05 18:09 ` [PATCH 10/17] tests/tcg/hexagon: add HVX vwhist tests Brian Cain
2026-09-14 21:21 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 11/17] tests/tcg/hexagon: add sfrecipa edge case tests Brian Cain
2026-09-14 21:22 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 12/17] tests/tcg/hexagon: add dfmpyhh Brian Cain
2026-09-14 21:22 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 13/17] tests/tcg/hexagon: add unconditional store-immediate tests Brian Cain
2026-09-14 21:23 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 14/17] tests/tcg/hexagon: add predicate register transfer test Brian Cain
2026-09-14 21:23 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 15/17] tests/tcg/hexagon: add rounding conv, sffma:lib, and sfinvsqrta Brian Cain
2026-09-14 21:23 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 16/17] tests/tcg/hexagon: add scalar+HVX and masked store tests Brian Cain
2026-09-14 21:24 ` Pierrick Bouvier
2026-09-05 18:09 ` [PATCH 17/17] tests/tcg/hexagon: add decbin MPS test case Brian Cain
2026-09-14 21:24 ` Pierrick Bouvier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260905180949.1852673-8-brian.cain@oss.qualcomm.com \
--to=brian.cain@oss.qualcomm.com \
--cc=alex.bennee@linaro.org \
--cc=pierrick.bouvier@oss.qualcomm.com \
--cc=qemu-devel@nongnu.org \
--cc=sid.manning@oss.qualcomm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.