From: Yixun Lan <dlan@kernel.org>
To: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
Cc: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Michael Turquette <mturquette@baylibre.com>,
Inochi Amaoto <inochiama@outlook.com>,
Alex Elder <elder@riscstar.com>, Haylen Chu <heylenay@4d2.org>,
Aurelien Jarno <aurelien@aurel32.net>,
stable@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4] clk: spacemit: k3: add CPU PLL rate tables
Date: Sat, 5 Sep 2026 22:17:46 +0000 [thread overview]
Message-ID: <20260905221746-GKD53903@kernel.org> (raw)
In-Reply-To: <uyl23bmb7dtvkneu7wbpmq24gkmrpmr5n5xkanjrnjf27xsp6g@gcjezv6xwolx>
Hi Anirudh,
On 11:41 Sat 05 Sep , Anirudh Srinivasan wrote:
> Hi Troy,
>
..
> > drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 96 insertions(+)
> >
>
> On a recently new K3 board (shipped with OpenSBI/U-boot dated
> end of July), I was seeing upstream kernel boot hang after IMSIC
> initialization. Some logging indicated that it was hanging around the
> clock controller initializations (k3_ccu_driver_init).
>
> On a board running older U-boot/OpenSBI from May, I originally didn't
> observe this hang, but doing multiple repeated boots showed a rare
> instance of this hang happening. Some changes were added to OpenSBI in
> this period (end of June) that trap clock controller registers to M
> Mode and handle reads/writes there.
>
> Yixun pointed me to this patch, and it seems to fix the boot hang on
> the board runner newer OpenSBI. I think this avoids some kind of a
> race condition with disabling/re-enabling a PLL that the clock driver
> does. I'm finding it a bit hard to explain/understand what exactly it
> the reason though.
>
..
> Yixun, could this patch get added in soon?
>
Let's wait a bit, the patch itself do solve the problem, but Aurelien
and me still have some minor concern, see other post in this thread
Although the problem is a combination of vendor firmware + upstream kernel,
but it will affect quite widely and probably last for quite long time, so I
think it would warrant a Fix tag and back port to old stable versions..
> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
>
Thanks for the testing
--
Yixun Lan (dlan)
WARNING: multiple messages have this Message-ID (diff)
From: Yixun Lan <dlan@kernel.org>
To: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
Cc: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Michael Turquette <mturquette@baylibre.com>,
Inochi Amaoto <inochiama@outlook.com>,
Alex Elder <elder@riscstar.com>, Haylen Chu <heylenay@4d2.org>,
Aurelien Jarno <aurelien@aurel32.net>,
stable@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4] clk: spacemit: k3: add CPU PLL rate tables
Date: Sat, 5 Sep 2026 22:17:46 +0000 [thread overview]
Message-ID: <20260905221746-GKD53903@kernel.org> (raw)
In-Reply-To: <uyl23bmb7dtvkneu7wbpmq24gkmrpmr5n5xkanjrnjf27xsp6g@gcjezv6xwolx>
Hi Anirudh,
On 11:41 Sat 05 Sep , Anirudh Srinivasan wrote:
> Hi Troy,
>
..
> > drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 96 insertions(+)
> >
>
> On a recently new K3 board (shipped with OpenSBI/U-boot dated
> end of July), I was seeing upstream kernel boot hang after IMSIC
> initialization. Some logging indicated that it was hanging around the
> clock controller initializations (k3_ccu_driver_init).
>
> On a board running older U-boot/OpenSBI from May, I originally didn't
> observe this hang, but doing multiple repeated boots showed a rare
> instance of this hang happening. Some changes were added to OpenSBI in
> this period (end of June) that trap clock controller registers to M
> Mode and handle reads/writes there.
>
> Yixun pointed me to this patch, and it seems to fix the boot hang on
> the board runner newer OpenSBI. I think this avoids some kind of a
> race condition with disabling/re-enabling a PLL that the clock driver
> does. I'm finding it a bit hard to explain/understand what exactly it
> the reason though.
>
..
> Yixun, could this patch get added in soon?
>
Let's wait a bit, the patch itself do solve the problem, but Aurelien
and me still have some minor concern, see other post in this thread
Although the problem is a combination of vendor firmware + upstream kernel,
but it will affect quite widely and probably last for quite long time, so I
think it would warrant a Fix tag and back port to old stable versions..
> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
>
Thanks for the testing
--
Yixun Lan (dlan)
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next prev parent reply other threads:[~2026-09-05 22:17 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 3:06 [PATCH v4] clk: spacemit: k3: add CPU PLL rate tables Troy Mitchell
2026-09-03 3:06 ` Troy Mitchell
2026-09-03 17:27 ` Aurelien Jarno
2026-09-03 17:27 ` Aurelien Jarno
2026-09-04 3:24 ` Troy Mitchell
2026-09-04 3:24 ` Troy Mitchell
2026-09-05 8:39 ` Aurelien Jarno
2026-09-05 8:39 ` Aurelien Jarno
2026-09-05 22:07 ` Yixun Lan
2026-09-05 22:07 ` Yixun Lan
2026-09-06 11:20 ` Troy Mitchell
2026-09-06 11:20 ` Troy Mitchell
2026-09-06 12:13 ` Yixun Lan
2026-09-06 12:13 ` Yixun Lan
2026-09-05 16:41 ` Anirudh Srinivasan
2026-09-05 16:41 ` Anirudh Srinivasan
2026-09-05 22:17 ` Yixun Lan [this message]
2026-09-05 22:17 ` Yixun Lan
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