From: sashiko-bot@kernel.org
To: yaolu@kylinos.cn
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop
Date: Tue, 08 Sep 2026 05:59:55 +0000 [thread overview]
Message-ID: <20260908055956.028281F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260908055202.141884-1-yaolu@kylinos.cn>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Incomplete fix: identical array indexing bugs exist in CalculateStutterEfficiency functions where `stream_descriptors` is incorrectly indexed with the plane index `k` instead of the mapped stream index.
--
commit 9f32a635ed6555b0a150b8f427a0ef1a3afa7d82
Author: Lu Yao <yaolu@kylinos.cn>
Subject: drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop
This commit fixes a loop boundary in
dcn6_calculate_watermarks_and_dram_speed_change_support() by correctly
using the plane index instead of the inner loop variable to access the
stream descriptor.
> diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
> index ba0082e216d59..ba4dad0cfdf4f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
[ ... ]
> @@ -1271,7 +1271,7 @@ void dcn6_calculate_watermarks_and_dram_speed_change_support(
> DML_LOG_VERBOSE("DML::%s: k=%u, VActiveLatencyHidingUs = %f\n", __func__, k, p->VActiveLatencyHidingUs[k]);
> }
>
> - for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[j].stream_index].writeback.active_writebacks_per_stream; ++j) {
> + for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream; ++j) {
> double byte_per_pixel_luma_in_buffer = 1.0;
> double buffer_for_luma = (double)p->WritebackInterfaceBufferSize * 1024.0 / 2.0;
[Severity: High]
This isn't a bug introduced by this patch, but does this fix miss identical
array indexing bugs in the stutter efficiency calculations?
In dml2_core_dcn6_calcs_dchub.c:dcn6_calculate_stutter_efficiency(), the
code incorrectly uses the plane index (k) directly instead of the mapped
stream index:
for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream; j++)
This exact same direct indexing pattern also occurs in:
- dml2_core_dcn5_calcs_dchub.c:dcn5_CalculateStutterEfficiency()
- dml2_core_dcn4_calcs.c:CalculateStutterEfficiency()
When multiple planes exist and are mapped to streams non-linearly (e.g.,
plane 0 mapped to stream 1) while writeback is active, the wrong stream
descriptor is accessed. This causes the driver to incorrectly calculate
TotalActiveWriteback as 0 instead of its true value.
Since stuttering is incorrectly kept enabled when writeback is active,
the display core could fail to meet memory bandwidth deadlines, resulting
in display underflow.
> if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[j].pixel_format == dml2_444_64) {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260908055202.141884-1-yaolu@kylinos.cn?part=1
prev parent reply other threads:[~2026-09-08 5:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 5:52 [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop yaolu
2026-09-08 5:59 ` sashiko-bot [this message]
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