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* [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop
@ 2026-09-08  5:52 yaolu
  2026-09-08  5:59 ` sashiko-bot
  0 siblings, 1 reply; 2+ messages in thread
From: yaolu @ 2026-09-08  5:52 UTC (permalink / raw)
  To: austin.zheng, jun.lei, harry.wentland, sunpeng.li,
	alexander.deucher, christian.koenig
  Cc: ivan.lipski, Roman.Li, aurabindo.pillai, amd-gfx, dri-devel,
	linux-kernel, Lu Yao

From: Lu Yao <yaolu@kylinos.cn>

Use plane_descriptors[k] for the loop bound, matching the loop body.

Fixes: 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6")
Signed-off-by: Lu Yao <yaolu@kylinos.cn>
---
 .../dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
index a4e2f8604650..60e873edf13c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
@@ -1252,7 +1252,7 @@ void dcn6_calculate_watermarks_and_dram_speed_change_support(
 			DML_LOG_VERBOSE("DML::%s: k=%u, VActiveLatencyHidingUs = %f\n", __func__, k, p->VActiveLatencyHidingUs[k]);
 		}
 
-		for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[j].stream_index].writeback.active_writebacks_per_stream; ++j) {
+		for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream; ++j) {
 			double byte_per_pixel_luma_in_buffer = 1.0;
 			double buffer_for_luma = (double)p->WritebackInterfaceBufferSize * 1024.0 / 2.0;
 			if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[j].pixel_format == dml2_444_64) {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop
  2026-09-08  5:52 [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop yaolu
@ 2026-09-08  5:59 ` sashiko-bot
  0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-09-08  5:59 UTC (permalink / raw)
  To: yaolu; +Cc: dri-devel

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Incomplete fix: identical array indexing bugs exist in CalculateStutterEfficiency functions where `stream_descriptors` is incorrectly indexed with the plane index `k` instead of the mapped stream index.
--

commit 9f32a635ed6555b0a150b8f427a0ef1a3afa7d82
Author: Lu Yao <yaolu@kylinos.cn>
Subject: drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop

This commit fixes a loop boundary in
dcn6_calculate_watermarks_and_dram_speed_change_support() by correctly
using the plane index instead of the inner loop variable to access the
stream descriptor.

> diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
> index ba0082e216d59..ba4dad0cfdf4f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c
[ ... ]
> @@ -1271,7 +1271,7 @@ void dcn6_calculate_watermarks_and_dram_speed_change_support(
>  			DML_LOG_VERBOSE("DML::%s: k=%u, VActiveLatencyHidingUs = %f\n", __func__, k, p->VActiveLatencyHidingUs[k]);
>  		}
>  
> -		for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[j].stream_index].writeback.active_writebacks_per_stream; ++j) {
> +		for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream; ++j) {
>  			double byte_per_pixel_luma_in_buffer = 1.0;
>  			double buffer_for_luma = (double)p->WritebackInterfaceBufferSize * 1024.0 / 2.0;

[Severity: High]
This isn't a bug introduced by this patch, but does this fix miss identical
array indexing bugs in the stutter efficiency calculations?

In dml2_core_dcn6_calcs_dchub.c:dcn6_calculate_stutter_efficiency(), the
code incorrectly uses the plane index (k) directly instead of the mapped
stream index:

    for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream; j++)

This exact same direct indexing pattern also occurs in:
- dml2_core_dcn5_calcs_dchub.c:dcn5_CalculateStutterEfficiency()
- dml2_core_dcn4_calcs.c:CalculateStutterEfficiency()

When multiple planes exist and are mapped to streams non-linearly (e.g.,
plane 0 mapped to stream 1) while writeback is active, the wrong stream
descriptor is accessed. This causes the driver to incorrectly calculate
TotalActiveWriteback as 0 instead of its true value.

Since stuttering is incorrectly kept enabled when writeback is active,
the display core could fail to meet memory bandwidth deadlines, resulting
in display underflow.

>  			if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[j].pixel_format == dml2_444_64) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908055202.141884-1-yaolu@kylinos.cn?part=1

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2026-09-08  5:52 [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop yaolu
2026-09-08  5:59 ` sashiko-bot

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