Re: [PATCH v12 05/12] cxl: Cache endpoint decoder settings during PCI enumeration

[sashiko-bot@kernel.org]

> Populate pci_dev->hdm for CXL.mem functions from pci_bus_add_device(),
> after final PCI fixups and state save but before driver binding. This
> gives driver-free reset paths an early HDM snapshot while avoiding the
> pre-resource-assignment window in PCI capability initialization.
> 
> Use the CXL Register Locator BAR Indicator to find the component register
> BAR, reject unassigned, disabled, or zero memory BAR resources before
> temporarily enabling Memory Space, and restore the original PCI_COMMAND
> value before returning. Cache the CXL Device DVSEC control register with
> the HDM state for reset recovery before a driver can alter it.
> 
> CXL core refreshes the cache as decoders are committed or reset, and keeps
> the cached DVSEC control synchronized when CXL.mem is enabled or disabled.
> Move the register helpers into the built-in CONFIG_CXL_RESET set so the
> early cache path is available without cxl_core, and keep the cxl-test mock
> core from building a duplicate regs.o.
> 
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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