From: Francesco Dolcini <francesco@dolcini.it>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Shawn Guo <shawnguo@kernel.org>
Cc: Francesco Dolcini <francesco.dolcini@toradex.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 5/7] arm64: dts: freescale: Add Lino iMX91
Date: Thu, 10 Sep 2026 12:16:11 +0200 [thread overview]
Message-ID: <20260910101616.139270-6-francesco@dolcini.it> (raw)
In-Reply-To: <20260910101616.139270-1-francesco@dolcini.it>
From: Francesco Dolcini <francesco.dolcini@toradex.com>
Add support for the Lino iMX91 SoM, its Verdin adapter, dahlia and
development carrier board.
Link: https://www.toradex.com/computer-on-modules/lino-arm-family/nxp-imx91
Link: https://www.toradex.com/accessories/lino-verdin-adapter
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx91-lino-verdin-dahlia.dts | 24 ++
.../dts/freescale/imx91-lino-verdin-dev.dts | 24 ++
arch/arm64/boot/dts/freescale/imx91-lino.dtsi | 305 ++++++++++++++++++
4 files changed, 355 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx91-lino-verdin-dahlia.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx91-lino-verdin-dev.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx91-lino.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 319a0e797e94..823ef16ba621 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -847,6 +847,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-tianma-tm050rdh03.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx91-lino-verdin-dahlia.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx91-lino-verdin-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
imx91-9x9-qsb-can1-dtbs += imx91-9x9-qsb.dtb imx91-9x9-qsb-can1.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx91-lino-verdin-dahlia.dts b/arch/arm64/boot/dts/freescale/imx91-lino-verdin-dahlia.dts
new file mode 100644
index 000000000000..eb3a8cdcd08f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-lino-verdin-dahlia.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Lino iMX91 SoM on Lino-Verdin Adapter / Dahlia carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/lino-arm-family/nxp-imx91
+ * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
+ */
+
+/dts-v1/;
+
+#include "imx91.dtsi"
+#include "imx91-lino.dtsi"
+#include "imx93-imx91-lino-verdin-common.dtsi"
+#include "imx93-imx91-lino-verdin-dahlia-common.dtsi"
+
+/ {
+ model = "Toradex Lino iMX91 on Verdin Adapter plus Dahlia Board";
+ compatible = "toradex,lino-imx91-verdin-dahlia",
+ "toradex,lino-imx91-verdin",
+ "toradex,lino-imx91",
+ "fsl,imx91";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx91-lino-verdin-dev.dts b/arch/arm64/boot/dts/freescale/imx91-lino-verdin-dev.dts
new file mode 100644
index 000000000000..a988897f3388
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-lino-verdin-dev.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Lino iMX91 SoM on Lino-Verdin Adapter / Development carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/lino-arm-family/nxp-imx91
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/dts-v1/;
+
+#include "imx91.dtsi"
+#include "imx91-lino.dtsi"
+#include "imx93-imx91-lino-verdin-common.dtsi"
+#include "imx93-imx91-lino-verdin-dev-common.dtsi"
+
+/ {
+ model = "Toradex Lino iMX91 on Verdin Adapter plus Development Board";
+ compatible = "toradex,lino-imx91-verdin-dev",
+ "toradex,lino-imx91-verdin",
+ "toradex,lino-imx91",
+ "fsl,imx91";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx91-lino.dtsi b/arch/arm64/boot/dts/freescale/imx91-lino.dtsi
new file mode 100644
index 000000000000..99d95694e910
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-lino.dtsi
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Lino iMX91 SoM
+ *
+ * https://www.toradex.com/computer-on-modules/lino-arm-family/nxp-imx91
+ */
+
+#include "imx91-pinfunc.h"
+#include "imx93-imx91-lino-common.dtsi"
+
+&iomuxc {
+ /* Lino CAN_1 */
+ pinctrl_can1: can1grp {
+ fsl,pins = <MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e>, /* Lino P12 */
+ <MX91_PAD_PDM_CLK__CAN1_TX 0x139e>; /* Lino P10 */
+ };
+
+ /* Lino CAN_2 */
+ pinctrl_can2: can2grp {
+ fsl,pins = <MX91_PAD_GPIO_IO25__CAN2_TX 0x139e>, /* Lino S28 */
+ <MX91_PAD_GPIO_IO27__CAN2_RX 0x139e>; /* Lino S30 */
+ };
+
+ /* Lino ETH_1 RGMII */
+ pinctrl_eth1: eqosgrp {
+ fsl,pins = <MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1fe>, /* Lino P77 */
+ <MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1fe>, /* Lino P79 */
+ <MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1fe>, /* Lino P81 */
+ <MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1fe>, /* Lino P83 */
+ <MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1fe>, /* Lino P73 */
+ <MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1fe>, /* Lino P75 */
+ <MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x1fe>, /* Lino P97 */
+ <MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x1fe>, /* Lino P95 */
+ <MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x1fe>, /* Lino P93 */
+ <MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x1fe>, /* Lino P91 */
+ <MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1fe>, /* Lino P89 */
+ <MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1fe>; /* Lino P85 */
+ };
+
+ /* Lino ETH MDIO */
+ pinctrl_mdio: eqosmdiogrp {
+ fsl,pins = <MX91_PAD_ENET1_MDC__ENET1_MDC 0x1fe>, /* Lino P69 */
+ <MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x1fe>; /* Lino P67 */
+ };
+
+ /* Lino ETH_2 RGMII */
+ pinctrl_eth2: fecgrp {
+ fsl,pins = <MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1fe>, /* Lino S77 */
+ <MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1fe>, /* Lino S79 */
+ <MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1fe>, /* Lino S81 */
+ <MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1fe>, /* Lino S83 */
+ <MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1fe>, /* Lino S71 */
+ <MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1fe>, /* Lino S73 */
+ <MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x1fe>, /* Lino S99 */
+ <MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x1fe>, /* Lino S97 */
+ <MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x1fe>, /* Lino S93 */
+ <MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x1fe>, /* Lino S91 */
+ <MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x1fe>, /* Lino S87 */
+ <MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x1fe>; /* Lino S89 */
+ };
+
+ /* Lino GPIO_11 */
+ pinctrl_gpio_11: gpio1io10grp {
+ fsl,pins = <MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x139e>; /* Lino P65 */
+ };
+
+ /* Lino SPI_2_CS as GPIO */
+ pinctrl_spi2_cs0_gpio: gpio1io11grp {
+ fsl,pins = <MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x139e>; /* Lino S18 */
+ };
+
+ /* Lino GPIO_1 */
+ pinctrl_gpio1: gpio2io0grp {
+ fsl,pins = <MX91_PAD_GPIO_IO00__GPIO2_IO0 0x139e>; /* Lino P30 */
+ };
+
+ /* Lino GPIO_2 */
+ pinctrl_gpio2: gpio2io1grp {
+ fsl,pins = <MX91_PAD_GPIO_IO01__GPIO2_IO1 0x139e>; /* Lino P32 */
+ };
+
+ /* Lino SPI_1_CS as GPIO */
+ pinctrl_spi1_cs0_gpio: gpio2io12grp {
+ fsl,pins = <MX91_PAD_GPIO_IO12__GPIO2_IO12 0x139e>; /* Lino P58 */
+ };
+
+ /* Lino GPIO_3 */
+ pinctrl_gpio3: gpio2io17grp {
+ fsl,pins = <MX91_PAD_GPIO_IO17__GPIO2_IO17 0x139e>; /* Lino P34 */
+ };
+
+ /* Lino GPIO_4 */
+ pinctrl_gpio4: gpio2io22grp {
+ fsl,pins = <MX91_PAD_GPIO_IO22__GPIO2_IO22 0x139e>; /* Lino P36 */
+ };
+
+ /* Lino PWM_3 as GPIO */
+ pinctrl_pwm3_gpio: gpio2io23grp {
+ fsl,pins = <MX91_PAD_GPIO_IO23__GPIO2_IO23 0x139e>; /* Lino P5 */
+ };
+
+ /* Lino GPIO_5 */
+ pinctrl_gpio5: gpio2io24grp {
+ fsl,pins = <MX91_PAD_GPIO_IO24__GPIO2_IO24 0x139e>; /* Lino P38 */
+ };
+
+ /* Lino GPIO_6 */
+ pinctrl_gpio6: gpio3io26grp {
+ fsl,pins = <MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x139e>; /* Lino P40 */
+ };
+
+ /* Lino GPIO_7 */
+ pinctrl_gpio7: gpio3io27grp {
+ fsl,pins = <MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x139e>; /* Lino P42 */
+ };
+
+ /* Lino GPIO_9 */
+ pinctrl_gpio9: gpio4io14grp {
+ fsl,pins = <MX91_PAD_ENET2_MDC__GPIO4_IO14 0x139e>; /* Lino P46 */
+ };
+
+ /* Lino GPIO_10 */
+ pinctrl_gpio10: gpio4io15grp {
+ fsl,pins = <MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x139e>; /* Lino P48 */
+ };
+
+ /* Lino GPIO_8 */
+ pinctrl_gpio8: gpio4io28grp {
+ fsl,pins = <MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x139e>; /* Lino P44 */
+ };
+
+ /* On-module GPIO_EXP_INT# */
+ pinctrl_gpio_exp_int: gpio4io29grp {
+ fsl,pins = <MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x139e>; /* GPIO_EXP_INT# */
+ };
+
+ /* Lino I2C_1 as GPIO */
+ pinctrl_i2c1_gpio: lpi2c1gpiogrp {
+ fsl,pins = <MX91_PAD_I2C1_SCL__GPIO1_IO0 0x40000b9e>, /* Lino P18 */
+ <MX91_PAD_I2C1_SDA__GPIO1_IO1 0x40000b9e>; /* Lino P16 */
+ };
+
+ /* Lino I2C_1 */
+ pinctrl_i2c1: lpi2c1grp {
+ fsl,pins = <MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e>, /* Lino P18 */
+ <MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e>; /* Lino P16 */
+ };
+
+ /* On-module PMIC I2C as GPIO */
+ pinctrl_pmic_i2c_gpio: lpi2c2gpiogrp {
+ fsl,pins = <MX91_PAD_I2C2_SCL__GPIO1_IO2 0x40000b9e>, /* PMIC_I2C_SCL */
+ <MX91_PAD_I2C2_SDA__GPIO1_IO3 0x40000b9e>; /* PMIC_I2C_SDA */
+ };
+
+ /* On-module PMIC I2C */
+ pinctrl_pmic_i2c: lpi2c2grp {
+ fsl,pins = <MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e>, /* PMIC_I2C_SCL */
+ <MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e>; /* PMIC_I2C_SDA */
+ };
+
+ /* Lino I2C_2 as GPIO */
+ pinctrl_i2c2_gpio: lpi2c3gpiogrp {
+ fsl,pins = <MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e>, /* Lino P20 */
+ <MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e>; /* Lino P22 */
+ };
+
+ /* Lino I2C_2 */
+ pinctrl_i2c2: lpi2c3grp {
+ fsl,pins = <MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e>, /* Lino P20 */
+ <MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e>; /* Lino P22 */
+ };
+
+ /* Lino I2C_3 as GPIO */
+ pinctrl_i2c3_gpio: lpi2c4gpiogrp {
+ fsl,pins = <MX91_PAD_GPIO_IO02__GPIO2_IO2 0x40000b9e>, /* Lino P24 */
+ <MX91_PAD_GPIO_IO03__GPIO2_IO3 0x40000b9e>; /* Lino P26 */
+ };
+
+ /* Lino I2C_3 */
+ pinctrl_i2c3: lpi2c4grp {
+ fsl,pins = <MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x40000b9e>, /* Lino P24 */
+ <MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x40000b9e>; /* Lino P26 */
+ };
+
+ /* Lino SPI_2 */
+ pinctrl_spi2: lpspi1grp {
+ fsl,pins = <MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x139e>, /* Lino S20 */
+ <MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x139e>, /* Lino S22 */
+ <MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x139e>; /* Lino S24 */
+ };
+
+ /* Lino SPI_1 */
+ pinctrl_spi1: lpspi8grp {
+ fsl,pins = <MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x139e>, /* Lino P54 */
+ <MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x139e>, /* Lino P56 */
+ <MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x139e>; /* Lino P52 */
+ };
+
+ /* Lino UART_3 */
+ pinctrl_uart3: lpuart1grp {
+ fsl,pins = <MX91_PAD_UART1_RXD__LPUART1_RX 0x39e>, /* Lino P17 */
+ <MX91_PAD_UART1_TXD__LPUART1_TX 0x39e>; /* Lino P19 */
+ };
+
+ /* Lino UART_4 */
+ pinctrl_uart4: lpuart2grp {
+ fsl,pins = <MX91_PAD_UART2_RXD__LPUART2_RX 0x39e>, /* Lino P23 */
+ <MX91_PAD_UART2_TXD__LPUART2_TX 0x39e>; /* Lino P25 */
+ };
+
+ /* Lino UART_1 */
+ pinctrl_uart1: lpuart6grp {
+ fsl,pins = <MX91_PAD_GPIO_IO04__LPUART6_TX 0x39e>, /* Lino P11 */
+ <MX91_PAD_GPIO_IO05__LPUART6_RX 0x39e>, /* Lino P9 */
+ <MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x39e>, /* Lino P8 */
+ <MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x39e>; /* Lino P6 */
+ };
+
+ /* Lino UART_2 */
+ pinctrl_uart2: lpuart7grp {
+ fsl,pins = <MX91_PAD_GPIO_IO08__LPUART7_TX 0x39e>, /* Lino P15 */
+ <MX91_PAD_GPIO_IO09__LPUART7_RX 0x39e>, /* Lino P13 */
+ <MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x39e>, /* Lino S7 */
+ <MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x39e>; /* Lino S5 */
+ };
+
+ /* Lino I2S_1 */
+ pinctrl_i2s1: sai3grp {
+ fsl,pins = <MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x139e>, /* Lino S94 */
+ <MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x139e>, /* Lino S98 */
+ <MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x139e>, /* Lino S100 */
+ <MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x139e>; /* Lino S96 */
+ };
+
+ /* Lino PWM_1 */
+ pinctrl_pwm1: tpm4ch1grp {
+ fsl,pins = <MX91_PAD_GPIO_IO21__TPM4_CH1 0x139e>; /* Lino P1 */
+ };
+
+ /* Lino PWM_2 */
+ pinctrl_pwm2: tpm5ch2grp {
+ fsl,pins = <MX91_PAD_GPIO_IO18__TPM5_CH2 0x139e>; /* Lino P3 */
+ };
+
+ /* Lino PWM_3 */
+ pinctrl_pwm3: tpm6ch1grp {
+ fsl,pins = <MX91_PAD_GPIO_IO23__TPM6_CH1 0x139e>; /* Lino P5 */
+ };
+
+ /* On-module eMMC */
+ pinctrl_emmc: usdhc1grp {
+ fsl,pins = <MX91_PAD_SD1_CLK__USDHC1_CLK 0x5fe>, /* eMMC_CLK */
+ <MX91_PAD_SD1_CMD__USDHC1_CMD 0x400013fe>, /* eMMC_CMD */
+ <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe>, /* eMMC_DATA0 */
+ <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe>, /* eMMC_DATA1 */
+ <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe>, /* eMMC_DATA2 */
+ <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe>, /* eMMC_DATA3 */
+ <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe>, /* eMMC_DATA4 */
+ <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe>, /* eMMC_DATA5 */
+ <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe>, /* eMMC_DATA6 */
+ <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe>, /* eMMC_DATA7 */
+ <MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1580>; /* eMMC_STROBE */
+ };
+
+ /* Lino SD_1_CD# */
+ pinctrl_sd1_cd: usdhc2cdgrp {
+ fsl,pins = <MX91_PAD_SD2_CD_B__GPIO3_IO0 0x139e>; /* Lino P78 */
+ };
+
+ /* Lino SD_1 */
+ pinctrl_sd1: usdhc2grp {
+ fsl,pins = <MX91_PAD_SD2_CLK__USDHC2_CLK 0x5fe>, /* Lino P68 */
+ <MX91_PAD_SD2_CMD__USDHC2_CMD 0x400013fe>, /* Lino P66 */
+ <MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe>, /* Lino P74 */
+ <MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe>, /* Lino P76 */
+ <MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe>, /* Lino P60 */
+ <MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe>; /* Lino P64 */
+ };
+
+ /* Lino SD_1_PWR_EN */
+ pinctrl_sd1_pwr_en: usdhc2pwrgrp {
+ fsl,pins = <MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x139e>; /* Lino P72 */
+ };
+
+ /* On-module PMIC_SD_2_VSEL */
+ pinctrl_sd1_vsel: usdhc2vselgrp {
+ fsl,pins = <MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e>; /* PMIC_SD_2_VSEL */
+ };
+
+ /* Lino SD_2 */
+ pinctrl_sd2: usdhc3grp {
+ fsl,pins = <MX91_PAD_SD3_CLK__USDHC3_CLK 0x5fe>, /* Lino S10 */
+ <MX91_PAD_SD3_CMD__USDHC3_CMD 0x400013fe>, /* Lino S8 */
+ <MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe>, /* Lino S12 */
+ <MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe>, /* Lino S16 */
+ <MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe>, /* Lino S2 */
+ <MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe>; /* Lino S4 */
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e>; /* PMIC_WDOG_B */
+ };
+};
--
2.47.3
next prev parent reply other threads:[~2026-09-10 10:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 10:16 [PATCH v1 0/7] arm64: dts: freescale: Add Toradex Lino and OSM iMX91/iMX93 Francesco Dolcini
2026-09-10 10:16 ` [PATCH v1 1/7] dt-bindings: arm: fsl: Add Lino iMX91/iMX93 Francesco Dolcini
2026-09-11 8:47 ` Krzysztof Kozlowski
2026-09-10 10:16 ` [PATCH v1 2/7] dt-bindings: arm: fsl: Add Toradex OSM iMX91/iMX93 Francesco Dolcini
2026-09-11 8:47 ` Krzysztof Kozlowski
2026-09-10 10:16 ` [PATCH v1 3/7] arm64: dts: freescale: Add Lino iMX93 Francesco Dolcini
2026-09-10 16:04 ` Frank Li
2026-09-10 16:10 ` Francesco Dolcini
2026-09-10 10:16 ` [PATCH v1 4/7] arm64: dts: freescale: imx93-lino: Add dahlia Francesco Dolcini
2026-09-10 10:16 ` Francesco Dolcini [this message]
2026-09-10 10:16 ` [PATCH v1 6/7] arm64: dts: freescale: Add Toradex OSM iMX93 Francesco Dolcini
2026-09-10 10:16 ` [PATCH v1 7/7] arm64: dts: freescale: Add Toradex OSM iMX91 Francesco Dolcini
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