[PATCH 0/2] clk: renesas: r8a779g0: Add ZG clocks

All of lore.kernel.org
 help / color / mirror / Atom feed

* [PATCH 0/2] clk: renesas: r8a779g0: Add ZG clocks
@ 2026-09-15  2:27 Kuninori Morimoto
  2026-09-15  2:28 ` [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z() Kuninori Morimoto
  2026-09-15  2:28 ` [PATCH 2/2] clk: renesas: r8a779g0: Add ZG clocks Kuninori Morimoto
  0 siblings, 2 replies; 5+ messages in thread
From: Kuninori Morimoto @ 2026-09-15  2:27 UTC (permalink / raw)
  To: Brian Masney, Geert Uytterhoeven, Jerome Brunet, Stephen Boyd
  Cc: linux-clk, linux-renesas-soc, Anh Nguyen


Hi Geert

This patch tidyp DEF_GEN4_Z(), and adds ZG clocks for r8a779g0

Kuninori Morimoto (2):
  clk: renesas: tidyup DEF_GEN4_Z()
  clk: renesas: r8a779g0: Add ZG clocks

 drivers/clk/renesas/r8a779a0-cpg-mssr.c |  6 +++---
 drivers/clk/renesas/r8a779f0-cpg-mssr.c |  4 ++--
 drivers/clk/renesas/r8a779g0-cpg-mssr.c |  4 +++-
 drivers/clk/renesas/r8a779h0-cpg-mssr.c |  8 ++++----
 drivers/clk/renesas/rcar-gen4-cpg.c     | 25 +++++++++++--------------
 drivers/clk/renesas/rcar-gen4-cpg.h     | 13 +++++++++++--
 6 files changed, 34 insertions(+), 26 deletions(-)

-- 
2.53.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z()
  2026-09-15  2:27 [PATCH 0/2] clk: renesas: r8a779g0: Add ZG clocks Kuninori Morimoto
@ 2026-09-15  2:28 ` Kuninori Morimoto
  2026-09-15  2:36   ` sashiko-bot
  2026-09-15  2:28 ` [PATCH 2/2] clk: renesas: r8a779g0: Add ZG clocks Kuninori Morimoto
  1 sibling, 1 reply; 5+ messages in thread
From: Kuninori Morimoto @ 2026-09-15  2:28 UTC (permalink / raw)
  To: Brian Masney, Geert Uytterhoeven, Jerome Brunet, Stephen Boyd
  Cc: linux-clk, linux-renesas-soc, Anh Nguyen

Current DEF_GEN4_Z() is using .offset to get "reg" and "pos", but the
offset positions and calculations differ from intuition (the register
is located in the order B -> C0 -> C1, but it is using C0 -> C1 -> B).
Tidyup them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c |  6 +++---
 drivers/clk/renesas/r8a779f0-cpg-mssr.c |  4 ++--
 drivers/clk/renesas/r8a779g0-cpg-mssr.c |  2 +-
 drivers/clk/renesas/r8a779h0-cpg-mssr.c |  8 ++++----
 drivers/clk/renesas/rcar-gen4-cpg.c     | 25 +++++++++++--------------
 drivers/clk/renesas/rcar-gen4-cpg.h     | 13 +++++++++++--
 6 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index d67dff05d9f4a..c0caecd15c2a4 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -99,9 +99,9 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_BASE(".rpcsrc",		CLK_RPCSRC,	CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
 
 	/* Core Clock Outputs */
-	DEF_GEN4_Z("z0",	R8A779A0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL20,	2, 0),
-	DEF_GEN4_Z("z1",	R8A779A0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL21,	2, 8),
-	DEF_GEN4_Z("zg",	R8A779A0_CLK_ZG,	CLK_TYPE_GEN4_Z,	CLK_PLL4,	2, 88),
+	DEF_GEN4_Z("z0",	R8A779A0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL20,	2, CPG_FRQCRC0, 0),
+	DEF_GEN4_Z("z1",	R8A779A0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL21,	2, CPG_FRQCRC0, 8),
+	DEF_GEN4_Z("zg",	R8A779A0_CLK_ZG,	CLK_TYPE_GEN4_Z,	CLK_PLL4,	2, CPG_FRQCRB,  24),
 	DEF_FIXED("zx",		R8A779A0_CLK_ZX,	CLK_PLL20_DIV2,	2, 1),
 	DEF_FIXED("s1d1",	R8A779A0_CLK_S1D1,	CLK_S1,		1, 1),
 	DEF_FIXED("s1d2",	R8A779A0_CLK_S1D2,	CLK_S1,		2, 1),
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index f33342314b2ef..77e70f7ecc634 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -79,8 +79,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
 	DEF_BASE(".rpcsrc",	CLK_RPCSRC,	CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
 
 	/* Core Clock Outputs */
-	DEF_GEN4_Z("z0",	R8A779F0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 0),
-	DEF_GEN4_Z("z1",	R8A779F0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 8),
+	DEF_GEN4_Z("z0",	R8A779F0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, CPG_FRQCRC0, 0),
+	DEF_GEN4_Z("z1",	R8A779F0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, CPG_FRQCRC0, 8),
 	DEF_FIXED("s0d2",	R8A779F0_CLK_S0D2,	CLK_S0,		2, 1),
 	DEF_FIXED("s0d3",	R8A779F0_CLK_S0D3,	CLK_S0,		3, 1),
 	DEF_FIXED("s0d4",	R8A779F0_CLK_S0D4,	CLK_S0,		4, 1),
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 54ba76ff5ab0f..45e65636f8d11 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -96,7 +96,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
 	DEF_FIXED(".vc",	CLK_VC,		CLK_PLL5_DIV2,	3, 1),
 
 	/* Core Clock Outputs */
-	DEF_GEN4_Z("z0",	R8A779G0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 0),
+	DEF_GEN4_Z("z0",	R8A779G0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, CPG_FRQCRC0, 0),
 	DEF_FIXED("s0d2",	R8A779G0_CLK_S0D2,	CLK_S0,		2, 1),
 	DEF_FIXED("s0d3",	R8A779G0_CLK_S0D3,	CLK_S0,		3, 1),
 	DEF_FIXED("s0d4",	R8A779G0_CLK_S0D4,	CLK_S0,		4, 1),
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index ffea06d77d5ea..7f3ac5a2ddc2f 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -99,10 +99,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {
 	DEF_RATE(".oco",	CLK_OCO,	32768),
 
 	/* Core Clock Outputs */
-	DEF_GEN4_Z("zc0",	R8A779H0_CLK_ZC0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 0),
-	DEF_GEN4_Z("zc1",	R8A779H0_CLK_ZC1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 8),
-	DEF_GEN4_Z("zc2",	R8A779H0_CLK_ZC2,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 32),
-	DEF_GEN4_Z("zc3",	R8A779H0_CLK_ZC3,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 40),
+	DEF_GEN4_Z("zc0",	R8A779H0_CLK_ZC0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, CPG_FRQCRC0, 0),
+	DEF_GEN4_Z("zc1",	R8A779H0_CLK_ZC1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, CPG_FRQCRC0, 8),
+	DEF_GEN4_Z("zc2",	R8A779H0_CLK_ZC2,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, CPG_FRQCRC1, 0),
+	DEF_GEN4_Z("zc3",	R8A779H0_CLK_ZC3,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, CPG_FRQCRC1, 8),
 	DEF_FIXED("s0d2",	R8A779H0_CLK_S0D2,	CLK_S0,		2, 1),
 	DEF_FIXED("s0d3",	R8A779H0_CLK_S0D3,	CLK_S0,		3, 1),
 	DEF_FIXED("s0d4",	R8A779H0_CLK_S0D4,	CLK_S0,		4, 1),
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 96922789e02ad..c3beb31f96b30 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -259,10 +259,7 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
 /*
  * Z0, Z1 and ZG Clock
  */
-#define CPG_FRQCRB			0x00000804
 #define CPG_FRQCRB_KICK			BIT(31)
-#define CPG_FRQCRC0			0x00000808
-#define CPG_FRQCRC1			0x000008e0
 
 struct cpg_z_clk {
 	struct clk_hw hw;
@@ -384,17 +381,17 @@ static struct clk * __init cpg_z_clk_register(const char *name,
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 
-	if (offset < 32) {
-		zclk->reg = reg + CPG_FRQCRC0;
-	} else if (offset < 64) {
-		zclk->reg = reg + CPG_FRQCRC1;
-		offset -= 32;
-	} else if (offset < 96) {
-		zclk->reg = reg + CPG_FRQCRB;
-		offset -= 64;
-	} else {
-		return ERR_PTR(-EINVAL);
-	}
+	/*
+	 * offset 0xAAABB
+	 * AAA : reg
+	 * BB  : pos
+	 *
+	 * see
+	 *	DEF_GEN4_Z()
+	 */
+	zclk->reg = reg + (offset >> FRQCR_offset);
+	offset = offset & 0x1F; /* 0 - 31 */
+
 	zclk->kick_reg = reg + CPG_FRQCRB;
 	zclk->hw.init = &init;
 	zclk->mask = GENMASK(offset + 4, offset);
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index 6c8280b37c37b..cfc150750dc4d 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -58,8 +58,14 @@ enum rcar_gen4_clk_types {
 #define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent)	\
 	DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx)
 
-#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)	\
-	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
+/*
+ * offset 0xAAABB
+ * AAA : reg
+ * BB  : pos
+ */
+#define FRQCR_offset	8
+#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, reg, pos)	\
+	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = (reg << FRQCR_offset) + pos)
 
 struct rcar_gen4_cpg_pll_config {
 	u8 extal_div;
@@ -70,6 +76,9 @@ struct rcar_gen4_cpg_pll_config {
 	u8 osc_prediv;
 };
 
+#define CPG_FRQCRB	0x804	/* Frequency Control Register B */
+#define CPG_FRQCRC0	0x808	/* Frequency Control Register C0 */
+#define CPG_FRQCRC1	0x8e0	/* Frequency Control Register C1 */
 #define CPG_SD0CKCR	0x870	/* SD-IF0 Clock Frequency Control Register */
 #define CPG_CANFDCKCR	0x878	/* CAN-FD Clock Frequency Control Register */
 #define CPG_MSOCKCR	0x87c	/* MSIOF Clock Frequency Control Register */
-- 
2.53.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z()
  2026-09-15  2:28 ` [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z() Kuninori Morimoto
@ 2026-09-15  2:36   ` sashiko-bot
  2026-09-15  3:14     ` Kuninori Morimoto
  0 siblings, 1 reply; 5+ messages in thread
From: sashiko-bot @ 2026-09-15  2:36 UTC (permalink / raw)
  To: Kuninori Morimoto; +Cc: linux-clk, wsa+renesas

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] clk: renesas: DEF_GEN4_Z macro arguments lack parentheses
--

commit ad51061672812b3bccf2c0614e480e134d8fc4e5
Author: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

clk: renesas: tidyup DEF_GEN4_Z()

This commit updates the DEF_GEN4_Z macro to take the register offset
and bit position explicitly rather than deriving them from a single
flat offset. It simplifies the offset calculation logic inside
cpg_z_clk_register().

> diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
> index 6c8280b37c37b..cfc150750dc4d 100644
> --- a/drivers/clk/renesas/rcar-gen4-cpg.h
> +++ b/drivers/clk/renesas/rcar-gen4-cpg.h
> @@ -58,8 +58,14 @@ enum rcar_gen4_clk_types {
>  #define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent)	\
>  	DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx)
>  
> -#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)	\
> -	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
> +/*
> + * offset 0xAAABB
> + * AAA : reg
> + * BB  : pos
> + */
> +#define FRQCR_offset	8
> +#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, reg, pos)	\
> +	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = (reg << FRQCR_offset) + pos)

[Severity: Low]
This isn't a bug introduced by this patch since current callers pass simple
constants, but could the lack of parentheses around the reg and pos arguments
cause issues in the future?

If an expression is ever passed for these arguments, operator precedence
rules might cause the offset to be miscalculated (e.g., if reg is passed
as BASE + 4, it would expand to BASE + 4 << 8 + pos). Could parentheses
be added around (reg) and (pos) to prevent this?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/87cxufs0yi.wl-kuninori.morimoto.gx@renesas.com?part=1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z()
  2026-09-15  2:36   ` sashiko-bot
@ 2026-09-15  3:14     ` Kuninori Morimoto
  0 siblings, 0 replies; 5+ messages in thread
From: Kuninori Morimoto @ 2026-09-15  3:14 UTC (permalink / raw)
  To: Geert Uytterhoeven; +Cc: Wolfram Sang, linux-clk


Hi Geert

> This commit updates the DEF_GEN4_Z macro to take the register offset
> and bit position explicitly rather than deriving them from a single
> flat offset. It simplifies the offset calculation logic inside
> cpg_z_clk_register().
(snip)
> > +#define FRQCR_offset 8
> > +#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, reg, pos)       \
> > +     DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = (reg << FRQCR_offset) + pos)
> 
> [Severity: Low]
> This isn't a bug introduced by this patch since current callers pass simple
> constants, but could the lack of parentheses around the reg and pos arguments
> cause issues in the future?
> 
> If an expression is ever passed for these arguments, operator precedence
> rules might cause the offset to be miscalculated (e.g., if reg is passed
> as BASE + 4, it would expand to BASE + 4 << 8 + pos). Could parentheses
> be added around (reg) and (pos) to prevent this?

Yes, indeed. I will update it

BTW, I think we can include CLK_TYPE_GEN4_Z into DEF_GEN4_Z(), and
reduce the line len ?

	DEF_GEN4_Z(..., CLK_TYPE_GEN4_Z, ...);
	                ^^^^^^^^^^^^^^^
Will post v2

Thank you for your help !!

Best regards
---
Kuninori Morimoto

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/2] clk: renesas: r8a779g0: Add ZG clocks
  2026-09-15  2:27 [PATCH 0/2] clk: renesas: r8a779g0: Add ZG clocks Kuninori Morimoto
  2026-09-15  2:28 ` [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z() Kuninori Morimoto
@ 2026-09-15  2:28 ` Kuninori Morimoto
  1 sibling, 0 replies; 5+ messages in thread
From: Kuninori Morimoto @ 2026-09-15  2:28 UTC (permalink / raw)
  To: Brian Masney, Geert Uytterhoeven, Jerome Brunet, Stephen Boyd
  Cc: linux-clk, linux-renesas-soc, Anh Nguyen

Add ZG related clocks for GSX

Signed-off-by: Anh Nguyen <anh.nguyen.pv@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 45e65636f8d11..bc24bf7e1f689 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -97,6 +97,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
 
 	/* Core Clock Outputs */
 	DEF_GEN4_Z("z0",	R8A779G0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, CPG_FRQCRC0, 0),
+	DEF_GEN4_Z("zg",	R8A779G0_CLK_ZG,	CLK_TYPE_GEN4_Z,	CLK_PLL4,	2, CPG_FRQCRB, 24),
 	DEF_FIXED("s0d2",	R8A779G0_CLK_S0D2,	CLK_S0,		2, 1),
 	DEF_FIXED("s0d3",	R8A779G0_CLK_S0D3,	CLK_S0,		3, 1),
 	DEF_FIXED("s0d4",	R8A779G0_CLK_S0D4,	CLK_S0,		4, 1),
@@ -163,6 +164,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
+	DEF_MOD("rgx",		  0,	R8A779G0_CLK_ZG),
 	DEF_MOD("isp0",		 16,	R8A779G0_CLK_S0D2_VIO),
 	DEF_MOD("isp1",		 17,	R8A779G0_CLK_S0D2_VIO),
 	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),
-- 
2.53.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2026-09-15  3:14 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-15  2:27 [PATCH 0/2] clk: renesas: r8a779g0: Add ZG clocks Kuninori Morimoto
2026-09-15  2:28 ` [PATCH 1/2] clk: renesas: tidyup DEF_GEN4_Z() Kuninori Morimoto
2026-09-15  2:36   ` sashiko-bot
2026-09-15  3:14     ` Kuninori Morimoto
2026-09-15  2:28 ` [PATCH 2/2] clk: renesas: r8a779g0: Add ZG clocks Kuninori Morimoto

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.