From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com,
andrew.jones@oss.qualcomm.com, anup@brainfault.org,
jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com,
atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com,
joerg.roedel@amd.com
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains
Date: Tue, 15 Sep 2026 11:28:27 +0800 [thread overview]
Message-ID: <20260915032828.11250-9-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when
attaching a second-stage domain, if the IOMMU supports AMO_HWAD.
Software pre-populates second-stage page tables with D set, so
enabling GADE by default does not change normal behavior. When
dirty tracking is enabled, iommufd clears the pre-set D bits and
GADE becomes necessary for hardware to update the dirty bit on
write access.
This avoids toggling GADE dynamically and keeps device context
setup consistent with second-stage domain attachment.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
drivers/iommu/riscv/iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 16779877351b..f01fd4e2f840 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
+ dc.tc |= RISCV_IOMMU_DC_TC_GADE;
} else {
if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode))
return -ENODEV;
--
2.50.1
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com,
andrew.jones@oss.qualcomm.com, anup@brainfault.org,
jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com,
atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com,
joerg.roedel@amd.com
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains
Date: Tue, 15 Sep 2026 11:28:27 +0800 [thread overview]
Message-ID: <20260915032828.11250-9-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when
attaching a second-stage domain, if the IOMMU supports AMO_HWAD.
Software pre-populates second-stage page tables with D set, so
enabling GADE by default does not change normal behavior. When
dirty tracking is enabled, iommufd clears the pre-set D bits and
GADE becomes necessary for hardware to update the dirty bit on
write access.
This avoids toggling GADE dynamically and keeps device context
setup consistent with second-stage domain attachment.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
drivers/iommu/riscv/iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 16779877351b..f01fd4e2f840 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
+ dc.tc |= RISCV_IOMMU_DC_TC_GADE;
} else {
if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode))
return -ENODEV;
--
2.50.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com,
andrew.jones@oss.qualcomm.com, anup@brainfault.org,
jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com,
atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com,
joerg.roedel@amd.com
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains
Date: Tue, 15 Sep 2026 11:28:27 +0800 [thread overview]
Message-ID: <20260915032828.11250-9-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when
attaching a second-stage domain, if the IOMMU supports AMO_HWAD.
Software pre-populates second-stage page tables with D set, so
enabling GADE by default does not change normal behavior. When
dirty tracking is enabled, iommufd clears the pre-set D bits and
GADE becomes necessary for hardware to update the dirty bit on
write access.
This avoids toggling GADE dynamically and keeps device context
setup consistent with second-stage domain attachment.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
drivers/iommu/riscv/iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 16779877351b..f01fd4e2f840 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
+ dc.tc |= RISCV_IOMMU_DC_TC_GADE;
} else {
if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode))
return -ENODEV;
--
2.50.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
next prev parent reply other threads:[~2026-09-15 3:28 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 3:28 [RFC PATCH v4 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 02/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 03/10] iommu/riscv: report iommu capabilities fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-18 3:39 ` Nutty.Liu
2026-09-18 3:39 ` Nutty.Liu
2026-09-18 3:39 ` Nutty.Liu
2026-09-15 3:28 ` [RFC PATCH v4 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-18 3:42 ` Nutty.Liu
2026-09-18 3:42 ` Nutty.Liu
2026-09-18 3:42 ` Nutty.Liu
2026-09-18 16:08 ` Gong Shuai
2026-09-18 16:08 ` Gong Shuai
2026-09-18 16:08 ` Gong Shuai
2026-09-20 3:08 ` fangyu.yu
2026-09-20 3:08 ` fangyu.yu
2026-09-20 3:08 ` fangyu.yu
2026-09-20 5:27 ` Gong Shuai
2026-09-20 5:27 ` Gong Shuai
2026-09-20 5:27 ` Gong Shuai
2026-09-15 3:28 ` [RFC PATCH v4 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-18 4:03 ` Nutty.Liu
2026-09-18 4:03 ` Nutty.Liu
2026-09-18 4:03 ` Nutty.Liu
2026-09-15 3:28 ` [RFC PATCH v4 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-18 4:03 ` Nutty.Liu
2026-09-18 4:03 ` Nutty.Liu
2026-09-18 4:03 ` Nutty.Liu
2026-09-15 3:28 ` [RFC PATCH v4 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu [this message]
2026-09-15 3:28 ` [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-18 16:18 ` Gong Shuai
2026-09-18 16:18 ` Gong Shuai
2026-09-18 16:18 ` Gong Shuai
2026-09-20 3:12 ` fangyu.yu
2026-09-20 3:12 ` fangyu.yu
2026-09-20 3:12 ` fangyu.yu
2026-09-20 5:05 ` Gong Shuai
2026-09-20 5:05 ` Gong Shuai
2026-09-20 5:05 ` Gong Shuai
2026-09-20 7:42 ` fangyu.yu
2026-09-20 7:42 ` fangyu.yu
2026-09-20 7:42 ` fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-15 3:28 ` fangyu.yu
2026-09-17 1:40 ` [RFC PATCH v4 00/10] iommu/riscv: Add hardware dirty tracking " Gong Shuai
2026-09-17 1:40 ` Gong Shuai
2026-09-17 1:40 ` Gong Shuai
2026-09-17 2:02 ` fangyu.yu
2026-09-17 2:02 ` fangyu.yu
2026-09-17 2:02 ` fangyu.yu
2026-09-17 2:54 ` [RFC PATCH v4 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries fangyu.yu
2026-09-17 2:54 ` fangyu.yu
2026-09-17 2:54 ` fangyu.yu
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