From: Orgad Shaneh <orgads@gmail.com>
To: tsbogend@alpha.franken.de
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/5] MIPS: OCTEON: cvmx-l2c: add the CN66XX L2 geometry
Date: Tue, 15 Sep 2026 07:12:45 +0000 [thread overview]
Message-ID: <20260915071306.15006-2-orgads@gmail.com> (raw)
In-Reply-To: <20260915071306.15006-1-orgads@gmail.com>
cvmx_l2c_get_set_bits() and cvmx_l2c_get_num_assoc() know the CN63XX as
the only OCTEON II part, so on a CN6635 both fell through to their
"Unsupported OCTEON Model" defaults: 2048 sets, and 8 ways which the
CN3XXX/CN5XXX fuse path - a read of L2D_FUS3, which is not a register
on OCTEON II - then shifted down to 2.
The CN66XX L2 has the CN63XX geometry, 16 ways and 1024 sets, and
reports its fused-off ways in MIO_FUS_DAT3[l2c_crip] like the rest of
OCTEON II, so name it in those three branches. With this the board
reports assoc 16, sets 1024, and cvmx_l2c_lock_line() computes the tag
alias from the right associativity.
The CN68XX and CN61XX are deliberately left alone: their L2 geometry
differs from the CN63XX, and the CN68XX also uses bit <2> of
MIO_FUS_DAT3[l2c_crip], which the decoding here does not handle. I have
no such board to test on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Orgad Shaneh <orgads@gmail.com>
---
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -773,7 +773,9 @@ int cvmx_l2c_get_set_bits(void)
if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
l2_set_bits = 11; /* 2048 sets */
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN38XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN66XX))
l2_set_bits = 10; /* 1024 sets */
else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
l2_set_bits = 9; /* 512 sets */
@@ -805,7 +807,8 @@ int cvmx_l2c_get_num_assoc(void)
OCTEON_IS_MODEL(OCTEON_CN50XX) ||
OCTEON_IS_MODEL(OCTEON_CN38XX))
l2_assoc = 8;
- else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN63XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN66XX))
l2_assoc = 16;
else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
OCTEON_IS_MODEL(OCTEON_CN30XX))
@@ -816,7 +819,7 @@ int cvmx_l2c_get_num_assoc(void)
}
/* Check to see if part of the cache is disabled */
- if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) {
union cvmx_mio_fus_dat3 mio_fus_dat3;
mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
--
2.47.0
next prev parent reply other threads:[~2026-09-15 7:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 7:12 [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Orgad Shaneh
2026-09-15 7:12 ` Orgad Shaneh [this message]
2026-09-26 9:34 ` [PATCH 2/5] MIPS: OCTEON: cvmx-l2c: add the CN66XX L2 geometry Thomas Bogendoerfer
2026-09-15 7:12 ` [PATCH 3/5] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II Orgad Shaneh
2026-09-26 9:35 ` Thomas Bogendoerfer
2026-09-15 7:12 ` [PATCH 4/5] MIPS: OCTEON: program L2C_CTL, not L2C_CFG, " Orgad Shaneh
2026-09-26 9:35 ` Thomas Bogendoerfer
2026-09-15 7:12 ` [PATCH 5/5] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1 Orgad Shaneh
2026-09-26 9:35 ` Thomas Bogendoerfer
2026-09-26 9:34 ` [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Thomas Bogendoerfer
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