From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Orgad Shaneh <orgads@gmail.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II
Date: Sat, 26 Sep 2026 11:35:23 +0200 [thread overview]
Message-ID: <areR20hl5SIKNG6-@alpha.franken.de> (raw)
In-Reply-To: <20260915071306.15006-4-orgads@gmail.com>
On Tue, Sep 15, 2026 at 07:12:47AM +0000, Orgad Shaneh wrote:
> cvmx_helper_initialize_packet_io_global() sets the L2 arbitration modes
> by rewriting L2C_CFG. That register (0x1180080000000) does not exist on
> OCTEON II; there the L2 controller is configured through L2C_CTL
> (0x1180080800000), whose corresponding fields are rsp_arb_mode and
> xmc_arb_mode.
>
> On a CN6335 the stray write hung the board hard when this function ran -
> no exception, no watchdog, just a dead console.
>
> Keep the L2C_CFG write for CN3XXX/CN5XXX and program L2C_CTL on CN6XXX
> with the values the vendor SDK uses there (rsp_arb_mode 1,
> xmc_arb_mode 0), which is the same trade the existing code makes for
> the older parts: keep IO blocks from being starved under high L2 load.
>
> Assisted-by: Claude:claude-opus-5
> Signed-off-by: Orgad Shaneh <orgads@gmail.com>
> ---
> diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
> --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
> +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
> @@ -1014,7 +1014,6 @@ int cvmx_helper_initialize_packet_io_global(void)
> {
> int result = 0;
> int interface;
> - union cvmx_l2c_cfg l2c_cfg;
> const int num_interfaces = cvmx_helper_get_number_of_interfaces();
>
> /*
> @@ -1029,10 +1028,21 @@ int cvmx_helper_initialize_packet_io_global(void)
> * to the cores. This avoids conditions where IO blocks might
> * be starved under very high L2 loads.
> */
> - l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
> - l2c_cfg.s.lrf_arb_mode = 0;
> - l2c_cfg.s.rfb_arb_mode = 0;
> - cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
> + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
> + union cvmx_l2c_ctl l2c_ctl;
> +
> + l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
> + l2c_ctl.s.rsp_arb_mode = 1;
> + l2c_ctl.s.xmc_arb_mode = 0;
> + cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64);
> + } else {
> + union cvmx_l2c_cfg l2c_cfg;
> +
> + l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
> + l2c_cfg.s.lrf_arb_mode = 0;
> + l2c_cfg.s.rfb_arb_mode = 0;
> + cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
> + }
>
> cvmx_pko_initialize_global();
> for (interface = 0; interface < num_interfaces; interface++) {
> --
> 2.47.0
applied to mips-next
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2026-09-26 10:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 7:12 [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Orgad Shaneh
2026-09-15 7:12 ` [PATCH 2/5] MIPS: OCTEON: cvmx-l2c: add the CN66XX L2 geometry Orgad Shaneh
2026-09-26 9:34 ` Thomas Bogendoerfer
2026-09-15 7:12 ` [PATCH 3/5] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II Orgad Shaneh
2026-09-26 9:35 ` Thomas Bogendoerfer
2026-09-15 7:12 ` [PATCH 4/5] MIPS: OCTEON: program L2C_CTL, not L2C_CFG, " Orgad Shaneh
2026-09-26 9:35 ` Thomas Bogendoerfer [this message]
2026-09-15 7:12 ` [PATCH 5/5] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1 Orgad Shaneh
2026-09-26 9:35 ` Thomas Bogendoerfer
2026-09-26 9:34 ` [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Thomas Bogendoerfer
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