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From: sashiko-bot@kernel.org
To: "Guodong Xu" <guodong.xu@oss.qualcomm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v7 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
Date: Tue, 15 Sep 2026 07:43:23 +0000	[thread overview]
Message-ID: <20260915074323.A8FC41F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-rva23u64-hwprobe-v2-v7-9-aa35ebd9ae96@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] riscv: RVA23U64 detection incorrectly requires legacy B extension
- [Medium] riscv: riscv_set_isa_bases couples independent profile evaluations
--

commit e0026c8e3b6f0de96cacfa903bced9ce7509616a
Author: Guodong Xu <guodong.xu@oss.qualcomm.com>

riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection

Introduce a per-hart and host-wide bitmap of conformant ISA "bases", computed
at init time by riscv_init_isa_bases(). Register it as an arch_initcall to
ensure it is evaluated after core_initcall sets up PMLEN features. This allows
subsequent consumers like hwprobe and /proc/cpuinfo to read a consistent cache
of base profiles.

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
[ ... ]
> +static void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
> +{
> +	const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
> +	DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };

[Severity: Medium]
Since ext_mask is initialized once and never cleared, will this cause bits to
accumulate across independent profile checks?

For example, if a future orthogonal base is added later in this function, it
would inherit stale bits like RISCV_ISA_EXT_I and could falsely fail the
bitmap_subset() check.

> +
> +	/* IMA */
> +	__set_bit(RISCV_ISA_EXT_I, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_M, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_A, ext_mask);
> +
> +	if (!bitmap_subset(ext_mask, isa, RISCV_ISA_EXT_MAX))
> +		return;
> +
> +	set_bit(RISCV_ISA_BASE_IMA, bases);
> +
> +	/* RVA23U64 */
> +
> +	/* Supm with PMLEN=7 */
> +	if (!riscv_have_user_pmlen(7))
> +		return;

[Severity: Medium]
Will this early return prevent subsequent profile checks from being evaluated?

If riscv_have_user_pmlen(7) evaluates to false, the function aborts
completely. This seems like it will inadvertently skip the evaluation of any
future bases added after RVA23U64.

> +
> +	__set_bit(RISCV_ISA_EXT_F, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_D, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_C, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_B, ext_mask);

[Severity: High]
Does this incorrectly require the legacy, unratified 'b' extension for
RVA23U64 detection?

When the kernel parses a DT containing the mandated individual Zba, Zbb, and
Zbs extensions but not the legacy 'b' extension, the isa bitmap will not
contain RISCV_ISA_EXT_B. 

Consequently, the bitmap_subset() check below will evaluate to false,
preventing RVA23U64 from being detected on compliant hardware.

> +	__set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
[ ... ]
> +	__set_bit(RISCV_ISA_EXT_SUPM, ext_mask);
> +
> +	if (!bitmap_subset(ext_mask, isa, RISCV_ISA_EXT_MAX))
> +		return;
> +
> +	set_bit(RISCV_ISA_BASE_RVA23U64, bases);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-rva23u64-hwprobe-v2-v7-0-aa35ebd9ae96@oss.qualcomm.com?part=9

  reply	other threads:[~2026-09-15  7:43 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-15  7:15 [PATCH v7 00/11] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-09-15  7:15 ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 01/11] riscv: Add B to hwcap and hwprobe Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 02/11] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 03/11] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 04/11] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 05/11] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 06/11] riscv: dts: spacemit: k1: " Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 07/11] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 08/11] riscv: Add a getter for user PMLEN support Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:43   ` sashiko-bot [this message]
2026-09-15 16:52   ` Conor Dooley
2026-09-15 16:52     ` Conor Dooley
2026-09-16  0:58     ` Guodong Xu
2026-09-16  0:58       ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 10/11] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 11/11] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-09-15  7:15   ` Guodong Xu

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