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From: Conor Dooley <conor@kernel.org>
To: Guodong Xu <guodong.xu@oss.qualcomm.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Chen Wang <chen.wang@linux.dev>,
	Inochi Amaoto <inochiama@gmail.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	devicetree@vger.kernel.org, spacemit@lists.linux.dev,
	sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
	Palmer Dabbelt <palmer@sifive.com>,
	Andy Chiu <tchiu@tenstorrent.com>,
	Florian Weimer <fweimer@redhat.com>,
	Peter Bergner <bergner@oss.tenstorrent.com>,
	Zihong Yao <zihong.plct@isrc.iscas.ac.cn>,
	Mark Harris <mark.hsj@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Andrew Jones <andrew.jones@oss.qualcomm.com>
Subject: Re: [PATCH v7 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
Date: Tue, 15 Sep 2026 17:52:23 +0100	[thread overview]
Message-ID: <20260915-widget-defiling-e22497c228cc@spud> (raw)
In-Reply-To: <20260915-rva23u64-hwprobe-v2-v7-9-aa35ebd9ae96@oss.qualcomm.com>

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On Tue, Sep 15, 2026 at 03:15:35AM -0400, Guodong Xu wrote:
> Introduce a per-hart and host-wide bitmap of conformant ISA "bases"
> (named profile-class sets such as IMA and RVA23U64), computed at init
> time by riscv_init_isa_bases().
> 
> Register riscv_init_isa_bases() as an arch_initcall. That is late
> enough that core_initcall(tagged_addr_init) has probed senvcfg.PMM and
> populated have_user_pmlen_*; without that ordering,
> riscv_have_user_pmlen(7) would still return its default false and the
> RVA23U64 detection path would always bail. It is also early enough that
> arch_initcall_sync(init_hwprobe_vdso_data) finds the bases populated
> when it snapshots the hwprobe values into the vDSO data page.
> 
> Consider this as the cache that subsequent consumers (hwprobe's
> RVA23U64 base behavior bit, /proc/cpuinfo's "isa bases" lines, etc.)
> can read without recomputing, which keeps them consistent with
> each other.
> 
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com>

Something is wrong here with the signoffs here, Drew's probably missing
either authorship or a Co-developed-by tag?

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Guodong Xu <guodong.xu@oss.qualcomm.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Chen Wang <chen.wang@linux.dev>,
	Inochi Amaoto <inochiama@gmail.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	devicetree@vger.kernel.org, spacemit@lists.linux.dev,
	sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
	Palmer Dabbelt <palmer@sifive.com>,
	Andy Chiu <tchiu@tenstorrent.com>,
	Florian Weimer <fweimer@redhat.com>,
	Peter Bergner <bergner@oss.tenstorrent.com>,
	Zihong Yao <zihong.plct@isrc.iscas.ac.cn>,
	Mark Harris <mark.hsj@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Andrew Jones <andrew.jones@oss.qualcomm.com>
Subject: Re: [PATCH v7 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
Date: Tue, 15 Sep 2026 17:52:23 +0100	[thread overview]
Message-ID: <20260915-widget-defiling-e22497c228cc@spud> (raw)
In-Reply-To: <20260915-rva23u64-hwprobe-v2-v7-9-aa35ebd9ae96@oss.qualcomm.com>


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On Tue, Sep 15, 2026 at 03:15:35AM -0400, Guodong Xu wrote:
> Introduce a per-hart and host-wide bitmap of conformant ISA "bases"
> (named profile-class sets such as IMA and RVA23U64), computed at init
> time by riscv_init_isa_bases().
> 
> Register riscv_init_isa_bases() as an arch_initcall. That is late
> enough that core_initcall(tagged_addr_init) has probed senvcfg.PMM and
> populated have_user_pmlen_*; without that ordering,
> riscv_have_user_pmlen(7) would still return its default false and the
> RVA23U64 detection path would always bail. It is also early enough that
> arch_initcall_sync(init_hwprobe_vdso_data) finds the bases populated
> when it snapshots the hwprobe values into the vDSO data page.
> 
> Consider this as the cache that subsequent consumers (hwprobe's
> RVA23U64 base behavior bit, /proc/cpuinfo's "isa bases" lines, etc.)
> can read without recomputing, which keeps them consistent with
> each other.
> 
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com>

Something is wrong here with the signoffs here, Drew's probably missing
either authorship or a Co-developed-by tag?

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  parent reply	other threads:[~2026-09-15 16:52 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-15  7:15 [PATCH v7 00/11] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-09-15  7:15 ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 01/11] riscv: Add B to hwcap and hwprobe Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 02/11] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 03/11] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 04/11] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 05/11] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 06/11] riscv: dts: spacemit: k1: " Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 07/11] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 08/11] riscv: Add a getter for user PMLEN support Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:43   ` sashiko-bot
2026-09-15 16:52   ` Conor Dooley [this message]
2026-09-15 16:52     ` Conor Dooley
2026-09-16  0:58     ` Guodong Xu
2026-09-16  0:58       ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 10/11] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-09-15  7:15   ` Guodong Xu
2026-09-15  7:15 ` [PATCH v7 11/11] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-09-15  7:15   ` Guodong Xu

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