From: Sebastian Ott <sebott@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eauger@redhat.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Alireza Sanaee <alireza.sanaee@huawei.com>,
Richard Henderson <richard.henderson@linaro.org>,
Cornelia Huck <cohuck@redhat.com>,
khushit.shah@nutanix.com
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Sebastian Ott <sebott@redhat.com>
Subject: [PATCH v6 3/3] arm/kvm: get demuxed ID registers from kvm
Date: Wed, 16 Sep 2026 18:51:17 +0200 [thread overview]
Message-ID: <20260916165117.39764-4-sebott@redhat.com> (raw)
In-Reply-To: <20260916165117.39764-1-sebott@redhat.com>
From: Cornelia Huck <cohuck@redhat.com>
We now have the infrastructure in place to handle demuxed ID registers
from kvm. Use it to get the values that kvm emulates for CCSIDR_EL1.
Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Sebastian Ott <sebott@redhat.com>
---
target/arm/kvm.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index ed99be7fd8..e4ef11945e 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -244,6 +244,44 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf,
return ret;
}
+
+/* CSSELR values supported by kvm; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
+#define KVM_CSSELR_MAX 14
+/*
+ * QEMU historically supported CSSELR values 0..15. This difference doen't matter
+ * since CSSELR_EL1.Level == 0b111 is reserved and thus CSSELR values 14..15 will
+ * make CCSIDR read as zero. Larger CSSELR values will only be necessary when
+ * support for MTE Allocation Tag caches is added.
+ */
+#define QEMU_CSSELR_MAX 16
+
+static int get_host_cpu_reg_demux(int fd, ARMHostCPUFeatures *ahcf,
+ ARMIDRegisterIdx index, int subindex)
+{
+
+ struct kvm_one_reg one_reg = {
+ .id = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX,
+ };
+
+ switch (index) {
+ case CCSIDR_EL1_IDX:
+ if (subindex >= QEMU_CSSELR_MAX) {
+ return -EINVAL;
+ } else if (subindex >= KVM_CSSELR_MAX) {
+ /* CSSELR_EL1.Level == 0b111 is reserved. */
+ ahcf->isar.idregs[index + subindex] = 0;
+ return 0;
+ }
+ one_reg.id |= KVM_REG_ARM_DEMUX_ID_CCSIDR | subindex;
+ one_reg.addr = (uintptr_t)&ahcf->isar.idregs[index + subindex];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ioctl(fd, KVM_GET_ONE_REG, &one_reg);
+}
+
static uint32_t kvm_arm_sve_get_vls(int fd)
{
uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
@@ -454,6 +492,10 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
/* Read the set of supported vector lengths. */
arm_host_cpu_features.sve_vq_supported = kvm_arm_sve_get_vls(fd);
}
+ /* Grab demuxed registers. */
+ for (int i = 0; i < QEMU_CSSELR_MAX; i++) {
+ err |= get_host_cpu_reg_demux(fd, ahcf, CCSIDR_EL1_IDX, i);
+ }
}
kvm_arm_destroy_scratch_host_vcpu(fdarray);
--
2.55.0
next prev parent reply other threads:[~2026-09-16 16:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 16:51 [PATCH v6 0/3] arm: demuxed ID registers (CCSIDR_EL1) Sebastian Ott
2026-09-16 16:51 ` [PATCH v6 1/3] arm: handle demuxed ID registers Sebastian Ott
2026-09-16 16:51 ` [PATCH v6 2/3] arm: handle CCSIDR_EL1 as a demuxed register Sebastian Ott
2026-09-16 16:51 ` Sebastian Ott [this message]
2026-09-28 13:47 ` [PATCH v6 0/3] arm: demuxed ID registers (CCSIDR_EL1) Peter Maydell
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