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From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org,
	neil.armstrong@linaro.org, conor+dt@kernel.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord
Date: Wed, 16 Sep 2026 18:47:01 +0000	[thread overview]
Message-ID: <20260916184702.2D2381F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260916-nord-usb-phy-v2-3-2c8461bb30e6@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] phy: qcom: mismatch between commit message and nord_usb3_tx_tbl
--

commit 1b7c23f467a9a0ffe85f80b15fdee3ce3ad5c895
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences
are identical to sm8550, but the sub-blocks are not laid out the same way.
A dedicated USB3_PCS_AON region at offset 0x1e00 is added, modifying how
the I/O clamp is driven.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index a4f130fc33e39..c4e88b0384cb5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -2356,6 +2356,20 @@ static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
>  	QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
>  };
>  
> +static const struct qmp_phy_init_tbl nord_usb3_tx_tbl[] = {
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x14),

[Severity: Medium]
The commit message claims that the initialization sequences are identical to
sm8550. However, this configures QSERDES_V6_TX_RCV_DETECT_LVL_2 to 0x14,
whereas sm8550 uses 0x12.

Is this an intentional hardware difference for Nord that should be mentioned
in the commit message, or is it an accidental typo?

> +	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
> +	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916-nord-usb-phy-v2-0-2c8461bb30e6@oss.qualcomm.com?part=3

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org,
	neil.armstrong@linaro.org, conor+dt@kernel.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord
Date: Wed, 16 Sep 2026 18:47:01 +0000	[thread overview]
Message-ID: <20260916184702.2D2381F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260916-nord-usb-phy-v2-3-2c8461bb30e6@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] phy: qcom: mismatch between commit message and nord_usb3_tx_tbl
--

commit 1b7c23f467a9a0ffe85f80b15fdee3ce3ad5c895
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences
are identical to sm8550, but the sub-blocks are not laid out the same way.
A dedicated USB3_PCS_AON region at offset 0x1e00 is added, modifying how
the I/O clamp is driven.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index a4f130fc33e39..c4e88b0384cb5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -2356,6 +2356,20 @@ static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
>  	QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
>  };
>  
> +static const struct qmp_phy_init_tbl nord_usb3_tx_tbl[] = {
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x14),

[Severity: Medium]
The commit message claims that the initialization sequences are identical to
sm8550. However, this configures QSERDES_V6_TX_RCV_DETECT_LVL_2 to 0x14,
whereas sm8550 uses 0x12.

Is this an intentional hardware difference for Nord that should be mentioned
in the commit message, or is it an accidental typo?

> +	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
> +	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916-nord-usb-phy-v2-0-2c8461bb30e6@oss.qualcomm.com?part=3

  reply	other threads:[~2026-09-16 18:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-16 18:30 [PATCH v2 0/3] phy: qcom: Add USB PHY support for Nord SoC Bartosz Golaszewski
2026-09-16 18:30 ` Bartosz Golaszewski
2026-09-16 18:30 ` [PATCH v2 1/3] dt-bindings: phy: qcom,snps-eusb2-phy: Document the Nord eUSB2 PHY Bartosz Golaszewski
2026-09-16 18:30   ` Bartosz Golaszewski
2026-09-16 18:36   ` sashiko-bot
2026-09-16 18:36     ` sashiko-bot
2026-09-18 10:24   ` Krzysztof Kozlowski
2026-09-18 10:24     ` Krzysztof Kozlowski
2026-09-16 18:30 ` [PATCH v2 2/3] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document the Nord QMP PHY Bartosz Golaszewski
2026-09-16 18:30   ` Bartosz Golaszewski
2026-09-16 18:30 ` [PATCH v2 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord Bartosz Golaszewski
2026-09-16 18:30   ` Bartosz Golaszewski
2026-09-16 18:47   ` sashiko-bot [this message]
2026-09-16 18:47     ` sashiko-bot

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