From: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org,
bmasney+clk@redhat.com, jbrunet+clk@baylibre.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
srinivas.kandagatla@oss.qualcomm.com,
sarath.ganapathiraju@oss.qualcomm.com
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
prasad.kumpatla@oss.qualcomm.com
Subject: [PATCH v8 0/2] Add LPASS VA CSR HeartBeat pulse clock support
Date: Thu, 17 Sep 2026 19:27:13 +0530 [thread overview]
Message-ID: <20260917-master-v8-0-823d2c5d090a@oss.qualcomm.com> (raw)
The LPASS VA CSR block contains rate generator hardware that produces
a HeartBeat Pulse (also known as RateGen Pulse). This pulse
synchronizes the start of the DMAs and Codec Interfaces for the audio
usecases and can serve as a periodic wakeup source for the DSP.
This series adds the DT binding and driver support to model this
rate generator as a clock provider.
Patch 1 adds the YAML binding for the new qcom,hawi-lpass-va-csr
clock provider node under Documentation/devicetree/bindings/clock/.
Patch 2 adds the lpass-va-csr driver under drivers/clk/qcom that
registers the lpass_heartbeat_pulse clock and enables/disables the
rate generator via regmap when the clock consumer requests it.
Changes in v8:
- Rebase the series on linux-next next-20260916.
- Require the LPASS LPR and audio vote clocks to access VA CSR
register space safely.
- Attach the DT vote clocks to runtime PM and resume the device before
programming the rate generator registers.
- Program the counter and delay registers once during probe.
- Use qcom's simple regmap gate ops for the enable bit (Srinivas).
- Drop the unreachable of_device_get_match_data() NULL check (Srinivas).
- Drop stale Reviewed-by/Tested-by tags after the binding and driver
changes.
- Link to v7: https://patch.msgid.link/20260831-heartbeat-v7-next-20260828-v7-0-e3ffeac46a51@oss.qualcomm.com
Changes in v7:
- Rebase the series on linux-next next-20260828.
- Add Prasad's Reviewed-by and Tested-by tags to patch 2.
- Link to v6: https://patch.msgid.link/20260821-heartbeat-v6-next-20260821-send-v6-0-62c5df84ce21@oss.qualcomm.com
Changes in v6:
- Rebase the series on linux-next next-20260821.
- Capitalize Hawi in binding text (Bjorn).
- Simplify the binding example by removing the soc wrapper and
two-cell address/size setup (Bjorn).
- Keep the full VA CSR register window in the binding and describe it
as the VA CSR register block after Konrad clarified the earlier
register-range concern (Bjorn, Konrad).
- Link to v5: https://patch.msgid.link/20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com
Changes in v5:
- Add explicit ARM64 Kconfig gating and Qualcomm default-module policy
for QCOM_CLK_LPASS_HEARTBEAT_PULSE to align with nearby qcom clock
entries.
- Link to v4: https://patch.msgid.link/20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com
Changes in v4:
- Rename the binding filename and schema ID to hawi-specific naming:
qcom,lpass-va-csr.yaml -> qcom,hawi-lpass-va-csr.yaml (Krzysztof).
- Rename Kconfig symbol QCOM_CLK_LPASS_VA_CSR to
QCOM_CLK_LPASS_HEARTBEAT_PULSE (Konrad).
- Add devm_pm_runtime_enable() in the lpass-va-csr probe path.
- Drop the qcom,lpass-va-macro binding extension patch; it will be
resubmitted with the Hawi DTSI changes.
- Drop sound/soc/codecs/Kconfig select wiring to keep this series
clock-only (Konrad).
- Link to v3: https://lore.kernel.org/all/20260723-master-v3-0-3d67b79b0515@oss.qualcomm.com/
Changes in v3:
- Move the qcom,lpass-va-csr binding under
Documentation/devicetree/bindings/clock/ (Krzysztof).
- Move the driver under drivers/clk/qcom/ (Krzysztof).
- Improve the schema description and use generic clock-controller node
naming (Krzysztof).
- Use additionalProperties: false and keep compatibles sorted.
Changes in v2:
- Split the qcom,lpass-va-csr and qcom,lpass-va-macro bindings into
separate patches.
Changes in v1:
- Initial version
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
Sarath Ganapathiraju (2):
dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
clk: qcom: Add LPASS VA CSR heartbeat pulse clock
.../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 62 +++++++++
drivers/clk/qcom/Kconfig | 14 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpass-va-csr.c | 140 +++++++++++++++++++++
4 files changed, 217 insertions(+)
---
base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1
change-id: 20260917-master-6c2778f57a9a
Best regards,
--
Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Sarath Ganapathiraju via B4 Relay <devnull+sarath.ganapathiraju.oss.qualcomm.com@kernel.org>
To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org,
bmasney+clk@redhat.com, jbrunet+clk@baylibre.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
srinivas.kandagatla@oss.qualcomm.com,
sarath.ganapathiraju@oss.qualcomm.com
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
prasad.kumpatla@oss.qualcomm.com
Subject: [PATCH v8 0/2] Add LPASS VA CSR HeartBeat pulse clock support
Date: Thu, 17 Sep 2026 19:27:13 +0530 [thread overview]
Message-ID: <20260917-master-v8-0-823d2c5d090a@oss.qualcomm.com> (raw)
The LPASS VA CSR block contains rate generator hardware that produces
a HeartBeat Pulse (also known as RateGen Pulse). This pulse
synchronizes the start of the DMAs and Codec Interfaces for the audio
usecases and can serve as a periodic wakeup source for the DSP.
This series adds the DT binding and driver support to model this
rate generator as a clock provider.
Patch 1 adds the YAML binding for the new qcom,hawi-lpass-va-csr
clock provider node under Documentation/devicetree/bindings/clock/.
Patch 2 adds the lpass-va-csr driver under drivers/clk/qcom that
registers the lpass_heartbeat_pulse clock and enables/disables the
rate generator via regmap when the clock consumer requests it.
Changes in v8:
- Rebase the series on linux-next next-20260916.
- Require the LPASS LPR and audio vote clocks to access VA CSR
register space safely.
- Attach the DT vote clocks to runtime PM and resume the device before
programming the rate generator registers.
- Program the counter and delay registers once during probe.
- Use qcom's simple regmap gate ops for the enable bit (Srinivas).
- Drop the unreachable of_device_get_match_data() NULL check (Srinivas).
- Drop stale Reviewed-by/Tested-by tags after the binding and driver
changes.
- Link to v7: https://patch.msgid.link/20260831-heartbeat-v7-next-20260828-v7-0-e3ffeac46a51@oss.qualcomm.com
Changes in v7:
- Rebase the series on linux-next next-20260828.
- Add Prasad's Reviewed-by and Tested-by tags to patch 2.
- Link to v6: https://patch.msgid.link/20260821-heartbeat-v6-next-20260821-send-v6-0-62c5df84ce21@oss.qualcomm.com
Changes in v6:
- Rebase the series on linux-next next-20260821.
- Capitalize Hawi in binding text (Bjorn).
- Simplify the binding example by removing the soc wrapper and
two-cell address/size setup (Bjorn).
- Keep the full VA CSR register window in the binding and describe it
as the VA CSR register block after Konrad clarified the earlier
register-range concern (Bjorn, Konrad).
- Link to v5: https://patch.msgid.link/20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com
Changes in v5:
- Add explicit ARM64 Kconfig gating and Qualcomm default-module policy
for QCOM_CLK_LPASS_HEARTBEAT_PULSE to align with nearby qcom clock
entries.
- Link to v4: https://patch.msgid.link/20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com
Changes in v4:
- Rename the binding filename and schema ID to hawi-specific naming:
qcom,lpass-va-csr.yaml -> qcom,hawi-lpass-va-csr.yaml (Krzysztof).
- Rename Kconfig symbol QCOM_CLK_LPASS_VA_CSR to
QCOM_CLK_LPASS_HEARTBEAT_PULSE (Konrad).
- Add devm_pm_runtime_enable() in the lpass-va-csr probe path.
- Drop the qcom,lpass-va-macro binding extension patch; it will be
resubmitted with the Hawi DTSI changes.
- Drop sound/soc/codecs/Kconfig select wiring to keep this series
clock-only (Konrad).
- Link to v3: https://lore.kernel.org/all/20260723-master-v3-0-3d67b79b0515@oss.qualcomm.com/
Changes in v3:
- Move the qcom,lpass-va-csr binding under
Documentation/devicetree/bindings/clock/ (Krzysztof).
- Move the driver under drivers/clk/qcom/ (Krzysztof).
- Improve the schema description and use generic clock-controller node
naming (Krzysztof).
- Use additionalProperties: false and keep compatibles sorted.
Changes in v2:
- Split the qcom,lpass-va-csr and qcom,lpass-va-macro bindings into
separate patches.
Changes in v1:
- Initial version
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
Sarath Ganapathiraju (2):
dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
clk: qcom: Add LPASS VA CSR heartbeat pulse clock
.../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 62 +++++++++
drivers/clk/qcom/Kconfig | 14 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpass-va-csr.c | 140 +++++++++++++++++++++
4 files changed, 217 insertions(+)
---
base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1
change-id: 20260917-master-6c2778f57a9a
Best regards,
--
Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
next reply other threads:[~2026-09-17 13:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 13:57 Sarath Ganapathiraju [this message]
2026-09-17 13:57 ` [PATCH v8 0/2] Add LPASS VA CSR HeartBeat pulse clock support Sarath Ganapathiraju via B4 Relay
2026-09-17 13:57 ` [PATCH v8 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock Sarath Ganapathiraju
2026-09-17 13:57 ` Sarath Ganapathiraju via B4 Relay
2026-09-28 18:00 ` Rob Herring (Arm)
2026-09-17 13:57 ` [PATCH v8 2/2] clk: qcom: Add LPASS VA CSR heartbeat " Sarath Ganapathiraju
2026-09-17 13:57 ` Sarath Ganapathiraju via B4 Relay
2026-09-17 14:07 ` sashiko-bot
2026-09-17 16:08 ` Srinivas Kandagatla
2026-09-18 4:40 ` Prasad Kumpatla
2026-09-18 9:50 ` Konrad Dybcio
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