From: sashiko-bot@kernel.org
To: "Yize Wang" <wangyize7@huawei.com>
Cc: "Oliver Upton" <oupton@kernel.org>,
"Marc Zyngier" <maz@kernel.org>,
kvmarm@lists.linux.dev
Subject: Re: [PATCH 1/2] KVM: arm64: Add batch group constant and data structure to UAPI header
Date: Fri, 18 Sep 2026 08:27:40 +0000 [thread overview]
Message-ID: <20260918082740.9E2A51F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260918081930.4014735-2-wangyize7@huawei.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] kvm: arm64: implicit padding hole in UAPI struct kvm_dev_arm_vgic_batch_entry
--
commit 54edd6d460b56fe24bcc0c18ebb7ce4904b10a69
Author: Yize Wang <wangyize7@huawei.com>
KVM: arm64: Add batch group constant and data structure to UAPI header
Add KVM_DEV_ARM_VGIC_GRP_BATCH_REGS group ID, KVM_DEV_ARM_VGIC_BATCH_MAX
limit, and struct kvm_dev_arm_vgic_batch_entry for batch VGIC register
access. These UAPI definitions allow userspace to read/write multiple
VGIC registers in a single ioctl call.
> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> index 019e5e3d892e6..f84530274edd4 100644
> --- a/arch/arm64/include/uapi/asm/kvm.h
> +++ b/arch/arm64/include/uapi/asm/kvm.h
[ ... ]
> @@ -418,12 +418,22 @@ enum {
> #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
> #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
> #define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9
> +#define KVM_DEV_ARM_VGIC_GRP_BATCH_REGS 10
> #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
> #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
> (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
> #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
> #define VGIC_LEVEL_INFO_LINE_LEVEL 0
>
> +#define KVM_DEV_ARM_VGIC_BATCH_MAX 4096
> +#define KVM_DEV_ARM_VGIC_ATTR_FLAG_LOCKED 12
> +struct kvm_dev_arm_vgic_batch_entry {
> + __u32 group;
> + __u64 attr;
[Severity: Low]
Does this struct layout introduce a 4-byte implicit padding hole between
the group and attr fields?
This layout appears to violate UAPI design guidelines, which strictly forbid
implicit padding to prevent ABI sizing mismatches and potential information
leaks.
While the kernel currently never copies the structure array back to userspace
(it only writes to val directly via put_user), and 64-bit integers are aligned
to 8 bytes on ARM32 compat (avoiding an immediate sizing mismatch), defining
this structure permanently exposes the flawed layout to userspace.
Could explicit padding be added or the fields reordered to ensure the
layout is perfectly packed without implicit holes?
> + __u32 val;
> + __s32 error;
> +};
> +
> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
> #define KVM_DEV_ARM_ITS_SAVE_TABLES 1
> #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260918081930.4014735-1-wangyize7@huawei.com?part=1
next prev parent reply other threads:[~2026-09-18 8:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-18 8:18 [PATCH 0/2] Batch register access for live migration optimization Yize Wang
2026-09-18 8:18 ` [PATCH 1/2] KVM: arm64: Add batch group constant and data structure to UAPI header Yize Wang
2026-09-18 8:27 ` sashiko-bot [this message]
2026-09-18 8:18 ` [PATCH 2/2] KVM: arm64: Add VGIC v3 batch register access implementation Yize Wang
2026-09-18 8:33 ` sashiko-bot
2026-09-18 12:08 ` [PATCH 0/2] Batch register access for live migration optimization Marc Zyngier
2026-09-20 12:12 ` [RESEND][PATCH " Yize Wang
2026-09-23 7:57 ` Yize Wang
[not found] ` <f70c6fe3-e3c5-4912-b4bb-8a418fec4346@huawei.com>
2026-10-03 14:53 ` [PATCH " Marc Zyngier
2026-10-08 8:32 ` Yize Wang
2026-10-08 12:50 ` [RESEND][PATCH " Yize Wang
2026-10-12 11:04 ` Yize Wang
2026-10-12 11:31 ` Marc Zyngier
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