Re: [PATCH v4 6/6] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Unused static array variables due to macro typo
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commit 426e06547f75580c252f2935af9323cd36b0aced
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support

This commit adds support for the Nord Gen5x16 bifurcated QMP PCIe PHY. It
adds configurations for x16, x8+x8, x8+x4+x4, and x8+x4+x2+x2 lane modes,
along with register programming and power sequencing.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
[ ... ]
> +static const char * const nord_pciephy_port_a_nocsr_reset_l[] = {
> +	"port_a_nocsr",
> +};
> +
> +static const char * const nord_pciephy_port_b_nocsr_reset_l[] = {
> +	"port_b_nocsr",
> +};
[ ... ]
> +NORD_QMP_PCIE_PORT_CFG(a, pciephy_port_a_reg_l, nord_pciephy_port_a_pd_l,
> +		       nord_pciephy_port_a_reset_l, pciephy_port_a_nocsr_reset_l,
> +		       nord_pciephy_port_a_pipeclk_l, true);
> +NORD_QMP_PCIE_PORT_CFG(b, pciephy_port_b_reg_l, nord_pciephy_port_b_pd_l,
> +		       nord_pciephy_port_b_reset_l, pciephy_port_b_nocsr_reset_l,
> +		       nord_pciephy_port_b_pipeclk_l, true);

[Severity: Low]
Does this code accidentally pass pciephy_port_a_nocsr_reset_l instead of
nord_pciephy_port_a_nocsr_reset_l into the NORD_QMP_PCIE_PORT_CFG macro for
port a (and similarly for port b)?

This leaves the newly defined nord_pciephy_port_a_nocsr_reset_l and
nord_pciephy_port_b_nocsr_reset_l static arrays entirely unused.

This will trigger a -Wunused-variable compiler warning, which can cause
build failures when compiling the kernel with -Werror.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260921-nord-v4-0-ed05c6e09240@oss.qualcomm.com?part=6