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From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: conor+dt@kernel.org, robh@kernel.org, neil.armstrong@linaro.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org,
	vkoul@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord
Date: Mon, 21 Sep 2026 11:55:07 +0000	[thread overview]
Message-ID: <20260921115508.592601F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260921-nord-usb-phy-v3-3-68aa02b12b96@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Meaningful code and commit message mismatch for nord_usb3_tx_tbl
--

commit 463808de5f918fa656e070bb28cb3c49135072fb
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

This commit adds USB3+DP combo PHY support for the Nord SoC, introducing a
new layout offset table (v6) to handle its dedicated USB3_PCS_AON region.

>     Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences
>     are identical to sm8550, but the sub-blocks are not laid out the same way:

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index a4f130fc33e39..c4e88b0384cb5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
[ ... ]
> @@ -2356,6 +2356,20 @@ static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
>  	QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
>  };
>  
> +static const struct qmp_phy_init_tbl nord_usb3_tx_tbl[] = {
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x14),

[Severity: Medium]
Is this value intentional? The commit message explicitly claims that the
initialisation sequences for Nord are "identical to sm8550". However, the
sm8550 equivalent uses 0x12 for QSERDES_V6_TX_RCV_DETECT_LVL_2, whereas
nord_usb3_tx_tbl sets it to 0x14.

Does the commit message need to be updated to document an intentional
hardware tweak for Nord, or is this value a typo?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260921-nord-usb-phy-v3-0-68aa02b12b96@oss.qualcomm.com?part=3

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: conor+dt@kernel.org, robh@kernel.org, neil.armstrong@linaro.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org,
	vkoul@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord
Date: Mon, 21 Sep 2026 11:55:07 +0000	[thread overview]
Message-ID: <20260921115508.592601F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260921-nord-usb-phy-v3-3-68aa02b12b96@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Meaningful code and commit message mismatch for nord_usb3_tx_tbl
--

commit 463808de5f918fa656e070bb28cb3c49135072fb
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

This commit adds USB3+DP combo PHY support for the Nord SoC, introducing a
new layout offset table (v6) to handle its dedicated USB3_PCS_AON region.

>     Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences
>     are identical to sm8550, but the sub-blocks are not laid out the same way:

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index a4f130fc33e39..c4e88b0384cb5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
[ ... ]
> @@ -2356,6 +2356,20 @@ static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
>  	QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
>  };
>  
> +static const struct qmp_phy_init_tbl nord_usb3_tx_tbl[] = {
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x14),

[Severity: Medium]
Is this value intentional? The commit message explicitly claims that the
initialisation sequences for Nord are "identical to sm8550". However, the
sm8550 equivalent uses 0x12 for QSERDES_V6_TX_RCV_DETECT_LVL_2, whereas
nord_usb3_tx_tbl sets it to 0x14.

Does the commit message need to be updated to document an intentional
hardware tweak for Nord, or is this value a typo?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260921-nord-usb-phy-v3-0-68aa02b12b96@oss.qualcomm.com?part=3

  reply	other threads:[~2026-09-21 11:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-21 11:47 [PATCH v3 0/3] phy: qcom: Add USB PHY support for Nord SoC Bartosz Golaszewski
2026-09-21 11:47 ` Bartosz Golaszewski
2026-09-21 11:47 ` [PATCH v3 1/3] dt-bindings: phy: qcom,snps-eusb2-phy: Document the Nord eUSB2 PHY Bartosz Golaszewski
2026-09-21 11:47   ` Bartosz Golaszewski
2026-09-25 13:23   ` Krzysztof Kozlowski
2026-09-25 13:23     ` Krzysztof Kozlowski
2026-09-21 11:47 ` [PATCH v3 2/3] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document the Nord QMP PHY Bartosz Golaszewski
2026-09-21 11:47   ` Bartosz Golaszewski
2026-09-21 11:47 ` [PATCH v3 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord Bartosz Golaszewski
2026-09-21 11:47   ` Bartosz Golaszewski
2026-09-21 11:55   ` sashiko-bot [this message]
2026-09-21 11:55     ` sashiko-bot
2026-09-25 15:55 ` [PATCH v3 0/3] phy: qcom: Add USB PHY support for Nord SoC Manivannan Sadhasivam
2026-09-25 15:55   ` Manivannan Sadhasivam
2026-10-03  9:36 ` Vinod Koul
2026-10-03  9:36   ` Vinod Koul

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