From: Igor Paunovic <royalnet026@gmail.com>
To: Tomeu Vizoso <tomeu@tomeuvizoso.net>,
Oded Gabbay <ogabbay@kernel.org>,
Heiko Stuebner <heiko@sntech.de>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Jeff Hugo" <jeff.hugo@oss.qualcomm.com>,
"Robert Foss" <rfoss@kernel.org>,
"Sidong Yang" <sidong.yang@furiosa.ai>,
"Diederik de Haas" <diederik@cknow-tech.com>,
"Sebastian Reichel" <sebastian.reichel@collabora.com>,
"Jiaxing Hu" <gahing@gahingwoo.com>,
"Nicolas Dufresne" <nicolas@ndufresne.ca>,
"Jonas Karlman" <jonas@kwiboo.se>,
"Guangshuo Li" <lgs201920130244@gmail.com>,
"Hüseyin BIYIK" <boogiepop@gmx.com>,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Igor Paunovic" <royalnet026@gmail.com>
Subject: [PATCH v2 06/11] dt-bindings: npu: rockchip: allow DVFS and thermal properties
Date: Tue, 22 Sep 2026 10:01:09 +0200 [thread overview]
Message-ID: <20260922080114.44662-7-royalnet026@gmail.com> (raw)
In-Reply-To: <20260922080114.44662-1-royalnet026@gmail.com>
The three NPU cores on the RK3588 are fed by a single clock and a single
supply, and the firmware accepts a fixed set of rates for that clock.
Describing those rates as an operating-points-v2 table is what lets a
driver scale the NPU instead of leaving it at whatever rate the bootloader
set, so allow the property on the core node.
Throttling the NPU from a thermal zone needs a core node to be usable as
a cooling device, so allow #cooling-cells too.
The OPP table belongs on every core, with opp-shared: the cores have no
clock of their own, and one shared table for one shared clock is the same
shape a CPU cluster uses. #cooling-cells goes on one core only, the one a
thermal zone's cooling map names, because the cores cannot be throttled
independently. Naming one representative node for a shared frequency
domain is the established shape, as in "Cpufreq cooling device on CPU0"
in Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
The schema cannot enforce which core carries #cooling-cells, because all
three cores share a compatible string and a node name pattern, so that
stays a devicetree convention. That is the same situation as for CPU
cooling, where cpus.yaml does not restrict #cooling-cells to cpu@0
either.
The example gains #cooling-cells; the operating-points-v2 property is
exercised by the RK3588 devicetree later in this series.
Assisted-by: LLM checkpatch dt_binding_check
Signed-off-by: Igor Paunovic <royalnet026@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v2: the text on where the properties go is rewritten for opp-shared on
all three cores, following Nicolas Dufresne's review of v1 3/7. The
only change to the schema file is the wording of the #cooling-cells
description; the constraints and the example are unchanged. Conor, your
Ack is kept on that basis; please say if it no longer holds.
.../bindings/npu/rockchip,rk3588-rknn-core.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
index caca2a4903cd1..beba1896156f5 100644
--- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
+++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
@@ -42,6 +42,13 @@ properties:
- const: npu
- const: pclk
+ "#cooling-cells":
+ description:
+ Present on one core only, the first, which stands for the shared NPU
+ clock as a cooling device. The other cores have no clock of their own
+ and cannot be throttled independently of it.
+ const: 2
+
interrupts:
maxItems: 1
@@ -50,6 +57,8 @@ properties:
npu-supply: true
+ operating-points-v2: true
+
power-domains:
maxItems: 1
@@ -100,6 +109,7 @@ examples:
clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
<&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
clock-names = "aclk", "hclk", "npu", "pclk";
+ #cooling-cells = <2>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&rknn_mmu_0>;
npu-supply = <&vdd_npu_s0>;
--
2.43.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Igor Paunovic <royalnet026@gmail.com>
To: Tomeu Vizoso <tomeu@tomeuvizoso.net>,
Oded Gabbay <ogabbay@kernel.org>,
Heiko Stuebner <heiko@sntech.de>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Jeff Hugo" <jeff.hugo@oss.qualcomm.com>,
"Robert Foss" <rfoss@kernel.org>,
"Sidong Yang" <sidong.yang@furiosa.ai>,
"Diederik de Haas" <diederik@cknow-tech.com>,
"Sebastian Reichel" <sebastian.reichel@collabora.com>,
"Jiaxing Hu" <gahing@gahingwoo.com>,
"Nicolas Dufresne" <nicolas@ndufresne.ca>,
"Jonas Karlman" <jonas@kwiboo.se>,
"Guangshuo Li" <lgs201920130244@gmail.com>,
"Hüseyin BIYIK" <boogiepop@gmx.com>,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Igor Paunovic" <royalnet026@gmail.com>
Subject: [PATCH v2 06/11] dt-bindings: npu: rockchip: allow DVFS and thermal properties
Date: Tue, 22 Sep 2026 10:01:09 +0200 [thread overview]
Message-ID: <20260922080114.44662-7-royalnet026@gmail.com> (raw)
In-Reply-To: <20260922080114.44662-1-royalnet026@gmail.com>
The three NPU cores on the RK3588 are fed by a single clock and a single
supply, and the firmware accepts a fixed set of rates for that clock.
Describing those rates as an operating-points-v2 table is what lets a
driver scale the NPU instead of leaving it at whatever rate the bootloader
set, so allow the property on the core node.
Throttling the NPU from a thermal zone needs a core node to be usable as
a cooling device, so allow #cooling-cells too.
The OPP table belongs on every core, with opp-shared: the cores have no
clock of their own, and one shared table for one shared clock is the same
shape a CPU cluster uses. #cooling-cells goes on one core only, the one a
thermal zone's cooling map names, because the cores cannot be throttled
independently. Naming one representative node for a shared frequency
domain is the established shape, as in "Cpufreq cooling device on CPU0"
in Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
The schema cannot enforce which core carries #cooling-cells, because all
three cores share a compatible string and a node name pattern, so that
stays a devicetree convention. That is the same situation as for CPU
cooling, where cpus.yaml does not restrict #cooling-cells to cpu@0
either.
The example gains #cooling-cells; the operating-points-v2 property is
exercised by the RK3588 devicetree later in this series.
Assisted-by: LLM checkpatch dt_binding_check
Signed-off-by: Igor Paunovic <royalnet026@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v2: the text on where the properties go is rewritten for opp-shared on
all three cores, following Nicolas Dufresne's review of v1 3/7. The
only change to the schema file is the wording of the #cooling-cells
description; the constraints and the example are unchanged. Conor, your
Ack is kept on that basis; please say if it no longer holds.
.../bindings/npu/rockchip,rk3588-rknn-core.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
index caca2a4903cd1..beba1896156f5 100644
--- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
+++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
@@ -42,6 +42,13 @@ properties:
- const: npu
- const: pclk
+ "#cooling-cells":
+ description:
+ Present on one core only, the first, which stands for the shared NPU
+ clock as a cooling device. The other cores have no clock of their own
+ and cannot be throttled independently of it.
+ const: 2
+
interrupts:
maxItems: 1
@@ -50,6 +57,8 @@ properties:
npu-supply: true
+ operating-points-v2: true
+
power-domains:
maxItems: 1
@@ -100,6 +109,7 @@ examples:
clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
<&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
clock-names = "aclk", "hclk", "npu", "pclk";
+ #cooling-cells = <2>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&rknn_mmu_0>;
npu-supply = <&vdd_npu_s0>;
--
2.43.0
next prev parent reply other threads:[~2026-09-22 8:02 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 8:01 [PATCH v2 00/11] accel/rocket: DVFS for the RK3588 NPU Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 01/11] accel/rocket: search every core slot when a core is removed Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 02/11] accel/rocket: number the cores by devicetree position, not bind order Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 03/11] accel/rocket: search every core slot when looking up a scheduler Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 04/11] accel/rocket: keep core slots stable across unbind and rebind Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 05/11] accel/rocket: request the core clocks by name Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic [this message]
2026-09-22 8:01 ` [PATCH v2 06/11] dt-bindings: npu: rockchip: allow DVFS and thermal properties Igor Paunovic
2026-09-22 16:06 ` Rob Herring
2026-09-22 16:06 ` Rob Herring
2026-09-23 8:57 ` Igor Paunovic
2026-09-23 8:57 ` Igor Paunovic
2026-09-23 9:15 ` Diederik de Haas
2026-09-23 9:15 ` Diederik de Haas
2026-09-23 9:43 ` Igor Paunovic
2026-09-23 9:43 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 07/11] arm64: dts: rockchip: rk3588: add an OPP table for the NPU Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 08/11] accel/rocket: restore the NPU clock boot rate before powering the cores down Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:13 ` sashiko-bot
2026-09-22 8:55 ` Igor Paunovic
2026-09-22 8:55 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 09/11] accel/rocket: add devfreq support Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:18 ` sashiko-bot
2026-09-22 8:56 ` Igor Paunovic
2026-09-22 8:56 ` Igor Paunovic
2026-09-23 13:14 ` Sidong Yang
2026-09-23 13:14 ` Sidong Yang
2026-09-23 14:26 ` Igor Paunovic
2026-09-23 14:26 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 10/11] accel/rocket: register a devfreq cooling device Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-22 8:01 ` [PATCH v2 11/11] arm64: dts: rockchip: rk3588: add passive cooling to the NPU thermal zone Igor Paunovic
2026-09-22 8:01 ` Igor Paunovic
2026-09-23 19:29 ` [PATCH v2 00/11] accel/rocket: DVFS for the RK3588 NPU Nicolas Dufresne
2026-09-23 19:29 ` Nicolas Dufresne
2026-09-23 19:54 ` Igor Paunovic
2026-09-23 19:54 ` Igor Paunovic
2026-09-24 5:37 ` Tomeu Vizoso
2026-09-24 5:37 ` Tomeu Vizoso
2026-09-24 7:36 ` Igor Paunovic
2026-09-24 7:36 ` Igor Paunovic
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