[PATCH i-g-t v5 0/5] Add BO Allocation and VM Bind stress infra

[PATCH i-g-t v5 0/5] Add BO Allocation and VM Bind stress infra

[Sobin Thomas]

This series adds the base BO allocation infra for excercising Xe VM
Bind/Unbind with varying BO Sizes and execution workloads 

This infra supports individual and array VM binds, random sized BO
allocation , threaded execution across engines, unaligned VA access and
leak/eviction scenarios

Sobin Thomas (5):
  tests/intel: add BO allocation stress coverage
  tests/intel: Add random-size BO leak tests
  tests/intel: Add array-of-binds random-size allocation tests
  tests/intel: Add threaded random-size allocation stress tests
  tests/intel: Add oversubscribe concurrent bind stress subtest

 tests/intel/xe_bo_alloc.c | 1557 +++++++++++++++++++++++++++++++++++++
 tests/meson.build         |    1 +
 2 files changed, 1558 insertions(+)
 create mode 100644 tests/intel/xe_bo_alloc.c

-- 
2.52.0

[PATCH i-g-t v5 1/5] tests/intel: add BO allocation stress coverage

[Sobin Thomas]

Add a new xe_bo_alloc test excercising BO allocation, VM bind, mapping and execution
across a range of BO sizes.
The test runs once per GT rather than once per engine, making sure that on multi-tile platforms
every GT/VRAM region is excercised. This stress test exercises concurrent buffer allocation
all the sizes at once.

This provide coverage for different BO allocation stress scenarios

v3: renamed the sub test functions.
v4: Addressed nits (kamil)

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
---
 tests/intel/xe_bo_alloc.c | 598 ++++++++++++++++++++++++++++++++++++++
 tests/meson.build         |   1 +
 2 files changed, 599 insertions(+)
 create mode 100644 tests/intel/xe_bo_alloc.c

diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
new file mode 100644
index 000000000..8680fe518
--- /dev/null
+++ b/tests/intel/xe_bo_alloc.c
@@ -0,0 +1,598 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+/**
+ * TEST: xe_bo_alloc
+ * Category: Core
+ * Mega feature: General
+ * Sub-category: Memory
+ * Functionality: BO allocation
+ * Description: Tests for buffer object allocation in Xe driver
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#include "igt.h"
+
+#include "lib/igt_syncobj.h"
+#include "lib/intel_reg.h"
+
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#include "xe_drm.h"
+#define BO_BIND_BASE_ADDR	0x1a0000ull
+#define THREAD_VA_STRIDE GB(1)
+#define SZ_4K_SHIFT	12
+#define MAX_ALLOCATIONS 50000
+
+/**
+ * SUBTEST: all-sizes-once
+ * Description: Test all BO allocations sizes in test table
+ * Test category: functionality test
+ */
+
+#define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
+#define MIN_BUFS_PER_PROC 2
+
+#define N_ALLOC_SIZES	256
+static uint64_t *alloc_sizes;
+
+/*
+ * Data-driven subtest matrix.
+ *
+ * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly one
+ * engine per invocation, so they're wired up as a dynamic child subtest
+ * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
+ *
+ * TYPE_THREAD are deliberately NOT split per engine here:
+ * threads() already do their own xe_for_each_engine() to spawn one
+ * thread per engine internally. Wrapping those in a second, outer
+ * per-engine loop would run the full all-engine fan-out
+ * once for every engine on the machine, multiplying the runtime by the
+ * engine count and re-exercising every engine N times over. So these
+ * stay flat, single subtests.
+ */
+enum test_type {
+	TYPE_ALL_SIZES,
+};
+
+struct test_case {
+	const char *name;
+	int count; /* -1 means "until vram_per_process is hit" */
+	uint32_t flags;
+	enum test_type type;
+	bool requires_evict_ram;
+};
+
+#define LEAK_BINDING		(0x1 << 0)
+#define LEAK_BO			(0x1 << 1)
+#define EVICT			(0x1 << 2)
+#define UNALIGNED		(0x1 << 3)
+#define ARRAY_BIND    (0x1 << 4)
+
+/*
+ * Represents a single BO under test: its reserved VA range, the BO handle,
+ * the CPU mapping obtained after binding, and its size. The prepare / bind
+ * / execute steps below all operate on arrays of this struct so that the
+ * same code path drives both a single BO (the original subtests) and an
+ * "array of binds" of several BOs at once (the new array-binds subtests).
+ */
+struct bo_alloc {
+	void *va_reserve;	/* raw mmap() reservation, kept only so it can
+				 * be released again; never touched directly.
+				 */
+	size_t va_reserve_size;
+	void *va;		/* fixed CPU mapping address used by mmap */
+	uint64_t gpu_va;	/* GPU virtual address used by VM_BIND */
+	void *map;		/* CPU mapping of the BO, valid after bind */
+	uint64_t bo_size;
+	uint32_t bo;
+};
+
+struct bo_group {
+	struct bo_alloc *bos;
+	int n_bos;
+};
+
+struct batch_data {
+	uint32_t batch[16];
+	uint64_t pad;
+	uint32_t data;
+};
+
+/*
+ * Reserve a chunk of process address space to use as the VM bind address
+ * for a BO, and hand back a pointer inside it aligned either to bo_size
+ * ("aligned" case) or to 64K ("unaligned" case, i.e. deliberately not
+ * aligned to bo_size).
+ *
+ * This replaces the previous use of aligned_alloc(bo_size, bo_size):
+ * aligned_alloc() requires size to be a multiple of alignment, which
+ * doesn't hold for most entries in alloc_sizes[] (multiples of 64K, not
+ * generally powers of two), so the old "aligned" path was silently
+ * returning a mis-aligned pointer for the majority of sizes tested.
+ * Reserving with PROT_NONE also avoids committing real memory that just
+ * gets thrown away once xe_bo_map_fixed() replaces it with the BO mapping.
+ */
+static void bo_alloc_reserve_va(struct bo_alloc *b, uint32_t flags, uint64_t va_base)
+{
+	uint64_t align = (flags & UNALIGNED) ? SZ_64K : b->bo_size;
+	size_t reserve_size = b->bo_size + align;
+	uintptr_t addr;
+	uintptr_t aligned_addr;
+	void *reserve;
+
+	/*
+	 * Keep each BO reservation in the caller-selected VA window so threads
+	 * and per-process tests do not clash on random mmap addresses. The
+	 * unaligned case still uses a 64 KiB alignment while the fixed address is
+	 * only a hint to keep the ranges stable and non-overlapping.
+	 */
+	addr = ALIGN(va_base, align);
+	reserve = mmap((void *)addr, reserve_size, PROT_NONE,
+		       MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED_NOREPLACE, -1, 0);
+	if (reserve == MAP_FAILED) {
+		reserve = mmap(NULL, reserve_size, PROT_NONE,
+			       MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+		igt_assert(reserve != MAP_FAILED);
+		addr = (uintptr_t)reserve;
+	}
+
+	b->va_reserve = reserve;
+	b->va_reserve_size = reserve_size;
+
+	addr = (uintptr_t)reserve;
+
+	/*
+	 * Round up to the next multiple of 'align'.
+	 * Works for arbitrary alignments, not just powers of two.
+	 */
+	aligned_addr = ((addr + align - 1) / align) * align;
+
+	b->va = (void *)aligned_addr;
+	b->gpu_va = to_user_pointer(b->va);
+
+	igt_debug("reserve=0x%llx align=0x%llx bo_size=0x%llx\n", (unsigned long long)addr,
+		  (unsigned long long)align, (unsigned long long)b->bo_size);
+
+	igt_assert_eq_u64(b->gpu_va % align, 0);
+}
+
+static void alloc_sizes_init(void)
+{
+	int i;
+
+	alloc_sizes = malloc(sizeof(*alloc_sizes) * N_ALLOC_SIZES);
+
+	/* For now just do increments of 64k */
+	for (i = 0; i < N_ALLOC_SIZES; ++i)
+		alloc_sizes[i] = 0x10000ull * (i + 1);
+}
+
+static void alloc_sizes_fini(void)
+{
+	free(alloc_sizes);
+}
+
+
+static uint32_t wkey = 0xc0ffeeull;
+#define WRITE_VALUE(page)	(((wkey) << 8) | (page))
+
+static void check_exec_data(void *ptr, int n_pages)
+{
+	int i;
+
+	for (i = 0; i < n_pages; ++i) {
+		struct batch_data *data = ptr + i * SZ_4K;
+
+		igt_assert_eq(data->data, WRITE_VALUE(i));
+	}
+}
+
+static void bo_alloc_release_va(struct bo_alloc *b)
+{
+	if (!b->va_reserve || !b->va_reserve_size)
+		return;
+	munmap(b->va_reserve, b->va_reserve_size);
+	b->va_reserve = NULL;
+	b->va_reserve_size = 0;
+}
+
+/*
+ * PREPARE step: allocate the VA range and create the BO. Doesn't touch the
+ * GPU. vm is passed through unbound to xe_bo_create() exactly as before:
+ * non-evict BOs are created VM-private, evict BOs are created external so
+ * they can be freely rebound after being evicted.
+ */
+static void create_bo_arr(int fd, uint32_t vm, struct bo_alloc *bos,  int n_bos, uint16_t gt_id,
+			  uint32_t flags, uint64_t start_va)
+{
+	uint64_t alignment = xe_get_default_alignment(fd);
+	uint32_t create_flags;
+	int i;
+
+	igt_assert(n_bos > 0);
+	create_flags = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+
+	for (i = 0; i < n_bos; i++) {
+		igt_assert_f(bos[i].bo_size,
+			     "BO[%d] has zero size\n", i);
+
+		bos[i].bo_size = ALIGN(bos[i].bo_size, alignment);
+		bo_alloc_reserve_va(&bos[i], flags, start_va + (i * alignment));
+		bos[i].map = NULL;
+
+		bos[i].bo = xe_bo_create(fd, vm,
+					 bos[i].bo_size,
+					 vram_if_possible(fd, gt_id),
+					 create_flags);
+
+		igt_assert_f(bos[i].bo,
+			     "Failed to create BO[%d]: gt=%u size=%#llx gpu_va=%#llx\n",
+			     i, gt_id, (unsigned long long)bos[i].bo_size,
+			     (unsigned long long)bos[i].gpu_va);
+	}
+}
+
+/*
+ * BIND step: bind one or more BOs as a single array-of-binds ioctl call
+ * (see __xe_vm_bind_array() above), replacing the previous open-coded
+ * xe_vm_bind_sync() called once per BO.
+ */
+static int test_bind_individual(int fd, uint32_t vm, struct bo_alloc *bos, int n_bos)
+{
+	struct drm_xe_sync sync = {
+		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.handle = syncobj_create(fd, 0),
+	};
+	int i, ret, j;
+
+	for (i = 0; i < n_bos; i++) {
+		struct drm_xe_sync *bind_sync = NULL;
+		uint32_t num_syncs = 0;
+
+		igt_debug("bind[%d/%d] size=%llu MiB va=0x%llx bo=%u\n", i, n_bos,
+			  (unsigned long long)(bos[i].bo_size >> 20),
+			  (unsigned long long)bos[i].gpu_va,
+			  bos[i].bo);
+
+		/*
+		 * Signal only after the last async bind.
+		 * VM bind operations on the same VM are ordered.
+		 */
+		if (i == n_bos - 1) {
+			bind_sync = &sync;
+			num_syncs = 1;
+		}
+
+		ret = __xe_vm_bind(fd, vm, 0, bos[i].bo, 0, bos[i].gpu_va, bos[i].bo_size,
+				   DRM_XE_VM_BIND_OP_MAP, 0, bind_sync, num_syncs, 0,
+				   (uint8_t)-1, 0);
+		if (ret == -ENOMEM || ret == -ENOSPC) {
+			igt_debug("VM Bind failed at BO[%d]: ret=%d errno=%d (%s)\n",
+				  i, ret, errno, strerror(-ret));
+			for (j = 0; j < i; j++)
+				xe_vm_unbind_sync(fd, vm, 0, bos[j].gpu_va, bos[j].bo_size);
+			syncobj_destroy(fd, sync.handle);
+			return ret;
+		}
+		igt_assert_eq(ret, 0);
+	}
+
+	igt_assert_f(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL),
+		     "Timed out waiting for async VM binds\n");
+
+	syncobj_destroy(fd, sync.handle);
+
+	return 0;
+}
+
+static int test_bind(int fd, uint32_t vm, struct bo_alloc *bos, int n_bos, uint32_t flags)
+{
+		return test_bind_individual(fd, vm, bos, n_bos);
+}
+
+/*
+ * UNBIND step: unbind each BO synchronously.
+ * This path intentionally avoids array-unbind ioctls for stability.
+ * BO in the batch.
+ */
+static void test_unbind(int fd, uint32_t vm, struct bo_alloc *bos, int n_bos)
+{
+	int i;
+
+	igt_assert(n_bos > 0);
+
+	for (i = 0; i < n_bos; ++i)
+		xe_vm_unbind_sync(fd, vm, 0, bos[i].gpu_va, bos[i].bo_size);
+}
+
+/*
+ * Map every BO after binding.
+ *
+ * gpu_va is also used as the fixed CPU virtual address, following the
+ * original test design.
+ */
+static void test_map_bos(int fd, struct bo_alloc *bos, int n_bos)
+{
+	int i;
+
+	for (i = 0; i < n_bos; i++) {
+		bos[i].map = xe_bo_map_fixed(fd,
+					     bos[i].bo,
+					     bos[i].bo_size,
+					     bos[i].gpu_va);
+
+		igt_assert_f(bos[i].map != MAP_FAILED,
+			     "Failed to map BO[%d]: bo=%u size=%#llx address=%#llx\n",
+			     i, bos[i].bo,
+			     (unsigned long long)bos[i].bo_size,
+			     (unsigned long long)bos[i].gpu_va);
+	}
+}
+
+/*
+ * Build and submit one batch for every 4 KiB page of one BO.
+ */
+static void execute_bo(int fd, uint32_t exec_queue,
+		       struct bo_alloc *bo)
+{
+	struct drm_xe_sync sync = {
+		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.handle = syncobj_create(fd, 0),
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.exec_queue_id = exec_queue,
+		.num_syncs = 0,
+		.syncs = to_user_pointer(&sync),
+	};
+	const uint64_t batch_offset =
+		offsetof(struct batch_data, batch);
+	const uint64_t data_offset =
+		offsetof(struct batch_data, data);
+	int n_pages = bo->bo_size >> SZ_4K_SHIFT;
+	int i;
+
+	for (i = 0; i < n_pages; i++) {
+		struct batch_data *data;
+		uint64_t page_addr;
+		uint64_t batch_addr;
+		uint64_t data_addr;
+		int b = 0;
+
+		data = (void *)((char *)bo->map + i * SZ_4K);
+
+		page_addr = bo->gpu_va + (i * SZ_4K);
+		batch_addr = page_addr + batch_offset;
+		data_addr = page_addr + data_offset;
+
+		memset(data, 0, sizeof(*data));
+
+		data->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		data->batch[b++] = lower_32_bits(data_addr);
+		data->batch[b++] = upper_32_bits(data_addr);
+		data->batch[b++] = WRITE_VALUE(i);
+		data->batch[b++] = MI_BATCH_BUFFER_END;
+
+		igt_assert(b <= ARRAY_SIZE(data->batch));
+
+		exec.address = batch_addr;
+
+		/*
+		 * Signal only after the final page submission.
+		 */
+		exec.num_syncs = i == n_pages - 1 ? 1 : 0;
+
+		xe_exec(fd, &exec);
+	}
+
+	igt_assert_f(syncobj_wait(fd, &sync.handle, 1,
+				  INT64_MAX, 0, NULL),
+		     "Timed out waiting for BO execution\n");
+
+	check_exec_data(bo->map, n_pages);
+
+	syncobj_destroy(fd, sync.handle);
+}
+
+static void execute_multi_bos(int fd, uint32_t exec_queue,
+			      struct bo_alloc *bos, int n_bos)
+{
+	int i;
+
+	test_map_bos(fd, bos, n_bos);
+
+	for (i = 0; i < n_bos; i++)
+		execute_bo(fd, exec_queue, &bos[i]);
+}
+
+static void bo_release(int fd, struct bo_alloc *b)
+{
+	if (b->map)
+		munmap(b->map, b->bo_size);
+	if (b->bo)
+		gem_close(fd, b->bo);
+	bo_alloc_release_va(b);
+}
+
+/*
+ * Runs prepare + bind + execute for n_bos BOs at once (n_bos == 1
+ * reproduces the original single-BO behaviour). If LEAK_BINDING is not
+ * set, unbinds afterwards. If LEAK_BO is set, the BOs are left mapped and
+ * bound and returned to the caller (as an array the caller owns and must
+ * eventually pass to check_leak_multi_group()/free()); otherwise they're torn down
+ * immediately and NULL is returned.
+ */
+static struct bo_alloc *test_alloc_sizes(int fd, uint32_t vm, uint32_t exec_q,
+					 uint16_t gt_id, uint64_t *sizes,
+					 int n_bos, uint32_t flags,  uint64_t va_base)
+{
+	struct bo_alloc *bos;
+	int i, ret;
+
+	bos = calloc(n_bos, sizeof(*bos));
+	igt_assert(bos);
+
+	for (i = 0; i < n_bos; ++i)
+		bos[i].bo_size = sizes[i];
+
+	create_bo_arr(fd, vm, bos, n_bos, gt_id, flags, va_base);
+	ret = test_bind(fd, vm, bos, n_bos, flags);
+	if (ret == -ENOMEM || ret == -ENOSPC)
+		goto cleanup;
+
+	igt_assert_eq(ret, 0);
+	execute_multi_bos(fd, exec_q, bos, n_bos);
+
+	if (!(flags & LEAK_BINDING))
+		test_unbind(fd, vm, bos, n_bos);
+
+cleanup:
+
+	if (ret || !(flags & LEAK_BO)) {
+		for (i = 0; i < n_bos; ++i)
+			bo_release(fd, &bos[i]);
+		free(bos);
+		return NULL;
+	}
+
+	return bos;
+}
+
+/* Thin single-BO wrapper: keeps the existing call sites unchanged. */
+static struct bo_alloc *test_alloc_size(int fd, uint32_t vm, uint32_t q,
+					uint16_t gt_id, uint64_t bo_size,
+					uint32_t flags, uint64_t va_base)
+{
+	struct bo_alloc *bos = test_alloc_sizes(fd, vm, q, gt_id, &bo_size,
+						1, flags, va_base);
+
+	/* Caller only ever gets/frees a single struct, so unwrap it. */
+	if (bos) {
+		struct bo_alloc *b = malloc(sizeof(*b));
+
+		igt_assert(b);
+		*b = bos[0];
+		free(bos);
+		return b;
+	}
+
+	return NULL;
+}
+
+static void all_sizes_once(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+	uint32_t vm, q;
+	int i;
+
+	vm = xe_vm_create(fd, 0, 0);
+	q =  xe_exec_queue_create(fd, vm, hwe, 0);
+
+	for (i = 0; i < N_ALLOC_SIZES; ++i)
+		test_alloc_size(fd, vm, q, hwe->gt_id, alloc_sizes[i], 0, BO_BIND_BASE_ADDR);
+
+	xe_exec_queue_destroy(fd, q);
+	xe_vm_destroy(fd, vm);
+}
+
+static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
+{
+	struct drm_xe_engine_class_instance *hwe;
+	uint16_t seen_gt[64];
+	int n_seen = 0, j;
+	bool dup;
+
+	if (t->requires_evict_ram) {
+		igt_require(xe_has_vram(fd));
+		igt_require(igt_get_avail_ram_mb() >=
+			    (xe_visible_vram_size(fd, 0) >> 20) / 2);
+	}
+
+	/*
+	 * These tests only care about which GT (and  therefore which VRAM region,
+	 * via gt_id -> vram_if_possible()) the BO ends up on, not which specific
+	 * engine issues the exec. So run once per distinct gt_id instead of once
+	 * per engine: on single-GT parts that's one dynamic child same as before,
+	 * and on multi-tile parts it exercises every tile's VRAM instead of silently
+	 * only ever hitting whichever GT the first engine happened to belong to
+	 */
+	xe_for_each_engine(fd, hwe) {
+		dup = false;
+
+		for (j = 0; j < n_seen; ++j) {
+			if (seen_gt[j] == hwe->gt_id) {
+				dup = true;
+				break;
+			}
+		}
+		if (dup)
+			continue;
+
+		igt_assert(n_seen < ARRAY_SIZE(seen_gt));
+		seen_gt[n_seen++] = hwe->gt_id;
+
+		igt_dynamic_f("gt%u", hwe->gt_id) {
+			switch (t->type) {
+			case TYPE_ALL_SIZES:
+				all_sizes_once(fd, hwe);
+				break;
+			default:
+				break;
+
+			}
+		}
+	}
+}
+
+/*
+ * Data-driven subtest matrix.
+ *
+ * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly one
+ * engine per invocation, so they're wired up as a dynamic child subtest
+ * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
+ *
+ * TYPE_THREAD / TYPE_PROCESS are deliberately NOT split per engine here:
+ * threads() and processes() already do their own xe_for_each_engine() to
+ * spawn one thread/process per engine internally. Wrapping those in a
+ * second, outer per-engine loop would run the full all-engine fan-out
+ * once for every engine on the machine, multiplying the runtime by the
+ * engine count and re-exercising every engine N times over. So these
+ * stay flat, single subtests.
+ */
+
+static const struct test_case test_matrix[] = {
+	{ "all-sizes-once", 0, 0, TYPE_ALL_SIZES, false },
+};
+
+int igt_main()
+{
+	int fd, i;
+
+	igt_fixture() {
+		fd = drm_open_driver(DRIVER_XE);
+		alloc_sizes_init();
+	}
+
+	for (i = 0; i < ARRAY_SIZE(test_matrix); ++i) {
+		const struct test_case *t = &test_matrix[i];
+
+		switch (t->type) {
+		case TYPE_ALL_SIZES:
+			igt_subtest_with_dynamic_f("%s", t->name)
+				run_gt_dynamic_subtests(fd, t);
+		}
+	}
+
+	igt_fixture() {
+		alloc_sizes_fini();
+		drm_close_driver(fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 4f5c9be7b..f3e1802fd 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -283,6 +283,7 @@ intel_kms_progs = [
 
 intel_xe_progs = [
 	'xe_wedged',
+        'xe_bo_alloc',
 	'xe_ccs',
 	'xe_create',
 	'xe_compute',
-- 
2.52.0

[PATCH i-g-t v5 2/5] tests/intel: Add random-size BO leak tests

[Sobin Thomas]

Add new RANDOM_SIZE subtests exercising randomly sized BO allocation
This test excercises allocation, execution, validation and cleanup
paths across a wider mix of BO size, helping to detect issues that
may only appear with specific size combinations.

Add the following subtests:
- rand-sizes-10
- rand-sizes-100
- rand-sizes-100-unaligned

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
---
 tests/intel/xe_bo_alloc.c | 126 ++++++++++++++++++++++++++++++++++----
 1 file changed, 115 insertions(+), 11 deletions(-)

diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
index 8680fe518..bd5bf5a33 100644
--- a/tests/intel/xe_bo_alloc.c
+++ b/tests/intel/xe_bo_alloc.c
@@ -34,6 +34,20 @@
  * SUBTEST: all-sizes-once
  * Description: Test all BO allocations sizes in test table
  * Test category: functionality test
+ *
+ * SUBTEST: rand-sizes-10
+ * Description: Test 10 random BO allocation sizes in test table
+ * Test category: functionality test
+ *
+ * SUBTEST: rand-sizes-100
+ * Description: Test 100 random BO allocation sizes in test table
+ * Test category: functionality test
+ *
+ * SUBTEST: rand-sizes-100-unaligned
+ * Description: Test 100 random BO allocation sizes in test table, unaligned bind addresses
+ * Test category: functionality test
+ *
+ *
  */
 
 #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
@@ -45,7 +59,7 @@ static uint64_t *alloc_sizes;
 /*
  * Data-driven subtest matrix.
  *
- * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly one
+ * TYPE_ALL_SIZES / TYPE_RANDOM_SIZE / TYPE_ARRAY_BIND all exercise exactly one
  * engine per invocation, so they're wired up as a dynamic child subtest
  * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
  *
@@ -59,6 +73,7 @@ static uint64_t *alloc_sizes;
  */
 enum test_type {
 	TYPE_ALL_SIZES,
+	TYPE_RANDOM_SIZE,
 };
 
 struct test_case {
@@ -337,6 +352,15 @@ static void test_map_bos(int fd, struct bo_alloc *bos, int n_bos)
 	}
 }
 
+static void bo_release(int fd, struct bo_alloc *b)
+{
+	if (b->map)
+		munmap(b->map, b->bo_size);
+	if (b->bo)
+		gem_close(fd, b->bo);
+	bo_alloc_release_va(b);
+}
+
 /*
  * Build and submit one batch for every 4 KiB page of one BO.
  */
@@ -414,15 +438,6 @@ static void execute_multi_bos(int fd, uint32_t exec_queue,
 		execute_bo(fd, exec_queue, &bos[i]);
 }
 
-static void bo_release(int fd, struct bo_alloc *b)
-{
-	if (b->map)
-		munmap(b->map, b->bo_size);
-	if (b->bo)
-		gem_close(fd, b->bo);
-	bo_alloc_release_va(b);
-}
-
 /*
  * Runs prepare + bind + execute for n_bos BOs at once (n_bos == 1
  * reproduces the original single-BO behaviour). If LEAK_BINDING is not
@@ -488,6 +503,88 @@ static struct bo_alloc *test_alloc_size(int fd, uint32_t vm, uint32_t q,
 	return NULL;
 }
 
+static void validate_bo_leak(int fd, uint32_t vm, struct bo_alloc *bos,
+			     int n_bos, uint32_t flags)
+{
+	int i;
+
+	for (i = 0; i < n_bos; ++i)
+		check_exec_data(bos[i].map, bos[i].bo_size >> SZ_4K_SHIFT);
+
+	/* Migrate the whole group back into VRAM, recheck */
+	if (flags & EVICT) {
+		igt_assert_eq(test_bind(fd, vm, bos, n_bos, flags), 0);
+
+		for (i = 0; i < n_bos; ++i)
+			check_exec_data(bos[i].map, bos[i].bo_size >> SZ_4K_SHIFT);
+
+		test_unbind(fd, vm, bos, n_bos);
+	}
+
+	for (i = 0; i < n_bos; ++i)
+		bo_release(fd, &bos[i]);
+}
+
+static void check_leak_multi_group(int fd, uint32_t vm, struct bo_group **groups,
+				   int count, uint32_t flags)
+{
+	int i;
+
+	for (i = 0; i < count; ++i) {
+		if (!groups[i])
+			continue;
+
+		validate_bo_leak(fd, vm, groups[i]->bos, groups[i]->n_bos, flags);
+		free(groups[i]);
+	}
+}
+
+static void alloc_rand_size_bos(int fd, struct drm_xe_engine_class_instance *hwe,
+				int count, uint64_t vram_per_process, pthread_barrier_t *barrier,
+				uint32_t flags)
+{
+	struct bo_group **leaks = NULL;
+	uint32_t vm, q, bo_size;
+	uint64_t vram_used = 0;
+	int i, max_batches = (count == -1) ? MAX_ALLOCATIONS : count;
+
+	igt_assert(count > 0 || (flags & EVICT && flags & LEAK_BO));
+	leaks = malloc(sizeof(*leaks) * max_batches);
+	igt_assert(leaks);
+
+	vm = xe_vm_create(fd, 0, 0);
+	q =  xe_exec_queue_create(fd, vm, hwe, 0);
+
+	for (i = 0; i < count || vram_used < vram_per_process; ++i) {
+		struct bo_alloc *bo;
+
+		bo_size = alloc_sizes[rand() % N_ALLOC_SIZES];
+
+		igt_assert(i < max_batches);
+		bo = test_alloc_size(fd, vm, q, hwe->gt_id, bo_size, flags,
+				     BO_BIND_BASE_ADDR);
+		if (bo) {
+			leaks[i] = malloc(sizeof(*leaks[i]));
+			igt_assert(leaks[i]);
+
+			leaks[i]->bos = bo;
+			leaks[i]->n_bos = 1;
+
+			vram_used += bo->bo_size;
+		} else {
+			leaks[i] = NULL;
+		}
+	}
+
+	if (barrier)
+		pthread_barrier_wait(barrier);
+	check_leak_multi_group(fd, vm, leaks, i, flags);
+
+	xe_exec_queue_destroy(fd, q);
+	xe_vm_destroy(fd, vm);
+	free(leaks);
+}
+
 static void all_sizes_once(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	uint32_t vm, q;
@@ -544,6 +641,9 @@ static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
 			case TYPE_ALL_SIZES:
 				all_sizes_once(fd, hwe);
 				break;
+			case TYPE_RANDOM_SIZE:
+				alloc_rand_size_bos(fd, hwe, t->count, 0, NULL, t->flags);
+				break;
 			default:
 				break;
 
@@ -555,7 +655,7 @@ static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
 /*
  * Data-driven subtest matrix.
  *
- * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly one
+ * TYPE_ALL_SIZES / TYPE_RANDOM_SIZE / TYPE_ARRAY_BIND all exercise exactly one
  * engine per invocation, so they're wired up as a dynamic child subtest
  * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
  *
@@ -570,6 +670,9 @@ static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
 
 static const struct test_case test_matrix[] = {
 	{ "all-sizes-once", 0, 0, TYPE_ALL_SIZES, false },
+	{ "rand-sizes-10", 10, 0, TYPE_RANDOM_SIZE, false },
+	{ "rand-sizes-100", 100, 0, TYPE_RANDOM_SIZE, false },
+	{ "rand-sizes-100-unaligned", 100, UNALIGNED, TYPE_RANDOM_SIZE, false },
 };
 
 int igt_main()
@@ -586,6 +689,7 @@ int igt_main()
 
 		switch (t->type) {
 		case TYPE_ALL_SIZES:
+		case TYPE_RANDOM_SIZE:
 			igt_subtest_with_dynamic_f("%s", t->name)
 				run_gt_dynamic_subtests(fd, t);
 		}
-- 
2.52.0

[PATCH i-g-t v5 3/5] tests/intel: Add array-of-binds random-size allocation tests

[Sobin Thomas]

Add new array-binds-rand-sizes-* subtests that allocate batches of
random-sized BOs and bind them using a single array-of-binds operation.

The new tests allocate 10 BOs per batch and exercise both aligned and
unaligned bind addresses. This extends existing eviction coverage by
verifying that BOs with varying sizes can be bound, managed and evicted
correctly when submitted as a single bind array rather than individual
bind operations.

Introduce alloc_random_size_bos_array_bind(), which mirrors the existing
random-size allocation flow while grouping multiple BOs into a single
array bind submission. This is particularly useful for eviction testing
where a set of BOs needs to be resident or evicted as a unit.

The tests are intended to provide additional coverage for array-of-binds
handling under random allocation patterns and VRAM pressure scenarios.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
---
 tests/intel/xe_bo_alloc.c | 177 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 177 insertions(+)

diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
index bd5bf5a33..343d07626 100644
--- a/tests/intel/xe_bo_alloc.c
+++ b/tests/intel/xe_bo_alloc.c
@@ -47,7 +47,15 @@
  * Description: Test 100 random BO allocation sizes in test table, unaligned bind addresses
  * Test category: functionality test
  *
+ * SUBTEST: array-binds-rand-sizes-10
+ * Description: Test 10 batches of 10 random BO allocation sizes each bound together as a
+ * single array of binds
+ * Test category: functionality test
  *
+ * SUBTEST: array-binds-rand-sizes-10-unaligned
+ * Description: Test 10 batches of 10 random BO allocation sizes bound together as a single
+ * array of binds, unaligned bind addresses
+ * Test category: functionality test
  */
 
 #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
@@ -74,6 +82,7 @@ static uint64_t *alloc_sizes;
 enum test_type {
 	TYPE_ALL_SIZES,
 	TYPE_RANDOM_SIZE,
+	TYPE_ARRAY_BIND
 };
 
 struct test_case {
@@ -178,6 +187,28 @@ static void bo_alloc_reserve_va(struct bo_alloc *b, uint32_t flags, uint64_t va_
 	igt_assert_eq_u64(b->gpu_va % align, 0);
 }
 
+static int __xe_vm_bind_array(int fd, uint32_t vm,
+			      struct drm_xe_vm_bind_op *bind_ops,
+			      uint32_t num_bind, struct drm_xe_sync *sync,
+			      uint32_t num_syncs)
+{
+	struct drm_xe_vm_bind bind = {
+		.vm_id = vm,
+		.num_binds = num_bind,
+		.vector_of_binds = (uintptr_t)bind_ops,
+		.num_syncs = num_syncs,
+		.syncs = (uintptr_t)sync,
+		.exec_queue_id = 0,
+	};
+
+	igt_assert(num_bind > 0);
+
+	if (igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind))
+		return -errno;
+
+	return 0;
+}
+
 static void alloc_sizes_init(void)
 {
 	int i;
@@ -254,6 +285,7 @@ static void create_bo_arr(int fd, uint32_t vm, struct bo_alloc *bos,  int n_bos,
 	}
 }
 
+
 /*
  * BIND step: bind one or more BOs as a single array-of-binds ioctl call
  * (see __xe_vm_bind_array() above), replacing the previous open-coded
@@ -308,8 +340,72 @@ static int test_bind_individual(int fd, uint32_t vm, struct bo_alloc *bos, int n
 	return 0;
 }
 
+static int test_bind_array(int fd, uint32_t vm,
+			   struct bo_alloc *bos, int n_bos)
+{
+	struct drm_xe_vm_bind_op *bind_ops;
+	struct drm_xe_sync sync = {
+		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.handle = syncobj_create(fd, 0),
+	};
+	int i, ret;
+
+	igt_assert(n_bos > 0);
+
+	bind_ops = calloc(n_bos, sizeof(*bind_ops));
+	igt_assert(bind_ops);
+
+	for (i = 0; i < n_bos; i++) {
+		igt_assert_f(bos[i].bo,
+			     "BO[%d] was not created before bind\n", i);
+
+		igt_assert_f(bos[i].bo_size,
+			     "BO[%d] has zero size\n", i);
+
+		bind_ops[i] = (struct drm_xe_vm_bind_op) {
+			.obj = bos[i].bo,
+			.obj_offset = 0,
+			.range = bos[i].bo_size,
+			.addr = bos[i].gpu_va,
+			.op = DRM_XE_VM_BIND_OP_MAP,
+			.flags = 0,
+		};
+
+		igt_debug("Bind op[%d]: bo=%u size=%#llx addr=%#llx\n",
+			  i,
+			  bos[i].bo,
+			  (unsigned long long)bos[i].bo_size,
+			  (unsigned long long)bos[i].gpu_va);
+	}
+
+	ret = __xe_vm_bind_array(fd, vm, bind_ops, n_bos, &sync, 1);
+	if (ret) {
+		if (ret == -ENOMEM || ret == -ENOSPC) {
+			syncobj_destroy(fd, sync.handle);
+			free(bind_ops);
+			return ret;
+		}
+
+		igt_assert_f(false, "Array VM_BIND failed: ret=%d errno=%d (%s)\n",
+			     ret, errno, strerror(errno));
+	}
+
+	igt_assert_f(syncobj_wait(fd, &sync.handle, 1,
+				  INT64_MAX, 0, NULL),
+		     "Timed out waiting for array VM_BIND\n");
+
+	syncobj_destroy(fd, sync.handle);
+	free(bind_ops);
+
+	return 0;
+}
+
 static int test_bind(int fd, uint32_t vm, struct bo_alloc *bos, int n_bos, uint32_t flags)
 {
+	if (flags & ARRAY_BIND)
+		return test_bind_array(fd, vm, bos, n_bos);
+	else
 		return test_bind_individual(fd, vm, bos, n_bos);
 }
 
@@ -600,6 +696,76 @@ static void all_sizes_once(int fd, struct drm_xe_engine_class_instance *hwe)
 	xe_vm_destroy(fd, vm);
 }
 
+/*
+ * Same idea as alloc_rand_size_bos(), but each iteration binds N_BOS_PER_BIND BOs
+ * together via a single array-of-binds call instead of one at a time.
+ * Used by the array-binds-* subtests, in particular the eviction stress
+ * test where several BOs need to be resident (or evicted) as a unit.
+ */
+#define N_BOS_PER_BIND	10
+
+static void alloc_random_size_bos_array_bind(int fd, struct drm_xe_engine_class_instance *hwe,
+					     int count, uint64_t vram_per_process,
+					     pthread_barrier_t *barrier, uint32_t flags,
+					     unsigned int *seed)
+{
+	struct bo_group **leaks = NULL;
+	uint32_t vm, exec_queue;
+	uint64_t vram_used = 0;
+	int i, max_batches = (count == -1) ? MAX_ALLOCATIONS : count;
+	int n_batches = 0;
+
+	igt_debug("count=%d max_batches=%d vram_per_process=%llu flags=%x\n",
+		  count, max_batches, (unsigned long long)vram_per_process, flags);
+
+	igt_assert(count > 0 || (flags & EVICT && flags & LEAK_BO));
+
+	leaks = malloc(sizeof(*leaks) * max_batches);
+	igt_assert(leaks);
+
+	vm = xe_vm_create(fd, 0, 0);
+	exec_queue =  xe_exec_queue_create(fd, vm, hwe, 0);
+
+	for (i = 0; i < count || vram_used < vram_per_process; ++i) {
+		uint64_t sizes[N_BOS_PER_BIND];
+		struct bo_alloc *bos;
+		int j;
+
+		for (j = 0; j < N_BOS_PER_BIND; ++j)
+			sizes[j] = alloc_sizes[rand_r(seed) % N_ALLOC_SIZES];
+
+		igt_assert_f(i < max_batches, "Failed to reach %llu bytes of VRAM pressure "
+			     " after %d batches (currently reached %llu bytes)\n",
+			     (unsigned long long)vram_per_process, max_batches,
+			     (unsigned long long)vram_used);
+
+		bos = test_alloc_sizes(fd, vm, exec_queue, hwe->gt_id, sizes,
+				       N_BOS_PER_BIND, flags, BO_BIND_BASE_ADDR);
+		if (bos) {
+			leaks[i] = malloc(sizeof(*leaks[i]));
+			igt_assert(leaks[i]);
+
+			leaks[i]->bos = bos;
+			leaks[i]->n_bos = N_BOS_PER_BIND;
+			n_batches++;
+
+			for (j = 0; j < N_BOS_PER_BIND; ++j)
+				vram_used += bos[j].bo_size;
+		} else {
+			leaks[i] = NULL;
+		}
+	}
+
+	if (barrier)
+		pthread_barrier_wait(barrier);
+
+	check_leak_multi_group(fd, vm, leaks, n_batches, flags);
+
+	xe_exec_queue_destroy(fd, exec_queue);
+	xe_vm_destroy(fd, vm);
+	free(leaks);
+}
+
 static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -644,6 +810,13 @@ static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
 			case TYPE_RANDOM_SIZE:
 				alloc_rand_size_bos(fd, hwe, t->count, 0, NULL, t->flags);
 				break;
+			case TYPE_ARRAY_BIND: {
+				unsigned int seed = hwe->gt_id + 1;
+
+				alloc_random_size_bos_array_bind(fd, hwe, t->count, 0, NULL,
+								 t->flags, &seed);
+				break;
+			}
 			default:
 				break;
 
@@ -673,6 +846,9 @@ static const struct test_case test_matrix[] = {
 	{ "rand-sizes-10", 10, 0, TYPE_RANDOM_SIZE, false },
 	{ "rand-sizes-100", 100, 0, TYPE_RANDOM_SIZE, false },
 	{ "rand-sizes-100-unaligned", 100, UNALIGNED, TYPE_RANDOM_SIZE, false },
+	{ "array-binds-rand-sizes-10", 10, ARRAY_BIND, TYPE_ARRAY_BIND, true },
+	{ "array-binds-rand-sizes-10-unaligned", 10,  ARRAY_BIND | UNALIGNED, TYPE_ARRAY_BIND,
+	  true },
 };
 
 int igt_main()
@@ -690,6 +866,7 @@ int igt_main()
 		switch (t->type) {
 		case TYPE_ALL_SIZES:
 		case TYPE_RANDOM_SIZE:
+		case TYPE_ARRAY_BIND:
 			igt_subtest_with_dynamic_f("%s", t->name)
 				run_gt_dynamic_subtests(fd, t);
 		}
-- 
2.52.0

[PATCH i-g-t v5 4/5] tests/intel: Add threaded random-size allocation stress tests

[Sobin Thomas]

Add a new TYPE_THREAD test mode that creates a worker thread per
available engine and performs random-sized BO allocations concurrently.

Each thread creates its own VM and execution queue and exercises the
existing allocation path with both aligned and unaligned bind addresses.
Additional variants cover leaked bindings.

These tests provide additional stress coverage for concurrent BO
allocation and VM bind activity across multiple engines.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
---
 tests/intel/xe_bo_alloc.c | 149 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 148 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
index 343d07626..d8368087b 100644
--- a/tests/intel/xe_bo_alloc.c
+++ b/tests/intel/xe_bo_alloc.c
@@ -56,6 +56,26 @@
  * Description: Test 10 batches of 10 random BO allocation sizes bound together as a single
  * array of binds, unaligned bind addresses
  * Test category: functionality test
+ *
+ *
+ * SUBTEST: threads-rand-sizes-50
+ * Description: Test 50 random bo allocation sizes in test table with a thread per engine
+ * test category: stress test
+ *
+ * SUBTEST: threads-rand-sizes-50-unaligned
+ * Description: Test 50 random bo allocation sizes in test table with a thread per engine,
+ * unaligned bind addresses
+ * test category: stress test
+ *
+ * SUBTEST: threads-leak-binding-rand-sizes-50
+ * Description: Test 50 random BO allocation sizes in test table with a thread per engine,
+ * leak the binding
+ * Test category: stress test
+ *
+ * SUBTEST: threads-leak-binding-rand-sizes-50-unaligned
+ * Description: Test 50 random BO allocation sizes in test table with a thread per engine,
+ * leak the binding, unaligned bind addresses
+ * Test category: stress test
  */
 
 #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
@@ -82,7 +102,8 @@ static uint64_t *alloc_sizes;
 enum test_type {
 	TYPE_ALL_SIZES,
 	TYPE_RANDOM_SIZE,
-	TYPE_ARRAY_BIND
+	TYPE_ARRAY_BIND,
+	TYPE_THREAD
 };
 
 struct test_case {
@@ -129,6 +150,20 @@ struct batch_data {
 	uint32_t data;
 };
 
+struct thread_data {
+	uint64_t va_base;
+	pthread_t thread;
+	pthread_mutex_t *mutex;
+	pthread_cond_t *cond;
+	struct drm_xe_engine_class_instance *hwe;
+	int fd;
+	int count;
+	uint32_t vm;
+	uint32_t flags;
+	unsigned int seed;
+	bool *go;
+};
+
 /*
  * Reserve a chunk of process address space to use as the VM bind address
  * for a BO, and hand back a pointer inside it aligned either to bo_size
@@ -766,6 +801,103 @@ static void alloc_random_size_bos_array_bind(int fd, struct drm_xe_engine_class_
 	free(leaks);
 }
 
+static void *bo_alloc_thread_fn(void *data)
+{
+	struct thread_data *t = data;
+	uint32_t q;
+	int i;
+
+	igt_assert(!(t->flags & LEAK_BO));
+
+	pthread_mutex_lock(t->mutex);
+	while (!*t->go)
+		pthread_cond_wait(t->cond, t->mutex);
+	pthread_mutex_unlock(t->mutex);
+
+	q =  xe_exec_queue_create(t->fd, t->vm, t->hwe, 0);
+
+	for (i = 0; i < t->count; ++i)
+		test_alloc_size(t->fd, t->vm, q, t->hwe->gt_id,
+				alloc_sizes[rand() % N_ALLOC_SIZES],
+				t->flags, t->va_base);
+
+	xe_exec_queue_destroy(t->fd, q);
+
+	return NULL;
+}
+
+static void run_threaded_bo_alloc_test(int fd, int count, uint32_t flags)
+{
+	struct drm_xe_engine_class_instance *hwe;
+	struct drm_xe_engine_class_instance **engines;
+	struct thread_data *threads_data;
+	pthread_mutex_t mutex;
+	pthread_cond_t cond;
+	bool begin_work = false;
+	int n_found = 0, n_threads = 0, i, ret;
+
+	xe_for_each_engine(fd, hwe)
+		n_found++;
+
+	igt_assert(n_found > 0);
+
+	engines = calloc(n_found, sizeof(*engines));
+	igt_assert(engines);
+
+	i = 0;
+	xe_for_each_engine(fd, hwe)
+		engines[i++] = hwe;
+
+	threads_data = calloc(n_found, sizeof(*threads_data));
+	igt_assert(threads_data);
+
+	pthread_mutex_init(&mutex, 0);
+	pthread_cond_init(&cond, 0);
+
+	for (i = 0; i < n_found; ++i) {
+		threads_data[i].mutex = &mutex;
+		threads_data[i].cond = &cond;
+		/* reuse engine 0 if only one exists */
+		threads_data[i].hwe = engines[i % n_found];
+		threads_data[i].fd = fd;
+		threads_data[i].count = count;
+		threads_data[i].vm = xe_vm_create(fd, 0, 0);
+		threads_data[i].flags = flags;
+		threads_data[i].go = &begin_work;
+		threads_data[i].seed = i + 1;
+		threads_data[i].va_base = BO_BIND_BASE_ADDR + (uint64_t)i * THREAD_VA_STRIDE;
+		ret = pthread_create(&threads_data[i].thread, 0, bo_alloc_thread_fn,
+				     &threads_data[i]);
+		if (ret)
+			break;
+		n_threads++;
+	}
+
+	ret = pthread_mutex_lock(&mutex);
+	igt_assert_eq(ret, 0);
+	begin_work = true;
+	ret = pthread_cond_broadcast(&cond);
+	igt_assert_eq(ret, 0);
+	ret = pthread_mutex_unlock(&mutex);
+	igt_assert_eq(ret, 0);
+
+	for (i = 0; i < n_threads; ++i) {
+		ret = pthread_join(threads_data[i].thread, NULL);
+		igt_assert_eq(ret, 0);
+	}
+
+	/* vm is created for every slot up to n_found regardless of thread creation success */
+	for (i = 0; i < n_found; ++i)
+		xe_vm_destroy(fd, threads_data[i].vm);
+
+	ret = pthread_cond_destroy(&cond);
+	igt_assert_eq(ret, 0);
+	ret = pthread_mutex_destroy(&mutex);
+	igt_assert_eq(ret, 0);
+	free(threads_data);
+	free(engines);
+}
+
 static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -849,6 +981,11 @@ static const struct test_case test_matrix[] = {
 	{ "array-binds-rand-sizes-10", 10, ARRAY_BIND, TYPE_ARRAY_BIND, true },
 	{ "array-binds-rand-sizes-10-unaligned", 10,  ARRAY_BIND | UNALIGNED, TYPE_ARRAY_BIND,
 	  true },
+	{ "threads-rand-sizes-50", 50, 0, TYPE_THREAD, false },
+	{ "threads-rand-sizes-50-unaligned", 50, UNALIGNED, TYPE_THREAD, false },
+	{ "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING, TYPE_THREAD, false },
+	{ "threads-leak-binding-rand-sizes-50-unaligned", 50, LEAK_BINDING | UNALIGNED,
+	  TYPE_THREAD, false },
 };
 
 int igt_main()
@@ -864,6 +1001,16 @@ int igt_main()
 		const struct test_case *t = &test_matrix[i];
 
 		switch (t->type) {
+		case TYPE_THREAD:
+			igt_subtest_f("%s", t->name) {
+				if (t->requires_evict_ram) {
+					igt_require(xe_has_vram(fd));
+					igt_require(igt_get_avail_ram_mb() >=
+						    (xe_visible_vram_size(fd, 0) >> 20) / 2);
+				}
+				run_threaded_bo_alloc_test(fd, t->count, t->flags);
+			}
+			break;
 		case TYPE_ALL_SIZES:
 		case TYPE_RANDOM_SIZE:
 		case TYPE_ARRAY_BIND:
-- 
2.52.0

[PATCH i-g-t v5 5/5] tests/intel: Add oversubscribe concurrent bind stress subtest

[Sobin Thomas]

Add test for oversubscribing VRAM in multi process environment that
creates VM, bind large BOs and submit workloads nearly simultaneously.

Previous coverage lacked a scenario combining multi-process bind
with VRAM oversubscription. This generates memory pressure with
multi-process VM Bind activity and concurrent submission, exercising
the bind pipeline under eviction pressure.

v3: Fixed minor nits
v4: Refactoring of the create_bo ( Nishit)
    Fix child process exit deadlock in release_ready_processes() (Nishit)

Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
---
 tests/intel/xe_bo_alloc.c | 533 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 532 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
index d8368087b..2ee468c62 100644
--- a/tests/intel/xe_bo_alloc.c
+++ b/tests/intel/xe_bo_alloc.c
@@ -29,6 +29,17 @@
 #define THREAD_VA_STRIDE GB(1)
 #define SZ_4K_SHIFT	12
 #define MAX_ALLOCATIONS 50000
+#define INT_ADD_CNT 4
+#define TIMEOUT_NS (30ULL * 1000000000ULL)
+#define MAX_SRAM_TEST_SIZE GB(32)
+#define GPR_RX_ADDR(x)          (0x600 + (x) * 8)
+#define MAX_PROCS 20
+
+#define EXEC_DATA_ADDR		0x100000ULL
+#define EXEC_RESULT_ADDR	0x200000ULL
+#define EXEC_BATCH_ADDR		0x300000ULL
+#define EXEC_UFENCE_ADDR	0x400000ULL
+#define STRESS_BIND_ADDR	0x40000000ULL
 
 /**
  * SUBTEST: all-sizes-once
@@ -76,14 +87,48 @@
  * Description: Test 50 random BO allocation sizes in test table with a thread per engine,
  * leak the binding, unaligned bind addresses
  * Test category: stress test
+ *
+ * SUBTEST: test_vm_oversubscribe_concurrent_bind
+ * Description: Test enough random BO allocation sizes, bound as arrays of binds, to trigger
+ * evictions with 2 processes per engine, leak the BO munmap / gem close, unaligned bind addresses
+ * Test category: stress test
  */
 
 #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
 #define MIN_BUFS_PER_PROC 2
 
 #define N_ALLOC_SIZES	256
+#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
+
 static uint64_t *alloc_sizes;
 
+struct gem_bo {
+	uint32_t handle;
+	uint64_t size;
+	uint32_t *ptr;
+	uint64_t addr;
+};
+
+struct xe_oversubscribe_ctx {
+	uint32_t vm_id;
+	uint32_t exec_queue_id;
+};
+
+struct mem_bind_sync {
+	struct gem_bo *bufs;
+	int n_bufs;
+	uint64_t *binds_ufence;
+};
+
+struct process_data {
+	pthread_mutex_t mutex;
+	pthread_cond_t cond;
+	int ready;
+	int failed;
+	pthread_barrier_t barrier;
+	bool go;
+};
+
 /*
  * Data-driven subtest matrix.
  *
@@ -103,7 +148,8 @@ enum test_type {
 	TYPE_ALL_SIZES,
 	TYPE_RANDOM_SIZE,
 	TYPE_ARRAY_BIND,
-	TYPE_THREAD
+	TYPE_THREAD,
+	TYPE_OVERSUBSCRIBE,
 };
 
 struct test_case {
@@ -114,6 +160,14 @@ struct test_case {
 	bool requires_evict_ram;
 };
 
+struct oversubscribe_params {
+	int n_proc;
+	int n_vram_bufs;
+	int n_sram_bufs;
+	uint64_t vram_size;
+	uint64_t sram_size;
+	uint64_t total_vram_demand;
+};
 #define LEAK_BINDING		(0x1 << 0)
 #define LEAK_BO			(0x1 << 1)
 #define EVICT			(0x1 << 2)
@@ -244,6 +298,478 @@ static int __xe_vm_bind_array(int fd, uint32_t vm,
 	return 0;
 }
 
+static void init_pdata(struct process_data *pdata)
+{
+	pthread_mutexattr_t mattr;
+	pthread_condattr_t cattr;
+
+	pthread_mutexattr_init(&mattr);
+	igt_assert_eq(pthread_mutexattr_setpshared(&mattr, PTHREAD_PROCESS_SHARED), 0);
+	igt_assert_eq(pthread_mutexattr_setrobust(&mattr, PTHREAD_MUTEX_ROBUST), 0);
+	igt_assert_eq(pthread_mutex_init(&pdata->mutex, &mattr), 0);
+	pthread_mutexattr_destroy(&mattr);
+
+	pthread_condattr_init(&cattr);
+	igt_assert_eq(pthread_condattr_setpshared(&cattr, PTHREAD_PROCESS_SHARED), 0);
+	igt_assert_eq(pthread_cond_init(&pdata->cond, &cattr), 0);
+	pthread_condattr_destroy(&cattr);
+	pdata->ready = 0;
+	pdata->failed = 0;
+	pdata->go = false;
+}
+
+static void process_ready_and_wait(struct process_data *pdata)
+{
+	int ret = pthread_mutex_lock(&pdata->mutex);
+
+	if (ret == EOWNERDEAD)
+		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
+	else
+		igt_assert_eq(ret, 0);
+	pdata->ready++;
+	pthread_cond_broadcast(&pdata->cond);
+	while (!pdata->go)
+		pthread_cond_wait(&pdata->cond, &pdata->mutex);
+	pthread_mutex_unlock(&pdata->mutex);
+}
+
+static void process_setup_failed(struct process_data *pdata)
+{
+	int ret = pthread_mutex_lock(&pdata->mutex);
+
+	if (ret == EOWNERDEAD)
+		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
+	else
+		igt_assert_eq(ret, 0);
+	pdata->failed++;
+	pthread_cond_broadcast(&pdata->cond);
+	pthread_mutex_unlock(&pdata->mutex);
+}
+
+static void release_ready_processes(struct process_data *pdata, int n_proc)
+{
+	struct timespec timeout;
+	int ret;
+
+	ret = pthread_mutex_lock(&pdata->mutex);
+	if (ret == EOWNERDEAD)
+		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
+	else
+		igt_assert_eq(ret, 0);
+
+	clock_gettime(CLOCK_REALTIME, &timeout);
+	timeout.tv_sec += 30;
+	/*
+	 * Wait until all children have either reached VM Bind rendevouz
+	 * Or, failed setup and exited the test path.
+	 */
+	while (pdata->ready + pdata->failed < n_proc) {
+		ret = pthread_cond_timedwait(&pdata->cond, &pdata->mutex, &timeout);
+		if (ret == EOWNERDEAD) {
+			igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
+		} else if (ret == ETIMEDOUT) {
+			igt_warn("Timeout waiting for the child process: ready=%d, failed =%d, expected=%d",
+			pdata->ready, pdata->failed, n_proc);
+			break;
+		}
+		igt_assert_eq(ret, 0);
+	}
+
+	igt_debug("Process rendezvous: ready=%d failed=%d total = %d\n",
+		  pdata->ready, pdata->failed, n_proc);
+
+	/* Release every successful child into VM_Bind at same time*/
+	pdata->go = true;
+	pthread_cond_broadcast(&pdata->cond);
+	pthread_mutex_unlock(&pdata->mutex);
+}
+
+static int build_add_batch(struct gem_bo *batch_bo, struct gem_bo *integers_bo,
+			   struct gem_bo *result_bo, int ints_to_add)
+{
+	int pos = 0;
+	int i;
+	uint64_t tmp_addr;
+
+	batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | MI_LRI_LRM_CS_MMIO | 2;
+	batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
+	tmp_addr = integers_bo->addr + 0 * sizeof(uint32_t);
+	batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
+	batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
+	for (i = 1; i < ints_to_add; i++) {
+		/* r1 = integers_bo[i] */
+		batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | MI_LRI_LRM_CS_MMIO | 2;
+		batch_bo->ptr[pos++] = GPR_RX_ADDR(1);
+		tmp_addr = integers_bo->addr + i * sizeof(uint32_t);
+		batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
+		batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
+		/* r0 = r0 + r1 */
+		batch_bo->ptr[pos++] = MI_MATH(4);
+		batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(0));
+		batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(1));
+		batch_bo->ptr[pos++] = MI_MATH_ADD;
+		batch_bo->ptr[pos++] = MI_MATH_STORE(MI_MATH_REG(0), MI_MATH_REG_ACCU);
+	}
+	/* result_bo[0] = r0 */
+	batch_bo->ptr[pos++] = MI_STORE_REGISTER_MEM_GEN8 | MI_LRI_LRM_CS_MMIO;
+	batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
+	tmp_addr = result_bo->addr + 0 * sizeof(uint32_t);
+	batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
+	batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
+
+	batch_bo->ptr[pos++] = MI_BATCH_BUFFER_END;
+	while (pos % 4 != 0)
+		batch_bo->ptr[pos++] = MI_NOOP;
+	return pos;
+}
+
+static void create_exec_queue(int fd, struct xe_oversubscribe_ctx *ctx)
+{
+	ctx->exec_queue_id = xe_exec_queue_create(fd, ctx->vm_id,
+						  &xe_engine(fd, 0)->instance, 0);
+}
+
+static uint64_t *
+vm_bind_bo_batch(int fd, struct xe_oversubscribe_ctx *ctx, struct gem_bo *bos, int size,
+		 int *out_err)
+{
+	uint64_t *ufence;
+	struct drm_xe_sync bind_sync;
+	struct drm_xe_vm_bind_op *binds;
+	int i;
+
+	binds = calloc(size, sizeof(*binds));
+	igt_assert(binds);
+
+	ufence = calloc(1, sizeof(*ufence));
+	igt_assert(ufence);
+	bind_sync = (struct drm_xe_sync) {
+		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.addr = to_user_pointer(ufence),
+		.timeline_value = 1,
+	};
+
+	for (i = 0; i < size; i++) {
+		binds[i] = (struct drm_xe_vm_bind_op) {
+			.obj = bos[i].handle,
+			.obj_offset = 0,
+			.range = bos[i].size,
+			.addr = bos[i].addr,
+			.op = DRM_XE_VM_BIND_OP_MAP,
+			.flags = 0,
+		};
+	}
+	*out_err = __xe_vm_bind_array(fd, ctx->vm_id, binds, size, &bind_sync, 1);
+	free(binds);
+	return ufence;
+}
+
+/* Returns 1 (caller should skip exec) on an allowed OOM error, 0 otherwise. */
+static int bind_bos(int fd, struct xe_oversubscribe_ctx *ctx, struct gem_bo *bufs,
+		    struct mem_bind_sync *bind, int *bind_err, bool allow_oom)
+{
+	if (!bind->n_bufs)
+		return 0;
+
+	bind->binds_ufence = vm_bind_bo_batch(fd, ctx, bufs, bind->n_bufs, bind_err);
+
+	if (*bind_err) {
+		if (allow_oom) {
+			igt_assert_f(*bind_err == -ENOMEM || *bind_err == -ENOSPC,
+				     "Unexpected bind error: %d (%s)\n",
+				     *bind_err, strerror(-*bind_err));
+			igt_debug("Bind failed with expected OOM (%s), skipping exec\n",
+				  strerror(-*bind_err));
+			return 1;
+		}
+
+		igt_assert_f(false, "Unexpected bind error: %d", *bind_err);
+	}
+
+	xe_wait_ufence(fd, bind->binds_ufence, 1, 0, TIMEOUT_NS);
+	return 0;
+}
+
+static int fill_random_integers(struct gem_bo *int_bo, int ints_to_add)
+{
+	uint32_t expected_result = 0;
+	char expr[256];
+	int len = 0;
+
+	for (int i = 0; i < ints_to_add; i++) {
+		uint32_t random_int = rand() % 8;
+
+		int_bo->ptr[i] = random_int;
+		expected_result += random_int;
+
+		len += snprintf(expr + len, sizeof(expr) - len, "%s%u",
+				i ? " + " : "", random_int);
+	}
+	igt_debug("%s = %u\n", expr, expected_result);
+	return expected_result;
+}
+
+static void cleanup_bo_resources(int fd, struct gem_bo *bo)
+{
+	if (bo->ptr) {
+		igt_assert_eq(munmap(bo->ptr, bo->size), 0);
+		bo->ptr = NULL;
+	}
+	if (bo->handle)
+		gem_close(fd, bo->handle);
+}
+
+static int create_test_bos(int fd, struct xe_oversubscribe_ctx *ctx,
+			   struct mem_bind_sync *bind, uint32_t placement,
+			   uint64_t *addr)
+{
+	const char *mem_type = (placement & vram_memory(fd, 0)) ? "VRAM" : "SRAM";
+	int ret;
+
+	for (int i = 0; i < bind->n_bufs; i++) {
+		struct gem_bo *bo = &bind->bufs[i];
+
+		bo->size = GB(1);
+		ret = __xe_bo_create_caching(fd, ctx->vm_id, bo->size, placement, 0,
+					     DRM_XE_GEM_CPU_CACHING_WC, &bo->handle);
+		if (ret) {
+			int saved_errno = errno; /* capture before anything can clobber it */
+
+			bind->n_bufs = i;
+			if (saved_errno == ENOMEM || saved_errno == ENOSPC) {
+				/* Continue on OOM, expected when oversubscribing the VM */
+				igt_debug("%s allocation failed at buffer %d (OOM)\n", mem_type, i);
+				break;
+			}
+			/* We are returning as this is a fail scenario */
+			igt_warn("%s allocation failed at buffer %d: %s\n",
+				 mem_type, i, strerror(saved_errno));
+			return -saved_errno;
+		}
+		bo->ptr = NULL;
+		bo->addr = *addr;
+		*addr += bo->size;
+		igt_debug("%s buffer %d created at 0x%016lx\n", mem_type, i, bo->addr);
+	}
+	return 0;
+}
+
+static void cleanup_sram_vram_objs(int fd, struct mem_bind_sync *vram_bind,
+				   struct mem_bind_sync *sram_bind)
+{
+	for (int i = 0; i < vram_bind->n_bufs; i++)
+		gem_close(fd, vram_bind->bufs[i].handle);
+	for (int i = 0; i < sram_bind->n_bufs; i++)
+		gem_close(fd, sram_bind->bufs[i].handle);
+	free(vram_bind->bufs);
+	free(sram_bind->bufs);
+	if (vram_bind->binds_ufence)
+		free(vram_bind->binds_ufence);
+	if (sram_bind->binds_ufence)
+		free(sram_bind->binds_ufence);
+}
+
+static void create_bo(int fd, uint32_t vm, struct gem_bo *bo, uint64_t size,
+		      uint64_t addr, bool map_now)
+{
+	bo->size = ALIGN(size, 4096);
+	bo->handle = xe_bo_create_caching(fd, vm, bo->size, system_memory(fd), 0,
+					  DRM_XE_GEM_CPU_CACHING_WC);
+	igt_assert(bo->handle);
+	bo->addr = addr;
+	if (map_now) {
+		bo->ptr = xe_bo_map(fd, bo->handle, bo->size);
+		igt_assert(bo->ptr != MAP_FAILED);
+	} else {
+		bo->ptr = NULL;
+	}
+}
+
+static bool calc_oversubscribe_params(int fd, struct oversubscribe_params *p)
+{
+	uint64_t target_vram, target_sram;
+	uint64_t total_vram_bufs, total_sram_bufs, max_by_mem;
+
+	p->vram_size =  xe_visible_available_vram_size(fd, 0);
+	p->sram_size = (uint64_t)igt_get_avail_ram_mb() << 20;
+	/*
+	 * Dynamically cap VRAM oversubscription so the overflow into system
+	 * RAM stays within 25% of available RAM. On small-VRAM platforms
+	 * the 2x target fits within the cap and behavior is
+	 * unchanged; on large-VRAM platforms (e.g. PVC) this prevents OOM.
+	 */
+
+	target_vram = min(p->vram_size * 2, p->vram_size + p->sram_size / 4);
+	target_sram = min_t(uint64_t, p->sram_size * 50 / 100,
+			    MAX_SRAM_TEST_SIZE);
+	total_vram_bufs = target_vram / GB(1);
+	total_sram_bufs = target_sram / GB(1);
+	max_by_mem = min(total_vram_bufs / MIN_BUFS_PER_PROC,
+			 total_sram_bufs / MIN_BUFS_PER_PROC);
+
+	p->n_proc = min_t(int, max_by_mem, MAX_PROCS);
+	if (p->n_proc <= 0)
+		return false;
+	p->n_vram_bufs = max_t(int, 2, total_vram_bufs / p->n_proc);
+	p->n_sram_bufs = max_t(int, 2, total_sram_bufs / p->n_proc);
+	p->total_vram_demand = (uint64_t)p->n_proc * p->n_vram_bufs * GB(1);
+	return true;
+}
+
+static void test_vm_oversubscribe_concurrent_bind(int fd)
+{
+	struct oversubscribe_params p;
+	struct process_data *pdata;
+
+	igt_require_f(calc_oversubscribe_params(fd, &p),
+		      "Not enough VRAM/RAM for oversubscription test\n");
+
+	igt_debug("VRAM size: %" PRIu64 "MB, System RAM available: %" PRIu64 "MB\n",
+		  p.vram_size >> 20, p.sram_size >> 20);
+
+	igt_debug("n_proc = %d\n", p.n_proc);
+	igt_debug("VRAM: %" PRIu64 "GB\n", p.vram_size >> 30);
+	igt_debug("VRAM demand: %" PRIu64 "MB (%.2fx oversubscription)\n",
+		  p.total_vram_demand >> 20, (double)p.total_vram_demand / p.vram_size);
+	igt_debug("Processes=%d VRAM_bufs=%d SRAM_bufs=%d\n", p.n_proc,
+		  p.n_vram_bufs, p.n_sram_bufs);
+
+	pdata = mmap(NULL, sizeof(*pdata), PROT_READ | PROT_WRITE,
+		     MAP_SHARED | MAP_ANONYMOUS, -1, 0);
+	igt_assert(pdata != MAP_FAILED);
+	init_pdata(pdata);
+
+	igt_fork(child, p.n_proc) {
+		struct xe_oversubscribe_ctx ctx = {0};
+		int rc, ret, fd_c;
+		uint64_t addr = STRESS_BIND_ADDR;
+		uint32_t expected_result = 0;
+		struct gem_bo integers_bo = {0}, result_bo = {0}, batch_bo = {0};
+		struct gem_bo *vram_bufs, *sram_bufs;
+		int pos = 0;
+		struct mem_bind_sync vram_bind = {0};
+		struct mem_bind_sync sram_bind = {0};
+		struct drm_xe_sync batch_syncs[1];
+		struct drm_xe_exec exec;
+		struct gem_bo ufence_bo = {0};
+		int vram_bind_err = 0, sram_bind_err = 0;
+
+		vram_bufs = calloc(p.n_vram_bufs, sizeof(*vram_bufs));
+		sram_bufs = calloc(p.n_sram_bufs, sizeof(*sram_bufs));
+		srand(child);
+
+		fd_c = drm_open_driver(DRIVER_XE);
+
+		igt_assert(vram_bufs && sram_bufs);
+
+		ctx.vm_id = xe_vm_create(fd_c, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0);
+		create_exec_queue(fd_c, &ctx);
+		vram_bind.bufs = vram_bufs;
+		vram_bind.n_bufs = p.n_vram_bufs;
+		sram_bind.bufs = sram_bufs;
+		sram_bind.n_bufs = p.n_sram_bufs;
+
+		ret = create_test_bos(fd_c, &ctx, &vram_bind, vram_memory(fd_c, 0), &addr);
+		if (ret) {
+			process_setup_failed(pdata);
+			goto cleanup;
+		}
+
+		ret = create_test_bos(fd_c, &ctx, &sram_bind, system_memory(fd_c), &addr);
+		if (ret) {
+			process_setup_failed(pdata);
+			goto cleanup;
+		}
+
+		if (!vram_bind.n_bufs || !sram_bind.n_bufs) {
+			igt_debug("No BOs allocated; VRAM/SRAM unavailable, skipping\n");
+			process_setup_failed(pdata);
+			goto cleanup;
+		}
+
+		/*
+		 * All allocations are complete. Report Ready and wait until every
+		 * child has either reached this point or repported a setup failure.
+		 */
+
+		 process_ready_and_wait(pdata);
+
+		/*
+		 * VM_Bind starts only after the parent releases all ready
+		 * childen.
+		 */
+
+		if (bind_bos(fd_c, &ctx, vram_bufs, &vram_bind, &vram_bind_err, true))
+			goto cleanup;
+
+		if (bind_bos(fd_c, &ctx, sram_bufs, &sram_bind, &sram_bind_err, false))
+			goto cleanup;
+
+		create_bo(fd_c, ctx.vm_id, &integers_bo, 4096, EXEC_DATA_ADDR, true);
+		expected_result = fill_random_integers(&integers_bo, INT_ADD_CNT);
+		igt_debug("%d\n", expected_result);
+		create_bo(fd_c, ctx.vm_id, &result_bo, 4096, EXEC_RESULT_ADDR, false);
+		create_bo(fd_c, ctx.vm_id, &batch_bo, 4096, EXEC_BATCH_ADDR, true);
+		pos = build_add_batch(&batch_bo, &integers_bo, &result_bo, INT_ADD_CNT);
+
+		igt_assert(pos * sizeof(int) <= batch_bo.size);
+
+		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, integers_bo.handle, 0, integers_bo.addr,
+				   integers_bo.size, 0);
+		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, result_bo.handle, 0, result_bo.addr,
+				   result_bo.size, 0);
+		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, batch_bo.handle, 0, batch_bo.addr,
+				   batch_bo.size, 0);
+		create_bo(fd_c, ctx.vm_id, &ufence_bo, 4096, EXEC_UFENCE_ADDR, true);
+
+		memset(ufence_bo.ptr, 0, ufence_bo.size);
+		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, ufence_bo.handle, 0, ufence_bo.addr,
+				   ufence_bo.size, 0);
+
+		batch_syncs[0] = (struct drm_xe_sync){
+			.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+			.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+			.addr = ufence_bo.addr,
+			.timeline_value = USER_FENCE_VALUE,
+		};
+
+		exec = (struct drm_xe_exec) {
+			.exec_queue_id = ctx.exec_queue_id,
+			.num_syncs = 1,
+			.syncs = (uintptr_t)batch_syncs,
+			.address = batch_bo.addr,
+			.num_batch_buffer = 1,
+		};
+
+		rc = igt_ioctl(fd_c, DRM_IOCTL_XE_EXEC, &exec);
+		igt_assert_f(rc == 0, "xe_exec failed unexpectedly: %s (%d)\n",
+			     strerror(errno), errno);
+		xe_wait_ufence(fd_c, (uint64_t *)ufence_bo.ptr, USER_FENCE_VALUE, ctx.exec_queue_id,
+			       TIMEOUT_NS);
+		result_bo.ptr = xe_bo_map(fd_c, result_bo.handle, result_bo.size);
+		igt_assert(result_bo.ptr != MAP_FAILED);
+		igt_assert_eq(result_bo.ptr[0], expected_result);
+cleanup:
+		cleanup_bo_resources(fd_c, &ufence_bo);
+		cleanup_bo_resources(fd_c, &result_bo);
+		cleanup_bo_resources(fd_c, &batch_bo);
+		cleanup_bo_resources(fd_c, &integers_bo);
+		cleanup_sram_vram_objs(fd_c, &vram_bind, &sram_bind);
+		xe_exec_queue_destroy(fd_c, ctx.exec_queue_id);
+		xe_vm_destroy(fd_c, ctx.vm_id);
+		drm_close_driver(fd_c);
+	}
+
+	release_ready_processes(pdata, p.n_proc);
+	igt_waitchildren();
+	igt_reset_timeout();
+
+	pthread_cond_destroy(&pdata->cond);
+	pthread_mutex_destroy(&pdata->mutex);
+	igt_assert_eq(munmap(pdata, sizeof(*pdata)), 0);
+}
+
 static void alloc_sizes_init(void)
 {
 	int i;
@@ -986,6 +1512,7 @@ static const struct test_case test_matrix[] = {
 	{ "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING, TYPE_THREAD, false },
 	{ "threads-leak-binding-rand-sizes-50-unaligned", 50, LEAK_BINDING | UNALIGNED,
 	  TYPE_THREAD, false },
+	{ "test_vm_oversubscribe_concurrent_bind", 0, 0, TYPE_OVERSUBSCRIBE, false},
 };
 
 int igt_main()
@@ -1011,6 +1538,10 @@ int igt_main()
 				run_threaded_bo_alloc_test(fd, t->count, t->flags);
 			}
 			break;
+		case TYPE_OVERSUBSCRIBE:
+			igt_subtest_f("%s", t->name)
+				test_vm_oversubscribe_concurrent_bind(fd);
+			break;
 		case TYPE_ALL_SIZES:
 		case TYPE_RANDOM_SIZE:
 		case TYPE_ARRAY_BIND:
-- 
2.52.0

✓ i915.CI.BAT: success for Add BO Allocation and VM Bind stress infra (rev4)

[Patchwork]

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== Series Details ==

Series: Add BO Allocation and VM Bind stress infra (rev4)
URL   : https://patchwork.freedesktop.org/series/172310/
State : success

== Summary ==

CI Bug Log - changes from IGT_9109 -> IGTPW_15885
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/index.html

Participating hosts (39 -> 38)
------------------------------

  Missing    (1): bat-dg2-13 

Known issues
------------

  Here are the changes found in IGTPW_15885 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live:
    - fi-hsw-4770:        [INCOMPLETE][1] ([i915#17144]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9109/fi-hsw-4770/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/fi-hsw-4770/igt@i915_selftest@live.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-kbl-7567u:       [DMESG-WARN][3] ([i915#13735]) -> [PASS][4] +79 other tests pass
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9109/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-7567u:       [DMESG-WARN][5] ([i915#13735] / [i915#180]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9109/fi-kbl-7567u/igt@kms_busy@basic@flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/fi-kbl-7567u/igt@kms_busy@basic@flip.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-kbl-7567u:       [DMESG-WARN][7] ([i915#13735] / [i915#15673] / [i915#180]) -> [PASS][8] +52 other tests pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9109/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html

  
  [i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
  [i915#15673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15673
  [i915#17144]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17144
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_9109 -> IGTPW_15885
  * Linux: CI_DRM_19203 -> CI_DRM_19205

  CI-20190529: 20190529
  CI_DRM_19203: 3413ca5893855693d3cc12697713842547261439 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_19205: 7cdd31de20cd320f9a1539bb5c3949275326f017 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_15885: 562a7eb5931347113b319d03004edf87b6843196 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_9109: 65f84b280be2caf8ce376295d97987a808affdee @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/index.html

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✓ Xe.CI.BAT: success for Add BO Allocation and VM Bind stress infra (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4697 bytes --]

== Series Details ==

Series: Add BO Allocation and VM Bind stress infra (rev4)
URL   : https://patchwork.freedesktop.org/series/172310/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_9109_BAT -> XEIGTPW_15885_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_15885_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_exec_fault_mode@twice-invalid-userptr-fault:
    - bat-bmg-2:          [PASS][1] -> [DMESG-WARN][2] ([Intel XE#9331])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-2/igt@xe_exec_fault_mode@twice-invalid-userptr-fault.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-2/igt@xe_exec_fault_mode@twice-invalid-userptr-fault.html

  * igt@xe_exec_fault_mode@twice-rebind-prefetch:
    - bat-bmg-1:          [PASS][3] -> [DMESG-WARN][4] ([Intel XE#9331])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-1/igt@xe_exec_fault_mode@twice-rebind-prefetch.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-1/igt@xe_exec_fault_mode@twice-rebind-prefetch.html

  * igt@xe_exec_system_allocator@many-execqueues-free:
    - bat-bmg-vm:         [PASS][5] -> [DMESG-WARN][6] ([Intel XE#9331])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-vm/igt@xe_exec_system_allocator@many-execqueues-free.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-vm/igt@xe_exec_system_allocator@many-execqueues-free.html

  * igt@xe_multigpu_svm@mgpu-latency-copy-prefetch:
    - bat-bmg-3:          [PASS][7] -> [DMESG-WARN][8] ([Intel XE#9331])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-3/igt@xe_multigpu_svm@mgpu-latency-copy-prefetch.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-3/igt@xe_multigpu_svm@mgpu-latency-copy-prefetch.html

  * igt@xe_waitfence@reltime:
    - bat-wcl-2:          [PASS][9] -> [FAIL][10] ([Intel XE#9115])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-wcl-2/igt@xe_waitfence@reltime.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-wcl-2/igt@xe_waitfence@reltime.html
    - bat-wcl-1:          [PASS][11] -> [FAIL][12] ([Intel XE#9115])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-wcl-1/igt@xe_waitfence@reltime.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-wcl-1/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@xe_exec_fault_mode@twice-userptr-rebind-prefetch:
    - bat-bmg-1:          [DMESG-WARN][13] ([Intel XE#9331]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-1/igt@xe_exec_fault_mode@twice-userptr-rebind-prefetch.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-1/igt@xe_exec_fault_mode@twice-userptr-rebind-prefetch.html

  * igt@xe_exec_system_allocator@many-execqueues-malloc:
    - bat-bmg-vm:         [DMESG-WARN][15] ([Intel XE#9331]) -> [PASS][16] +1 other test pass
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-vm/igt@xe_exec_system_allocator@many-execqueues-malloc.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-vm/igt@xe_exec_system_allocator@many-execqueues-malloc.html

  * igt@xe_multigpu_svm@mgpu-pagefault-basic:
    - bat-bmg-3:          [DMESG-WARN][17] ([Intel XE#9331]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/bat-bmg-3/igt@xe_multigpu_svm@mgpu-pagefault-basic.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/bat-bmg-3/igt@xe_multigpu_svm@mgpu-pagefault-basic.html

  
  [Intel XE#9115]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9115
  [Intel XE#9331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9331


Build changes
-------------

  * IGT: IGT_9109 -> IGTPW_15885
  * Linux: xe-5807-3413ca5893855693d3cc12697713842547261439 -> xe-5810-7cdd31de20cd320f9a1539bb5c3949275326f017

  IGTPW_15885: 562a7eb5931347113b319d03004edf87b6843196 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_9109: 65f84b280be2caf8ce376295d97987a808affdee @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5807-3413ca5893855693d3cc12697713842547261439: 3413ca5893855693d3cc12697713842547261439
  xe-5810-7cdd31de20cd320f9a1539bb5c3949275326f017: 7cdd31de20cd320f9a1539bb5c3949275326f017

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/index.html

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✗ i915.CI.Full: failure for Add BO Allocation and VM Bind stress infra (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 149154 bytes --]

== Series Details ==

Series: Add BO Allocation and VM Bind stress infra (rev4)
URL   : https://patchwork.freedesktop.org/series/172310/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19205_full -> IGTPW_15885_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_15885_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_15885_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/index.html

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): pig-kbl-iris 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_15885_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-rkl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-4/igt@gem_mmap_gtt@cpuset-big-copy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@i915_suspend@forcewake:
    - shard-mtlp:         [PASS][3] -> [TIMEOUT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-5/igt@i915_suspend@forcewake.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@i915_suspend@forcewake.html

  * igt@kms_pm_dc@dc5-dpms-suspend-resume:
    - shard-mtlp:         [PASS][5] -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-4/igt@kms_pm_dc@dc5-dpms-suspend-resume.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_pm_dc@dc5-dpms-suspend-resume.html

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-4.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-mtlp:         [PASS][8] -> [FAIL][9] +1 other test fail
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-4/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-4/igt@kms_vblank@ts-continuation-dpms-suspend.html

  
Known issues
------------

  Here are the changes found in IGTPW_15885_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#14544] / [i915#6230])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@api_intel_bb@crc32.html

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-dg1:          NOTRUN -> [SKIP][11] ([i915#8411])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@gem_basic@multigpu-create-close:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@gem_basic@multigpu-create-close.html

  * igt@gem_caching@writes:
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#4873])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@gem_caching@writes.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu:         NOTRUN -> [SKIP][14] ([i915#3555] / [i915#9323])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-3/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][15] ([i915#3555] / [i915#9323])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy.html
    - shard-dg1:          NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9323])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([i915#9323]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-tglu:         NOTRUN -> [SKIP][18] ([i915#7697])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#7697])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-tglu-1:       NOTRUN -> [SKIP][20] ([i915#6335])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gem_create@create-ext-cpu-access-big.html
    - shard-rkl:          NOTRUN -> [SKIP][21] ([i915#6335])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_freq@sysfs@gt0:
    - shard-dg2:          [PASS][22] -> [FAIL][23] ([i915#9561]) +1 other test fail
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg2-8/igt@gem_ctx_freq@sysfs@gt0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-6/igt@gem_ctx_freq@sysfs@gt0.html

  * igt@gem_ctx_isolation@preservation-s3@ccs0:
    - shard-mtlp:         NOTRUN -> [ABORT][24] ([i915#17175])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_ctx_isolation@preservation-s3@ccs0.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk:          NOTRUN -> [INCOMPLETE][25] ([i915#13356] / [i915#16466]) +1 other test incomplete
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk9/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-dg1:          NOTRUN -> [SKIP][26] ([i915#8555])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_ctx_persistence@idempotent:
    - shard-snb:          NOTRUN -> [SKIP][27] ([i915#1099])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-snb6/igt@gem_ctx_persistence@idempotent.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-rkl:          NOTRUN -> [SKIP][28] ([i915#280])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@in-flight-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][29] ([i915#13356] / [i915#13390])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk4/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@bonded-semaphore:
    - shard-mtlp:         NOTRUN -> [SKIP][30] ([i915#4812])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_exec_balancer@bonded-semaphore.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg1:          NOTRUN -> [SKIP][31] ([i915#4771])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg1:          NOTRUN -> [SKIP][32] ([i915#4036])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@noheartbeat:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#8555]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@gem_exec_balancer@noheartbeat.html

  * igt@gem_exec_balancer@parallel:
    - shard-tglu:         NOTRUN -> [SKIP][34] ([i915#4525]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][35] ([i915#4525]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#4525]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_flush@basic-uc-pro-default:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#3539] / [i915#4852]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@gem_exec_flush@basic-uc-pro-default.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg1:          NOTRUN -> [SKIP][38] ([i915#3539])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_flush@basic-wb-rw-default:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#3539] / [i915#4852])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-8/igt@gem_exec_flush@basic-wb-rw-default.html

  * igt@gem_exec_reloc@basic-gtt-wc-active:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#3281]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@gem_exec_reloc@basic-gtt-wc-active.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-rkl:          NOTRUN -> [SKIP][41] ([i915#3281]) +4 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_reloc@basic-write-cpu-active:
    - shard-dg1:          NOTRUN -> [SKIP][42] ([i915#3281]) +12 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@gem_exec_reloc@basic-write-cpu-active.html

  * igt@gem_exec_reloc@basic-write-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#14544] / [i915#3281]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@gem_exec_reloc@basic-write-gtt-active:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#3281]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@gem_exec_reloc@basic-write-gtt-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg1:          NOTRUN -> [SKIP][45] ([i915#4812]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [PASS][46] -> [INCOMPLETE][47] ([i915#13356]) +1 other test incomplete
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg2-7/igt@gem_exec_suspend@basic-s0.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-none:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4860]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@gem_fence_thrash@bo-write-verify-threaded-none.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglu:         NOTRUN -> [SKIP][49] ([i915#2190])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@gem_huc_copy@huc-copy.html
    - shard-glk:          NOTRUN -> [SKIP][50] ([i915#2190])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk9/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu:         NOTRUN -> [SKIP][51] ([i915#4613] / [i915#7582])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#4613]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][53] ([i915#4613]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-glk:          NOTRUN -> [SKIP][54] ([i915#4613]) +5 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk9/igt@gem_lmem_swapping@random-engines.html
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#4613]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][56] ([i915#4613]) +5 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_media_vme:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#284])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@gem_media_vme.html
    - shard-tglu-1:       NOTRUN -> [SKIP][58] ([i915#284])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gem_media_vme.html
    - shard-dg1:          NOTRUN -> [SKIP][59] ([i915#284])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@gem_media_vme.html

  * igt@gem_mmap@basic-small-bo:
    - shard-mtlp:         NOTRUN -> [SKIP][60] ([i915#4083]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-3/igt@gem_mmap@basic-small-bo.html

  * igt@gem_mmap_gtt@basic-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#4077]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@gem_mmap_gtt@basic-wc.html

  * igt@gem_mmap_wc@write:
    - shard-dg1:          NOTRUN -> [SKIP][62] ([i915#4083]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@gem_mmap_wc@write.html

  * igt@gem_mmap_wc@write-read:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#4083])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-8/igt@gem_mmap_wc@write-read.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#3282]) +3 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pread@exhaustion:
    - shard-tglu:         NOTRUN -> [WARN][65] ([i915#2658])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@gem_pread@exhaustion.html

  * igt@gem_pread@snoop:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#3282]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@gem_pread@snoop.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg1:          NOTRUN -> [SKIP][67] ([i915#4270]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][68] ([i915#13717])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#13398])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#4270])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_readwrite@beyond-eob:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#3282]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@gem_readwrite@beyond-eob.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][72] ([i915#8428])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-3/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#5190] / [i915#8428])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#4079])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#8411])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_tiled_partial_pwrite_pread@reads:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#3282]) +5 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@gem_tiled_partial_pwrite_pread@reads.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#3297]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-dg1:          NOTRUN -> [SKIP][78] ([i915#3297]) +4 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglu:         NOTRUN -> [SKIP][79] ([i915#3297] / [i915#3323])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-mtlp:         NOTRUN -> [SKIP][80] ([i915#3297])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-glk:          NOTRUN -> [SKIP][81] ([i915#3323])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk8/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-rkl:          NOTRUN -> [SKIP][82] ([i915#3297] / [i915#3323])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#3282] / [i915#3297])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][84] ([i915#3297]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@sd-probe:
    - shard-dg1:          NOTRUN -> [SKIP][85] ([i915#3297] / [i915#4958])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@gem_userptr_blits@sd-probe.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#3297])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#3297]) +2 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume:
    - shard-glk:          NOTRUN -> [INCOMPLETE][88] ([i915#13356] / [i915#14586]) +1 other test incomplete
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk8/igt@gem_workarounds@suspend-resume.html
    - shard-rkl:          NOTRUN -> [INCOMPLETE][89] ([i915#13356])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@gem_workarounds@suspend-resume.html

  * igt@gen3_render_linear_blits:
    - shard-dg2:          NOTRUN -> [SKIP][90] +9 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@gen3_render_linear_blits.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk11:        NOTRUN -> [ABORT][91] ([i915#5566])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk11/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@batch-without-end:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#2856])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@gen9_exec_parse@batch-without-end.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#2527] / [i915#2856]) +4 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-3/igt@gen9_exec_parse@bb-oversize.html
    - shard-mtlp:         NOTRUN -> [SKIP][94] ([i915#2856])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#2527] / [i915#2856])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-dg1:          NOTRUN -> [SKIP][96] ([i915#2527]) +3 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@gen9_exec_parse@shadow-peek.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#2527]) +2 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@gen9_exec_parse@valid-registers.html

  * igt@gpu_buddy@gpu_buddy:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] ([i915#15678])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@gpu_buddy@gpu_buddy.html
    - shard-dg1:          NOTRUN -> [SKIP][99] ([i915#15678])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@gpu_buddy@gpu_buddy.html

  * igt@i915_drm_fdinfo@all-busy-check-all:
    - shard-mtlp:         NOTRUN -> [SKIP][100] ([i915#14123])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-3/igt@i915_drm_fdinfo@all-busy-check-all.html
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#14123])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-6/igt@i915_drm_fdinfo@all-busy-check-all.html

  * igt@i915_drm_fdinfo@busy-hang@vcs0:
    - shard-dg1:          NOTRUN -> [SKIP][102] ([i915#14073]) +5 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@i915_drm_fdinfo@busy-hang@vcs0.html

  * igt@i915_module_load@fault-injection:
    - shard-dg2:          NOTRUN -> [ABORT][103] ([i915#15342] / [i915#15481])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@i915_module_load@fault-injection.html

  * igt@i915_module_load@fault-injection@__uc_init:
    - shard-dg2:          NOTRUN -> [ABORT][104] ([i915#15481])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@i915_module_load@fault-injection@__uc_init.html
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#14544] / [i915#15479]) +4 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@i915_module_load@fault-injection@__uc_init.html

  * igt@i915_module_load@fault-injection@intel_connector_register:
    - shard-rkl:          NOTRUN -> [ABORT][106] ([i915#15342]) +1 other test abort
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@i915_module_load@fault-injection@intel_connector_register.html
    - shard-dg2:          NOTRUN -> [DMESG-WARN][107] ([i915#15342])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@i915_module_load@fault-injection@intel_connector_register.html

  * igt@i915_module_load@resize-bar:
    - shard-tglu-1:       NOTRUN -> [SKIP][108] ([i915#6412])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][109] ([i915#8399])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#6590]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-7/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-rkl:          NOTRUN -> [SKIP][111] ([i915#14498])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-glk:          NOTRUN -> [INCOMPLETE][112] ([i915#13356] / [i915#15172])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk5/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#11681] / [i915#6621])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_pm_rps@thresholds:
    - shard-dg1:          NOTRUN -> [SKIP][114] ([i915#11681]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@i915_pm_rps@thresholds.html

  * igt@i915_power@sanity:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#7984])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@i915_power@sanity.html

  * igt@i915_query@query-topology-unsupported:
    - shard-dg1:          NOTRUN -> [SKIP][116] ([i915#16079])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@i915_query@query-topology-unsupported.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-dg1:          NOTRUN -> [SKIP][117] ([i915#5723])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_selftest@mock:
    - shard-tglu:         NOTRUN -> [ABORT][118] ([i915#17076]) +1 other test abort
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-3/igt@i915_selftest@mock.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-rkl:          [PASS][119] -> [INCOMPLETE][120] ([i915#4817])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@i915_suspend@fence-restore-untiled.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@i915_suspend@fence-restore-untiled.html
    - shard-glk11:        NOTRUN -> [INCOMPLETE][121] ([i915#13356] / [i915#16182] / [i915#4817])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk11/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - shard-dg1:          NOTRUN -> [SKIP][122] ([i915#4212]) +4 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#12454] / [i915#12712])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#12454] / [i915#12712])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [FAIL][125] ([i915#14888]) +2 other tests fail
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk8/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-2.html

  * igt@kms_atomic@plane-primary-legacy:
    - shard-snb:          NOTRUN -> [FAIL][126] ([i915#17126]) +5 other tests fail
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-snb7/igt@kms_atomic@plane-primary-legacy.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-tglu-1:       NOTRUN -> [SKIP][127] ([i915#9531])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][128] ([i915#1769])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
    - shard-dg1:          NOTRUN -> [SKIP][129] ([i915#1769] / [i915#3555])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#5286]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-tglu:         NOTRUN -> [SKIP][131] ([i915#5286]) +5 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-7/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][132] ([i915#5286])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][133] ([i915#4538] / [i915#5286]) +4 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][134] ([i915#5286]) +4 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#3638]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][136] +8 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#3828]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#4538] / [i915#5190]) +4 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][139] ([i915#3638]) +3 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][140] ([i915#4538]) +6 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#5190])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-7/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#10307] / [i915#6095]) +69 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-glk11:        NOTRUN -> [SKIP][143] +95 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk11/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][145] +573 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk8/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#14098] / [i915#14544] / [i915#6095]) +3 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#12313])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-glk10:        NOTRUN -> [SKIP][148] +109 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][149] ([i915#6095]) +44 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][150] ([i915#12805])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][151] ([i915#12805])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][152] ([i915#6095]) +3 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-mtlp:         [PASS][153] -> [FAIL][154] ([i915#17158]) +3 other tests fail
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][155] ([i915#13356] / [i915#15582]) +1 other test incomplete
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk9/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#14098] / [i915#6095]) +43 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][157] ([i915#12313])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][158] ([i915#12313]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][159] ([i915#6095]) +74 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#14544] / [i915#6095]) +3 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][161] ([i915#6095]) +163 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][162] ([i915#12313])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][163] ([i915#6095]) +65 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][164] ([i915#13781]) +4 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_cdclk@plane-scaling@pipe-c-edp-1.html

  * igt@kms_chamelium_audio@hdmi-audio-after-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#11151]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html
    - shard-tglu-1:       NOTRUN -> [SKIP][166] ([i915#11151])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-dg1:          NOTRUN -> [SKIP][167] ([i915#11151] / [i915#7828]) +9 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-16/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d:
    - shard-mtlp:         NOTRUN -> [SKIP][168] ([i915#16464] / [i915#16471])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_chamelium_color_pipeline@plane-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4-lut1d:
    - shard-tglu:         NOTRUN -> [SKIP][169] ([i915#16471]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-lut1d:
    - shard-dg1:          NOTRUN -> [SKIP][170] ([i915#16471]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_chamelium_color_pipeline@plane-lut1d-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut3d-green-only:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#16471])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-dg2:          NOTRUN -> [SKIP][172] ([i915#11151] / [i915#7828]) +2 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][173] ([i915#11151] / [i915#7828]) +7 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#11151] / [i915#14544] / [i915#7828])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-rkl:          NOTRUN -> [SKIP][175] ([i915#11151] / [i915#7828]) +9 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][176] ([i915#11151] / [i915#7828]) +3 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-tglu:         NOTRUN -> [SKIP][177] ([i915#11151] / [i915#7828]) +6 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-7/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lut1d@pipe-b-plane-0:
    - shard-tglu:         NOTRUN -> [FAIL][178] ([i915#17116]) +38 other tests fail
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-9/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lut1d@pipe-b-plane-0.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020@pipe-a-plane-2:
    - shard-dg1:          NOTRUN -> [FAIL][179] ([i915#17116]) +51 other tests fail
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020@pipe-a-plane-2.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lut1d@pipe-d-plane-2:
    - shard-tglu-1:       NOTRUN -> [FAIL][180] ([i915#17116]) +12 other tests fail
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lut1d@pipe-d-plane-2.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d@pipe-b-plane-0:
    - shard-mtlp:         NOTRUN -> [FAIL][181] ([i915#15733]) +25 other tests fail
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-3/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d@pipe-b-plane-0.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d@pipe-b-plane-2:
    - shard-rkl:          NOTRUN -> [FAIL][182] ([i915#17116]) +9 other tests fail
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d@pipe-b-plane-2.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d@pipe-d-plane-1:
    - shard-dg2:          NOTRUN -> [FAIL][183] ([i915#17116]) +12 other tests fail
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-6/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d@pipe-d-plane-1.html

  * igt@kms_color_pipeline@plane-lut1d:
    - shard-snb:          NOTRUN -> [SKIP][184] +547 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-snb6/igt@kms_color_pipeline@plane-lut1d.html

  * igt@kms_color_pipeline@plane-lut1d-ctm3x4-lut1d@pipe-a-plane-3:
    - shard-mtlp:         NOTRUN -> [SKIP][185] ([i915#16990]) +7 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_color_pipeline@plane-lut1d-ctm3x4-lut1d@pipe-a-plane-3.html

  * igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-d-plane-5:
    - shard-tglu:         NOTRUN -> [SKIP][186] ([i915#16990]) +15 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-d-plane-5.html

  * igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4@pipe-d-plane-4:
    - shard-dg1:          NOTRUN -> [SKIP][187] ([i915#16990]) +47 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-16/igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4@pipe-d-plane-4.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#14544] / [i915#15865])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][189] ([i915#15330] / [i915#3116] / [i915#3299]) +2 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#15330] / [i915#3299])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#15330] / [i915#3116])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#15865])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-6/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][193] ([i915#15865]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-9/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          NOTRUN -> [SKIP][194] ([i915#15865]) +1 other test skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-rkl:          NOTRUN -> [SKIP][195] ([i915#15865]) +1 other test skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_content_protection@srm.html
    - shard-mtlp:         NOTRUN -> [SKIP][196] ([i915#15865]) +2 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#3555])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         NOTRUN -> [FAIL][198] ([i915#13566]) +1 other test fail
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          [PASS][199] -> [FAIL][200] ([i915#13566]) +1 other test fail
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][201] ([i915#13049])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-mtlp:         NOTRUN -> [SKIP][202] ([i915#13049])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][203] ([i915#13566])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][204] ([i915#13049])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][205] ([i915#13049]) +3 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][206] ([i915#3555]) +8 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-mtlp:         NOTRUN -> [SKIP][207] ([i915#8814])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][208] ([i915#3555])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][209] ([i915#13049]) +1 other test skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-mtlp:         NOTRUN -> [INCOMPLETE][210] ([i915#12358]) +1 other test incomplete
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-8/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#14544]) +5 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#13046] / [i915#5354]) +1 other test skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-7/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-tglu:         NOTRUN -> [SKIP][213] ([i915#9067])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][214] ([i915#4103])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#4103])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-16/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-tglu-1:       NOTRUN -> [SKIP][216] ([i915#9723])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
    - shard-dg1:          NOTRUN -> [SKIP][217] ([i915#9723])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#3555])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
    - shard-rkl:          NOTRUN -> [SKIP][219] ([i915#3555] / [i915#3804])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][220] ([i915#3804])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2:          NOTRUN -> [SKIP][221] ([i915#13749])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-8/igt@kms_dp_link_training@non-uhbr-mst.html
    - shard-rkl:          NOTRUN -> [SKIP][222] ([i915#13749]) +1 other test skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_dp_link_training@non-uhbr-mst.html
    - shard-tglu-1:       NOTRUN -> [SKIP][223] ([i915#13749])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg1:          NOTRUN -> [SKIP][224] ([i915#13749])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#13748])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_dp_link_training@uhbr-sst.html
    - shard-dg1:          NOTRUN -> [SKIP][226] ([i915#13748]) +1 other test skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_dp_link_training@uhbr-sst.html
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#13748])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-dg1:          NOTRUN -> [SKIP][228] ([i915#16867])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][229] ([i915#13707])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback:
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#16870])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#16361])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@kms_dsc@dsc-fractional-bpp.html
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#14544] / [i915#16361])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
    - shard-dg1:          NOTRUN -> [SKIP][233] ([i915#16361]) +4 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-fractional-bpp-bigjoiner:
    - shard-tglu:         NOTRUN -> [SKIP][234] ([i915#16361]) +2 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@kms_dsc@dsc-fractional-bpp-bigjoiner.html

  * igt@kms_dsc@dsc-fractional-bpp-ultrajoiner:
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#16361]) +1 other test skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_dsc@dsc-fractional-bpp-ultrajoiner.html

  * igt@kms_dsc@dsc-with-formats-ultrajoiner:
    - shard-mtlp:         NOTRUN -> [SKIP][236] ([i915#16361])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-4/igt@kms_dsc@dsc-with-formats-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][237] ([i915#16361])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-rkl:          [PASS][238] -> [ABORT][239] ([i915#15132])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@kms_fbcon_fbt@fbc-suspend.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][240] ([i915#16680])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-8/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-rkl:          NOTRUN -> [SKIP][241] ([i915#16081])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@kms_feature_discovery@display-2x.html
    - shard-mtlp:         NOTRUN -> [SKIP][242] ([i915#16081]) +1 other test skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-8/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-dg2:          NOTRUN -> [SKIP][243] ([i915#16081])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-7/igt@kms_feature_discovery@display-4x.html
    - shard-dg1:          NOTRUN -> [SKIP][244] ([i915#16081])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_feature_discovery@display-4x.html
    - shard-tglu:         NOTRUN -> [SKIP][245] ([i915#16081])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-tglu:         NOTRUN -> [SKIP][246] ([i915#16599])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@dsc:
    - shard-tglu-1:       NOTRUN -> [SKIP][247] ([i915#16600])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_feature_discovery@dsc.html

  * igt@kms_feature_discovery@vrr:
    - shard-rkl:          NOTRUN -> [SKIP][248] ([i915#16600])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_feature_discovery@vrr.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-tglu:         NOTRUN -> [SKIP][249] ([i915#3637] / [i915#9934]) +9 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-3/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-tglu-1:       NOTRUN -> [SKIP][250] ([i915#3637] / [i915#9934]) +6 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-dg2:          NOTRUN -> [SKIP][251] ([i915#9934]) +3 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][252] ([i915#3637] / [i915#9934]) +2 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][253] ([i915#12745] / [i915#13356] / [i915#4839])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk11/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][254] ([i915#12745] / [i915#13356])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk11/igt@kms_flip@2x-flip-vs-suspend-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][255] ([i915#9934]) +7 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-dg1:          NOTRUN -> [SKIP][256] ([i915#9934]) +9 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip@blocking-wf_vblank@a-hdmi-a1:
    - shard-rkl:          [PASS][257] -> [FAIL][258] ([i915#14600]) +1 other test fail
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-2/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][259] ([i915#8381])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][260] ([i915#8381])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][261] ([i915#15643] / [i915#5190])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][262] ([i915#15643]) +1 other test skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][263] ([i915#3555] / [i915#8810] / [i915#8813]) +1 other test skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#15643])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
    - shard-dg1:          NOTRUN -> [SKIP][265] ([i915#15643]) +2 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][266] ([i915#15643])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][267] ([i915#15643]) +4 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
    - shard-tglu:         NOTRUN -> [SKIP][268] ([i915#15643]) +4 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][269] ([i915#4423])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][270] ([i915#15990] / [i915#8708]) +8 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][271] +91 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-shrfb-fliptrack-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][272] ([i915#15990]) +3 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbchdr-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][273] +92 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-spr-indfb-fullscreen:
    - shard-mtlp:         NOTRUN -> [SKIP][274] ([i915#15991]) +18 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-shrfb-draw-pwrite:
    - shard-glk:          [PASS][275] -> [SKIP][276] +2 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-shrfb-draw-pwrite.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk5/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbchdr-tiling-4:
    - shard-dg1:          NOTRUN -> [SKIP][277] ([i915#5439])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_frontbuffer_tracking@fbchdr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-tglu-1:       NOTRUN -> [SKIP][278] +79 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][279] ([i915#1825]) +9 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][280] ([i915#15991] / [i915#1825]) +5 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][281] ([i915#15102]) +29 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][282] ([i915#5439])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][283] ([i915#14544] / [i915#15102]) +1 other test skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][284] ([i915#15102]) +37 other tests skip
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-indfb-msflip-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][285] ([i915#15989]) +13 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][286] ([i915#5439])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-linear:
    - shard-dg2:          NOTRUN -> [SKIP][287] ([i915#15102]) +9 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-linear.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][288] ([i915#15989]) +16 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][289] ([i915#15989]) +4 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-pwrite.html
    - shard-rkl:          NOTRUN -> [SKIP][290] ([i915#15989]) +20 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][291] ([i915#15989]) +24 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][292] ([i915#15990]) +9 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-shrfb-plflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][293] ([i915#15989]) +18 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@hdr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][294] ([i915#15991]) +16 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@kms_frontbuffer_tracking@hdr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@hdr-shrfb-scaledprimary:
    - shard-rkl:          [PASS][295] -> [SKIP][296] ([i915#15989]) +3 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-shrfb-scaledprimary.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_frontbuffer_tracking@hdr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][297] ([i915#15102]) +41 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][298] ([i915#15991] / [i915#5354]) +6 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][299] ([i915#15990] / [i915#8708]) +6 other tests skip
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][300] ([i915#15990] / [i915#8708]) +3 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-tglu:         NOTRUN -> [SKIP][301] ([i915#15102]) +43 other tests skip
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][302] +96 other tests skip
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-7/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][303] ([i915#15990]) +28 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_getfb@getfb-handle-zero:
    - shard-dg1:          [PASS][304] -> [DMESG-WARN][305] ([i915#4423])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-16/igt@kms_getfb@getfb-handle-zero.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_getfb@getfb-handle-zero.html

  * igt@kms_hdmi_audio_bw@suspend-mem-audio-recovery:
    - shard-glk:          NOTRUN -> [INCOMPLETE][306] ([i915#13356])
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk3/igt@kms_hdmi_audio_bw@suspend-mem-audio-recovery.html

  * igt@kms_hdr@invalid-hdr:
    - shard-tglu-1:       NOTRUN -> [SKIP][307] ([i915#3555] / [i915#8228])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][308] ([i915#3555] / [i915#8228])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][309] ([i915#3555] / [i915#8228])
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][310] ([i915#15460])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_joiner@basic-big-joiner.html
    - shard-mtlp:         NOTRUN -> [SKIP][311] ([i915#15460])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-8/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][312] ([i915#15459])
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][313] ([i915#15458]) +1 other test skip
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-7/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-dg1:          NOTRUN -> [SKIP][314] ([i915#16451])
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][315] ([i915#15815])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
    - shard-dg1:          NOTRUN -> [SKIP][316] ([i915#15815])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-rkl:          [PASS][317] -> [INCOMPLETE][318] ([i915#12756] / [i915#13476])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-8/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][319] ([i915#12756])
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2.html

  * igt@kms_pipe_stress@stress-xrgb8888-xtiled:
    - shard-glk:          NOTRUN -> [DMESG-FAIL][320] ([i915#118])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk3/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-tglu:         NOTRUN -> [SKIP][321] ([i915#14712])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
    - shard-mtlp:         NOTRUN -> [SKIP][322] ([i915#14712])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
    - shard-glk:          NOTRUN -> [DMESG-FAIL][323] ([i915#118] / [i915#16396])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk3/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-mtlp:         NOTRUN -> [SKIP][324] ([i915#15709]) +3 other tests skip
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping:
    - shard-tglu-1:       NOTRUN -> [SKIP][325] ([i915#15709])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-rkl:          NOTRUN -> [SKIP][326] ([i915#15709]) +2 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-a-plane-7:
    - shard-tglu:         NOTRUN -> [SKIP][327] ([i915#16386]) +1 other test skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-3/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-a-plane-7.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-dg1:          NOTRUN -> [SKIP][328] ([i915#15709]) +5 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping:
    - shard-dg2:          NOTRUN -> [SKIP][329] ([i915#15709]) +1 other test skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-1/igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][330] ([i915#16386]) +1 other test skip
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7.html
    - shard-dg1:          NOTRUN -> [SKIP][331] ([i915#16386]) +1 other test skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-tglu:         NOTRUN -> [SKIP][332] ([i915#15709]) +4 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][333] ([i915#13026] / [i915#13356]) +1 other test incomplete
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk10/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
    - shard-rkl:          [PASS][334] -> [INCOMPLETE][335] ([i915#14412])
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb:
    - shard-glk:          NOTRUN -> [FAIL][336] ([i915#10647] / [i915#12177])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk2/igt@kms_plane_alpha_blend@alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][337] ([i915#10647]) +1 other test fail
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk2/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][338] ([i915#3555]) +4 other tests skip
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-tglu-1:       NOTRUN -> [SKIP][339] ([i915#13958]) +1 other test skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-dg1:          NOTRUN -> [SKIP][340] ([i915#13958])
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-tglu-1:       NOTRUN -> [SKIP][341] ([i915#14259])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_plane_multiple@tiling-yf.html
    - shard-dg1:          NOTRUN -> [SKIP][342] ([i915#14259])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg1:          NOTRUN -> [SKIP][343] ([i915#6953])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][344] ([i915#15329]) +8 other tests skip
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-dg1:          NOTRUN -> [SKIP][345] ([i915#15329] / [i915#3555])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
    - shard-tglu:         NOTRUN -> [SKIP][346] ([i915#15329] / [i915#3555])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-9/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-dg1:          NOTRUN -> [SKIP][347] ([i915#15329]) +8 other tests skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][348] ([i915#12343])
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-3/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade:
    - shard-tglu:         NOTRUN -> [SKIP][349] ([i915#12343] / [i915#9812])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-2/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][350] ([i915#12343] / [i915#9812])
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_pm_backlight@fade-with-suspend.html
    - shard-dg1:          NOTRUN -> [SKIP][351] ([i915#12343] / [i915#5354])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-tglu-1:       NOTRUN -> [SKIP][352] ([i915#9685])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg2:          NOTRUN -> [SKIP][353] ([i915#15948])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-6/igt@kms_pm_dc@dc5-psr.html
    - shard-rkl:          NOTRUN -> [SKIP][354] ([i915#15948])
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-psr-suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][355] ([i915#16914])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_pm_dc@dc5-psr-suspend-resume.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          NOTRUN -> [SKIP][356] ([i915#3828])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-tglu-1:       NOTRUN -> [SKIP][357] ([i915#3828])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg1:          [PASS][358] -> [SKIP][359] ([i915#15073])
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-17/igt@kms_pm_rpm@dpms-non-lpsp.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@fences:
    - shard-dg1:          NOTRUN -> [SKIP][360] ([i915#4077]) +12 other tests skip
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-17/igt@kms_pm_rpm@fences.html

  * igt@kms_pm_rpm@fences-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][361] ([i915#4077]) +4 other tests skip
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@kms_pm_rpm@fences-dpms.html

  * igt@kms_pm_rpm@i2c:
    - shard-glk:          [PASS][362] -> [FAIL][363] ([i915#8717])
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-glk2/igt@kms_pm_rpm@i2c.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk2/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          NOTRUN -> [SKIP][364] ([i915#15073])
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu:         NOTRUN -> [SKIP][365] ([i915#15073])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
    - shard-mtlp:         NOTRUN -> [SKIP][366] ([i915#15073])
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-tglu:         NOTRUN -> [SKIP][367] ([i915#6524])
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@basic-crc-vgem:
    - shard-dg2:          NOTRUN -> [SKIP][368] ([i915#6524] / [i915#6805])
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-8/igt@kms_prime@basic-crc-vgem.html
    - shard-dg1:          NOTRUN -> [SKIP][369] ([i915#6524])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_prime@basic-crc-vgem.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][370] ([i915#6524]) +1 other test skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-mtlp:         NOTRUN -> [SKIP][371] ([i915#12316])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-glk10:        NOTRUN -> [SKIP][372] ([i915#11520]) +2 other tests skip
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk10/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][373] ([i915#11520]) +10 other tests skip
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk9/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-dg2:          NOTRUN -> [SKIP][374] ([i915#11520]) +2 other tests skip
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][375] ([i915#11520]) +7 other tests skip
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-glk11:        NOTRUN -> [SKIP][376] ([i915#11520]) +1 other test skip
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk11/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-snb:          NOTRUN -> [SKIP][377] ([i915#11520]) +10 other tests skip
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-snb4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][378] ([i915#11520]) +5 other tests skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][379] ([i915#11520]) +11 other tests skip
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu-1:       NOTRUN -> [SKIP][380] ([i915#11520]) +6 other tests skip
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          NOTRUN -> [SKIP][381] ([i915#9683]) +1 other test skip
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_psr2_su@page_flip-nv12.html
    - shard-tglu:         NOTRUN -> [SKIP][382] ([i915#9683])
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-9/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-tglu-1:       NOTRUN -> [SKIP][383] ([i915#9683])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-dg1:          NOTRUN -> [SKIP][384] ([i915#9683])
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-dg1:          NOTRUN -> [SKIP][385] ([i915#1072] / [i915#9732]) +26 other tests skip
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@fbc-psr-cursor-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][386] ([i915#9732]) +20 other tests skip
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-9/igt@kms_psr@fbc-psr-cursor-plane-onoff.html
    - shard-mtlp:         NOTRUN -> [SKIP][387] ([i915#9688]) +6 other tests skip
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-1/igt@kms_psr@fbc-psr-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-dg2:          NOTRUN -> [SKIP][388] ([i915#1072] / [i915#9732]) +8 other tests skip
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-7/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][389] ([i915#9732]) +13 other tests skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][390] ([i915#1072] / [i915#9732]) +22 other tests skip
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_psr@psr2-primary-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][391] ([i915#4077] / [i915#9688]) +1 other test skip
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-6/igt@kms_psr@psr2-primary-mmap-gtt@edp-1.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          NOTRUN -> [SKIP][392] ([i915#15949]) +1 other test skip
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
    - shard-tglu-1:       NOTRUN -> [SKIP][393] ([i915#15949])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          NOTRUN -> [INCOMPLETE][394] ([i915#15492] / [i915#16184])
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk3/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][395] ([i915#12755] / [i915#15867] / [i915#5190])
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg1:          NOTRUN -> [SKIP][396] ([i915#5289]) +1 other test skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
    - shard-tglu:         NOTRUN -> [SKIP][397] ([i915#5289]) +1 other test skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-snb:          NOTRUN -> [ABORT][398] ([i915#13179]) +1 other test abort
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-snb1/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-glk:          NOTRUN -> [FAIL][399] ([i915#10959])
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu:         NOTRUN -> [SKIP][400] ([i915#8623])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@ts-continuation-dpms-rpm:
    - shard-dg1:          [PASS][401] -> [SKIP][402] ([i915#4423])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-12/igt@kms_vblank@ts-continuation-dpms-rpm.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_vblank@ts-continuation-dpms-rpm.html

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][403] ([i915#4423])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-4.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-dg1:          NOTRUN -> [SKIP][404] ([i915#9906])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-14/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          NOTRUN -> [SKIP][405] ([i915#3555] / [i915#9906])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_vrr@negative-basic.html
    - shard-dg1:          NOTRUN -> [SKIP][406] ([i915#3555] / [i915#9906])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-12/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][407] ([i915#9906])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-tglu-1:       NOTRUN -> [SKIP][408] ([i915#9906])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-dg1:          NOTRUN -> [SKIP][409] ([i915#2433])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@perf@per-context-mode-unprivileged.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][410] ([i915#2433])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@perf@unprivileged-single-ctx-counters.html

  * igt@perf_pmu@busy-double-start@rcs0:
    - shard-mtlp:         [PASS][411] -> [FAIL][412] ([i915#4349]) +1 other test fail
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-3/igt@perf_pmu@busy-double-start@rcs0.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@perf_pmu@busy-double-start@rcs0.html

  * igt@perf_pmu@module-unload:
    - shard-tglu-1:       NOTRUN -> [FAIL][413] ([i915#17127])
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@perf_pmu@module-unload.html
    - shard-snb:          NOTRUN -> [FAIL][414] ([i915#17127])
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-snb1/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][415] ([i915#13356] / [i915#16236])
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk6/igt@perf_pmu@rc6-suspend.html

  * igt@prime_udl@share-import-addfb:
    - shard-tglu-1:       NOTRUN -> [SKIP][416] ([i915#16420])
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-1/igt@prime_udl@share-import-addfb.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          NOTRUN -> [SKIP][417] ([i915#3291] / [i915#3708])
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg1:          NOTRUN -> [SKIP][418] ([i915#3708])
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          NOTRUN -> [SKIP][419] ([i915#3708])
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@prime_vgem@fence-write-hang.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-mtlp:         [ABORT][420] -> [PASS][421]
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-2/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-mtlp:         [FAIL][422] ([i915#17176]) -> [PASS][423]
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_big@single:
    - shard-tglu:         [FAIL][424] ([i915#15816]) -> [PASS][425]
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-tglu-7/igt@gem_exec_big@single.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-5/igt@gem_exec_big@single.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-rkl:          [INCOMPLETE][426] ([i915#13356]) -> [PASS][427] +1 other test pass
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@gem_exec_suspend@basic-s3.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-rkl:          [SKIP][428] ([i915#4270]) -> [PASS][429]
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-2/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          [INCOMPLETE][430] ([i915#13809] / [i915#16226]) -> [PASS][431]
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@gem_softpin@noreloc-s3.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@gem_softpin@noreloc-s3.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg2:          [DMESG-WARN][432] ([i915#13029] / [i915#14545]) -> [PASS][433]
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg2-1/igt@i915_module_load@reload-no-display.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-5/igt@i915_module_load@reload-no-display.html

  * igt@i915_suspend@debugfs-reader:
    - shard-glk:          [INCOMPLETE][434] ([i915#13356] / [i915#16182] / [i915#4817]) -> [PASS][435]
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-glk4/igt@i915_suspend@debugfs-reader.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk2/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-rkl:          [INCOMPLETE][436] ([i915#4817]) -> [PASS][437]
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@i915_suspend@fence-restore-tiled2untiled.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-glk:          [FAIL][438] ([i915#14888]) -> [PASS][439] +1 other test pass
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk2/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [FAIL][440] ([i915#15733] / [i915#5138]) -> [PASS][441]
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-rkl:          [FAIL][442] ([i915#13566]) -> [PASS][443] +2 other tests pass
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-128x42.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][444] ([i915#13566]) -> [PASS][445] +3 other tests pass
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-tglu-8/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_force_connector_basic@force-edid:
    - shard-mtlp:         [SKIP][446] ([i915#15672]) -> [PASS][447]
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-1/igt@kms_force_connector_basic@force-edid.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff:
    - shard-rkl:          [SKIP][448] ([i915#15989]) -> [PASS][449] +12 other tests pass
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
    - shard-glk:          [SKIP][450] -> [PASS][451] +9 other tests pass
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-glk2/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-glk8/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-mtlp:         [INCOMPLETE][452] -> [PASS][453] +1 other test pass
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-8/igt@kms_hdr@bpc-switch-suspend.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1-xrgb2101010:
    - shard-mtlp:         [FAIL][454] ([i915#17172]) -> [PASS][455]
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-8/igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1-xrgb2101010.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-7/igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1-xrgb2101010.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-mtlp:         [INCOMPLETE][456] ([i915#17032]) -> [PASS][457]
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-7/igt@kms_pm_backlight@fade-with-suspend.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][458] ([i915#15073]) -> [PASS][459] +5 other tests pass
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@kms_pm_rpm@dpms-lpsp.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
    - shard-dg1:          [SKIP][460] ([i915#15073]) -> [PASS][461]
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-12/igt@kms_pm_rpm@dpms-lpsp.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg2:          [SKIP][462] ([i915#15073]) -> [PASS][463] +1 other test pass
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg2-4/igt@kms_pm_rpm@dpms-non-lpsp.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg2-7/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@perf_pmu@busy-double-start@vcs1:
    - shard-dg1:          [FAIL][464] ([i915#4349]) -> [PASS][465] +2 other tests pass
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-16/igt@perf_pmu@busy-double-start@vcs1.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-19/igt@perf_pmu@busy-double-start@vcs1.html
    - shard-mtlp:         [FAIL][466] ([i915#4349]) -> [PASS][467]
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-3/igt@perf_pmu@busy-double-start@vcs1.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-2/igt@perf_pmu@busy-double-start@vcs1.html

  
#### Warnings ####

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          [SKIP][468] ([i915#3555] / [i915#9323]) -> [SKIP][469] ([i915#14544] / [i915#3555] / [i915#9323])
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-8/igt@gem_ccs@block-copy-compressed.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          [SKIP][470] ([i915#14544] / [i915#9323]) -> [SKIP][471] ([i915#9323])
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@gem_ccs@suspend-resume.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-mtlp:         [ABORT][472] -> [ABORT][473] ([i915#17175])
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-mtlp-2/igt@gem_ctx_isolation@preservation-s3.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-mtlp-5/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_exec_reloc@basic-gtt-wc-active:
    - shard-rkl:          [SKIP][474] ([i915#3281]) -> [SKIP][475] ([i915#14544] / [i915#3281]) +1 other test skip
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@gem_exec_reloc@basic-gtt-wc-active.html
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc-active.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          [SKIP][476] ([i915#14544] / [i915#4613]) -> [SKIP][477] ([i915#4613])
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          [SKIP][478] ([i915#4613]) -> [SKIP][479] ([i915#14544] / [i915#4613])
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-verify.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_pwrite@basic-self:
    - shard-rkl:          [SKIP][480] ([i915#14544] / [i915#3282]) -> [SKIP][481] ([i915#3282])
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@gem_pwrite@basic-self.html
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@gem_pwrite@basic-self.html

  * igt@gem_readwrite@new-obj:
    - shard-rkl:          [SKIP][482] ([i915#3282]) -> [SKIP][483] ([i915#14544] / [i915#3282])
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@gem_readwrite@new-obj.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gem_readwrite@new-obj.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-rkl:          [SKIP][484] ([i915#14544] / [i915#3297]) -> [SKIP][485] ([i915#3297])
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@gem_userptr_blits@readonly-unsync.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          [SKIP][486] ([i915#3297]) -> [SKIP][487] ([i915#14544] / [i915#3297]) +1 other test skip
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@gem_userptr_blits@unsync-overlap.html
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen9_exec_parse@bb-large:
    - shard-rkl:          [SKIP][488] ([i915#14544] / [i915#2527]) -> [SKIP][489] ([i915#2527])
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@gen9_exec_parse@bb-large.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          [SKIP][490] ([i915#2527]) -> [SKIP][491] ([i915#14544] / [i915#2527]) +1 other test skip
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gen9_exec_parse@bb-oversize.html

  * igt@gpu_buddy@gpu_buddy:
    - shard-rkl:          [SKIP][492] ([i915#15678]) -> [SKIP][493] ([i915#14544] / [i915#15678])
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-2/igt@gpu_buddy@gpu_buddy.html
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@gpu_buddy@gpu_buddy.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          [SKIP][494] ([i915#7707]) -> [SKIP][495] ([i915#14544] / [i915#7707])
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@intel_hwmon@hwmon-write.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-rkl:          [SKIP][496] ([i915#5286]) -> [SKIP][497] ([i915#14544] / [i915#5286])
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          [SKIP][498] ([i915#14544] / [i915#5286]) -> [SKIP][499] ([i915#5286])
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-rkl:          [SKIP][500] ([i915#14544] / [i915#3638]) -> [SKIP][501] ([i915#3638])
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
    - shard-rkl:          [SKIP][502] ([i915#14098] / [i915#6095]) -> [SKIP][503] ([i915#14098] / [i915#14544] / [i915#6095]) +3 other tests skip
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][504] ([i915#6095]) -> [SKIP][505] ([i915#14544] / [i915#6095]) +3 other tests skip
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-b-hdmi-a-2.html
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][506] ([i915#12313] / [i915#14544]) -> [SKIP][507] ([i915#12313])
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-4:
    - shard-dg1:          [SKIP][508] ([i915#6095]) -> [SKIP][509] ([i915#4423] / [i915#6095]) +1 other test skip
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-17/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-4.html
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][510] ([i915#14544] / [i915#6095]) -> [SKIP][511] ([i915#6095])
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][512] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][513] ([i915#14098] / [i915#6095]) +2 other tests skip
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d:
    - shard-rkl:          [SKIP][514] ([i915#16471]) -> [SKIP][515] ([i915#14544] / [i915#16471])
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-2/igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d.html
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-rkl:          [SKIP][516] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][517] ([i915#11151] / [i915#7828])
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-fast.html
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-1/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-rkl:          [SKIP][518] ([i915#11151] / [i915#7828]) -> [SKIP][519] ([i915#11151] / [i915#14544] / [i915#7828]) +1 other test skip
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@kms_chamelium_hpd@dp-hpd.html
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          [SKIP][520] ([i915#14544] / [i915#15865]) -> [SKIP][521] ([i915#15865])
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_content_protection@atomic.html
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][522] ([i915#15865]) -> [SKIP][523] ([i915#14544] / [i915#15865])
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@kms_content_protection@mei-interface.html
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-rkl:          [SKIP][524] ([i915#4103]) -> [SKIP][525] ([i915#14544] / [i915#4103])
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-rkl:          [SKIP][526] ([i915#14544] / [i915#9934]) -> [SKIP][527] ([i915#9934])
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_flip@2x-blocking-wf_vblank.html
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-rkl:          [SKIP][528] ([i915#9934]) -> [SKIP][529] ([i915#14544] / [i915#9934]) +1 other test skip
   [528]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-3/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [529]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-rkl:          [SKIP][530] ([i915#14544] / [i915#15643]) -> [SKIP][531] ([i915#15643])
   [530]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
   [531]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][532] ([i915#1825]) -> [SKIP][533] ([i915#14544] / [i915#1825])
   [532]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html
   [533]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-suspend:
    - shard-rkl:          [INCOMPLETE][534] ([i915#16056]) -> [SKIP][535] ([i915#15989])
   [534]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-suspend.html
   [535]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-8/igt@kms_frontbuffer_tracking@fbchdr-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][536] ([i915#15102]) -> [SKIP][537] ([i915#14544] / [i915#15102]) +9 other tests skip
   [536]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [537]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][538] ([i915#14544] / [i915#1825]) -> [SKIP][539] ([i915#1825]) +2 other tests skip
   [538]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [539]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
    - shard-dg1:          [SKIP][540] -> [SKIP][541] ([i915#4423]) +1 other test skip
   [540]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
   [541]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-wc:
    - shard-dg1:          [SKIP][542] ([i915#15990]) -> [SKIP][543] ([i915#15990] / [i915#4423])
   [542]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-wc.html
   [543]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-dg1:          [SKIP][544] ([i915#15989]) -> [SKIP][545] ([i915#15989] / [i915#4423]) +1 other test skip
   [544]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-12/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [545]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-16/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@hdr-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][546] ([i915#14544]) -> [SKIP][547] +17 other tests skip
   [546]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
   [547]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-4/igt@kms_frontbuffer_tracking@hdr-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][548] -> [SKIP][549] ([i915#14544]) +17 other tests skip
   [548]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-4/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-shrfb-pgflip-blt.html
   [549]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-rkl:          [SKIP][550] ([i915#14544] / [i915#15102]) -> [SKIP][551] ([i915#15102]) +8 other tests skip
   [550]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-suspend.html
   [551]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-rkl:          [SKIP][552] ([i915#14544] / [i915#15458]) -> [SKIP][553] ([i915#15458])
   [552]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_joiner@invalid-modeset-ultra-joiner.html
   [553]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][554] ([i915#14544] / [i915#15815]) -> [SKIP][555] ([i915#15815])
   [554]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [555]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping:
    - shard-rkl:          [SKIP][556] ([i915#15709]) -> [SKIP][557] ([i915#14544] / [i915#15709]) +1 other test skip
   [556]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-8/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html
   [557]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-rkl:          [ABORT][558] ([i915#15132]) -> [INCOMPLETE][559] ([i915#14412])
   [558]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [559]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          [SKIP][560] ([i915#12343]) -> [SKIP][561] ([i915#12343] / [i915#14544])
   [560]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@kms_pm_backlight@brightness-with-dpms.html
   [561]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-rkl:          [SKIP][562] ([i915#12343] / [i915#5354]) -> [SKIP][563] ([i915#12343] / [i915#14544] / [i915#5354])
   [562]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-2/igt@kms_pm_backlight@fade-with-suspend.html
   [563]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][564] ([i915#11520] / [i915#14544]) -> [SKIP][565] ([i915#11520]) +1 other test skip
   [564]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
   [565]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
    - shard-rkl:          [SKIP][566] ([i915#11520]) -> [SKIP][567] ([i915#11520] / [i915#14544]) +1 other test skip
   [566]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-8/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
   [567]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@pr-primary-blt:
    - shard-rkl:          [SKIP][568] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][569] ([i915#1072] / [i915#9732]) +2 other tests skip
   [568]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-6/igt@kms_psr@pr-primary-blt.html
   [569]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-3/igt@kms_psr@pr-primary-blt.html

  * igt@kms_psr@psr-suspend:
    - shard-rkl:          [SKIP][570] ([i915#1072] / [i915#9732]) -> [SKIP][571] ([i915#1072] / [i915#14544] / [i915#9732]) +7 other tests skip
   [570]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-7/igt@kms_psr@psr-suspend.html
   [571]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_psr@psr-suspend.html

  * igt@kms_psr@psr2-primary-mmap-cpu:
    - shard-dg1:          [SKIP][572] ([i915#1072] / [i915#9732]) -> [SKIP][573] ([i915#1072] / [i915#4423] / [i915#9732])
   [572]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-dg1-19/igt@kms_psr@psr2-primary-mmap-cpu.html
   [573]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-dg1-18/igt@kms_psr@psr2-primary-mmap-cpu.html

  * igt@kms_vrr@flip-basic:
    - shard-rkl:          [SKIP][574] ([i915#15243] / [i915#3555]) -> [SKIP][575] ([i915#14544] / [i915#15243] / [i915#3555])
   [574]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-8/igt@kms_vrr@flip-basic.html
   [575]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@kms_vrr@flip-basic.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          [SKIP][576] ([i915#2436]) -> [SKIP][577] ([i915#14544] / [i915#2436])
   [576]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19205/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [577]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
  [i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12756]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12756
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14123]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14123
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14412
  [i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14600]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14600
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14888]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14888
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15172]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15172
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15342
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15479]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15479
  [i915#15481]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15481
  [i915#15492]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15492
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15672
  [i915#15678]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15678
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15815
  [i915#15816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15816
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15948]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15948
  [i915#15949]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15949
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16056
  [i915#16079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16079
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16184]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16184
  [i915#16226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16226
  [i915#16236]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16236
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#16386]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16386
  [i915#16396]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16396
  [i915#16420]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16420
  [i915#16451]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16451
  [i915#16464]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16464
  [i915#16466]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16466
  [i915#16471]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16471
  [i915#16599]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16599
  [i915#16600]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16600
  [i915#16680]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16680
  [i915#16867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16867
  [i915#16870]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16870
  [i915#16914]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16914
  [i915#16990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16990
  [i915#17032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17032
  [i915#17076]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17076
  [i915#17116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17116
  [i915#17126]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17126
  [i915#17127]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17127
  [i915#17158]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17158
  [i915#17172]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17172
  [i915#17175]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17175
  [i915#17176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17176
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
  [i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8717
  [i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_9109 -> IGTPW_15885
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_19205: 7cdd31de20cd320f9a1539bb5c3949275326f017 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_15885: 562a7eb5931347113b319d03004edf87b6843196 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_9109: 65f84b280be2caf8ce376295d97987a808affdee @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15885/index.html

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✗ Xe.CI.FULL: failure for Add BO Allocation and VM Bind stress infra (rev4)

[Patchwork]

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== Series Details ==

Series: Add BO Allocation and VM Bind stress infra (rev4)
URL   : https://patchwork.freedesktop.org/series/172310/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_9109_FULL -> XEIGTPW_15885_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_15885_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_15885_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_15885_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-d-edp-1:
    - shard-ptl:          [PASS][1] -> [ABORT][2] +3 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-1/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-edp-1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-edp-1.html

  * igt@xe_bo_alloc@array-binds-rand-sizes-10 (NEW):
    - shard-ptl:          NOTRUN -> [SKIP][3] +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@xe_bo_alloc@array-binds-rand-sizes-10.html
    - shard-lnl:          NOTRUN -> [SKIP][4] +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-3/igt@xe_bo_alloc@array-binds-rand-sizes-10.html

  
New tests
---------

  New tests have been introduced between XEIGT_9109_FULL and XEIGTPW_15885_FULL:

### New IGT tests (24) ###

  * igt@xe_bo_alloc@all-sizes-once:
    - Statuses : 3 pass(s)
    - Exec time: [29.69, 34.95] s

  * igt@xe_bo_alloc@all-sizes-once@gt0:
    - Statuses : 3 pass(s)
    - Exec time: [14.94, 17.95] s

  * igt@xe_bo_alloc@all-sizes-once@gt1:
    - Statuses : 3 pass(s)
    - Exec time: [14.67, 16.97] s

  * igt@xe_bo_alloc@array-binds-rand-sizes-10:
    - Statuses : 1 pass(s) 2 skip(s)
    - Exec time: [0.02, 11.43] s

  * igt@xe_bo_alloc@array-binds-rand-sizes-10-unaligned:
    - Statuses : 1 pass(s) 2 skip(s)
    - Exec time: [0.01, 11.06] s

  * igt@xe_bo_alloc@array-binds-rand-sizes-10-unaligned@gt0:
    - Statuses : 1 pass(s)
    - Exec time: [5.38] s

  * igt@xe_bo_alloc@array-binds-rand-sizes-10-unaligned@gt1:
    - Statuses : 1 pass(s)
    - Exec time: [5.56] s

  * igt@xe_bo_alloc@array-binds-rand-sizes-10@gt0:
    - Statuses : 1 pass(s)
    - Exec time: [5.50] s

  * igt@xe_bo_alloc@array-binds-rand-sizes-10@gt1:
    - Statuses : 1 pass(s)
    - Exec time: [5.54] s

  * igt@xe_bo_alloc@rand-sizes-10:
    - Statuses : 3 pass(s)
    - Exec time: [1.01, 1.62] s

  * igt@xe_bo_alloc@rand-sizes-100:
    - Statuses : 2 pass(s)
    - Exec time: [10.94, 12.07] s

  * igt@xe_bo_alloc@rand-sizes-100-unaligned:
    - Statuses : 1 pass(s)
    - Exec time: [11.18] s

  * igt@xe_bo_alloc@rand-sizes-100-unaligned@gt0:
    - Statuses : 1 pass(s)
    - Exec time: [5.68] s

  * igt@xe_bo_alloc@rand-sizes-100-unaligned@gt1:
    - Statuses : 1 pass(s)
    - Exec time: [5.47] s

  * igt@xe_bo_alloc@rand-sizes-100@gt0:
    - Statuses : 2 pass(s)
    - Exec time: [5.51, 6.27] s

  * igt@xe_bo_alloc@rand-sizes-100@gt1:
    - Statuses : 2 pass(s)
    - Exec time: [5.40, 5.78] s

  * igt@xe_bo_alloc@rand-sizes-10@gt0:
    - Statuses : 3 pass(s)
    - Exec time: [0.54, 0.82] s

  * igt@xe_bo_alloc@rand-sizes-10@gt1:
    - Statuses : 3 pass(s)
    - Exec time: [0.46, 0.78] s

  * igt@xe_bo_alloc@test_vm_oversubscribe_concurrent_bind:
    - Statuses : 1 pass(s) 2 skip(s)
    - Exec time: [0.34, 1.55] s

  * igt@xe_bo_alloc@threads-leak-binding-rand-sizes-50:
    - Statuses : 3 pass(s)
    - Exec time: [5.75, 6.27] s

  * igt@xe_bo_alloc@threads-leak-binding-rand-sizes-50-unaligned:
    - Statuses : 1 pass(s)
    - Exec time: [5.80] s

  * igt@xe_bo_alloc@threads-rand-sizes-50:
    - Statuses : 3 pass(s)
    - Exec time: [5.77, 6.04] s

  * igt@xe_bo_alloc@threads-rand-sizes-50-unaligned:
    - Statuses : 3 pass(s)
    - Exec time: [5.59, 6.72] s

  * igt@xe_exec_balancer:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_15885_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-ptl:          NOTRUN -> [SKIP][5] ([Intel XE#7225])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-1/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-ptl:          NOTRUN -> [SKIP][6] ([Intel XE#5765])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-ptl:          NOTRUN -> [SKIP][7] ([Intel XE#5947])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2327]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][9] ([Intel XE#6925])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-ptl:          NOTRUN -> [SKIP][10] ([Intel XE#5901])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-ptl:          NOTRUN -> [SKIP][11] ([Intel XE#7085])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#607] / [Intel XE#7361])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
    - shard-ptl:          NOTRUN -> [SKIP][13] ([Intel XE#5851])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#610] / [Intel XE#7387])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-ptl:          NOTRUN -> [SKIP][15] ([Intel XE#5808]) +13 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-ptl:          NOTRUN -> [SKIP][16] ([Intel XE#5850])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#1124]) +8 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p:
    - shard-ptl:          NOTRUN -> [SKIP][18] ([Intel XE#7679]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#367]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-ptl:          NOTRUN -> [SKIP][20] ([Intel XE#367]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2887]) +10 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][22] ([Intel XE#5823] / [Intel XE#6918]) +14 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][23] ([Intel XE#5822]) +10 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2652]) +17 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#3432]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-ptl:          NOTRUN -> [SKIP][26] ([Intel XE#9205]) +4 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2724] / [Intel XE#7449])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2325] / [Intel XE#7358])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-ptl:          NOTRUN -> [SKIP][29] ([Intel XE#5824]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7358]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-6/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709:
    - shard-ptl:          NOTRUN -> [SKIP][31] ([Intel XE#8391]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2252]) +4 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-ptl:          NOTRUN -> [SKIP][33] ([Intel XE#2252]) +6 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_color_pipeline@plane-ctm3x4@pipe-a-plane-3:
    - shard-ptl:          NOTRUN -> [SKIP][34] ([Intel XE#6969]) +15 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_color_pipeline@plane-ctm3x4@pipe-a-plane-3.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lut1d@pipe-d-plane-1:
    - shard-bmg:          NOTRUN -> [FAIL][35] ([Intel XE#9333]) +25 other tests fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lut1d@pipe-d-plane-1.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601@pipe-a-plane-1:
    - shard-ptl:          NOTRUN -> [FAIL][36] ([Intel XE#9333]) +12 other tests fail
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601@pipe-a-plane-1.html

  * igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-b-plane-4:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#6969]) +15 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-b-plane-4.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2390] / [Intel XE#6974])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-6/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#6974])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
    - shard-ptl:          NOTRUN -> [SKIP][40] ([Intel XE#6974])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-ptl:          NOTRUN -> [SKIP][41] ([Intel XE#5832] / [Intel XE#6974])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@suspend-resume:
    - shard-bmg:          NOTRUN -> [FAIL][42] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +3 other tests fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_content_protection@suspend-resume.html
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#7642]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_content_protection@suspend-resume.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][44] ([Intel XE#6707] / [Intel XE#7439]) +1 other test fail
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2320]) +5 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_cursor_crc@cursor-random-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-ptl:          NOTRUN -> [SKIP][47] ([Intel XE#5900]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-ptl:          NOTRUN -> [SKIP][48] ([Intel XE#5962]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-ptl:          NOTRUN -> [SKIP][49] ([Intel XE#5962] / [Intel XE#7343])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-1/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2286] / [Intel XE#6035])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#4210] / [Intel XE#7467])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#4354] / [Intel XE#7386])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_dp_link_training@uhbr-mst.html
    - shard-ptl:          NOTRUN -> [SKIP][53] ([Intel XE#7386])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback:
    - shard-ptl:          NOTRUN -> [SKIP][54] ([Intel XE#9009])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html

  * igt@kms_dsc@dsc-basic-ultrajoiner:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#8265]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_dsc@dsc-basic-ultrajoiner.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-ptl:          NOTRUN -> [SKIP][56] ([Intel XE#5907]) +5 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_feature_discovery@dsc:
    - shard-ptl:          NOTRUN -> [SKIP][57] ([Intel XE#9287])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_feature_discovery@dsc.html

  * igt@kms_feature_discovery@vrr:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#8586]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_feature_discovery@vrr.html

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-ptl:          NOTRUN -> [SKIP][59] ([Intel XE#2316]) +3 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][60] -> [FAIL][61] ([Intel XE#301]) +1 other test fail
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][62] -> [FAIL][63] ([Intel XE#301] / [Intel XE#3149])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-ptl:          NOTRUN -> [SKIP][64] ([Intel XE#7178]) +5 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7178] / [Intel XE#7351]) +5 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#7179])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][67] ([Intel XE#5800] / [Intel XE#6312]) +5 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-1/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-pri-indfb-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][68] ([Intel XE#6312]) +14 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#7061]) +6 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#4141]) +16 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][71] ([Intel XE#7061] / [Intel XE#7356]) +6 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#2311]) +50 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move:
    - shard-ptl:          NOTRUN -> [SKIP][73] ([Intel XE#7865]) +25 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][74] ([Intel XE#7061]) +3 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#7061] / [Intel XE#7356]) +6 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2313]) +51 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][77] ([Intel XE#5812]) +68 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-suspend:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][78] ([Intel XE#9259])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-6/igt@kms_frontbuffer_tracking@hdr-suspend.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank160:
    - shard-bmg:          [PASS][79] -> [FAIL][80] ([Intel XE#9313])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-2/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html

  * igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery:
    - shard-bmg:          NOTRUN -> [FAIL][81] ([Intel XE#9319] / [Intel XE#9346])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#7308])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-6/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-ptl:          NOTRUN -> [SKIP][83] ([Intel XE#5917] / [Intel XE#6174])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#6911] / [Intel XE#7466])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_joiner@basic-force-ultra-joiner.html
    - shard-ptl:          NOTRUN -> [SKIP][85] ([Intel XE#6900])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#7591])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
    - shard-ptl:          NOTRUN -> [SKIP][87] ([Intel XE#7591])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@legacy:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#2486])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5:
    - shard-ptl:          NOTRUN -> [SKIP][89] ([Intel XE#8303]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier:
    - shard-ptl:          NOTRUN -> [SKIP][90] ([Intel XE#7283]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#7283]) +4 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-ptl:          NOTRUN -> [SKIP][92] ([Intel XE#4596] / [Intel XE#5854])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#5020] / [Intel XE#7348])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_plane_multiple@tiling-y.html
    - shard-ptl:          NOTRUN -> [SKIP][94] ([Intel XE#5020])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b:
    - shard-ptl:          NOTRUN -> [SKIP][95] ([Intel XE#6886]) +14 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c.html

  * igt@kms_pm_backlight@fade:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-2/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2505] / [Intel XE#7447])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@kms_pm_dc@deep-pkgc.html
    - shard-ptl:          NOTRUN -> [FAIL][99] ([Intel XE#7395])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@package-g7:
    - shard-ptl:          NOTRUN -> [SKIP][101] ([Intel XE#6813])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@kms_pm_rpm@package-g7.html
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#6814] / [Intel XE#7428])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#1489]) +7 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][104] ([Intel XE#5858] / [Intel XE#7304]) +3 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][105] ([Intel XE#5858]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-ptl:          NOTRUN -> [SKIP][106] ([Intel XE#7304]) +4 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-ptl:          NOTRUN -> [SKIP][107] ([Intel XE#7413])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-ptl:          NOTRUN -> [SKIP][108] ([Intel XE#1406]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-dpms:
    - shard-ptl:          NOTRUN -> [SKIP][109] ([Intel XE#1406] / [Intel XE#5835]) +3 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@kms_psr@fbc-psr2-dpms.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#2234])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@kms_psr@psr2-primary-render.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][111] ([Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][112] ([Intel XE#7795])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-ptl:          NOTRUN -> [SKIP][113] ([Intel XE#5821])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-ptl:          NOTRUN -> [SKIP][114] ([Intel XE#5813])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#2413])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#1435] / [Intel XE#8695])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-ptl:          NOTRUN -> [SKIP][118] ([Intel XE#5910])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#6503]) +2 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-ptl:          NOTRUN -> [SKIP][120] ([Intel XE#5857])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-dp-2:
    - shard-bmg:          [PASS][121] -> [ABORT][122] ([Intel XE#9093]) +1 other test abort
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-2/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-dp-2.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-dp-2.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-ptl:          [PASS][123] -> [FAIL][124] ([Intel XE#4227] / [Intel XE#7397])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-3/igt@kms_vrr@flip-basic-fastset.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1:
    - shard-ptl:          [PASS][125] -> [FAIL][126] ([Intel XE#6293] / [Intel XE#7397])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-3/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html

  * igt@kms_vrr@flipline@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [FAIL][127] ([Intel XE#4227] / [Intel XE#7397]) +1 other test fail
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@kms_vrr@flipline@pipe-a-edp-1.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-bmg:          NOTRUN -> [SKIP][128] ([Intel XE#1499] / [Intel XE#9271])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-2/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@sriov_basic@pf-unbind-with-vf-probed:
    - shard-bmg:          NOTRUN -> [ABORT][129] ([Intel XE#8868])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@sriov_basic@pf-unbind-with-vf-probed.html

  * igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-system:
    - shard-ptl:          [PASS][130] -> [ABORT][131] ([Intel XE#9362]) +3 other tests abort
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-2/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-system.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-1/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-system.html

  * igt@xe_ccs@suspend-resume@xmajor-compressed-compfmt0-vram01-vram01:
    - shard-bmg:          [PASS][132] -> [ABORT][133] ([Intel XE#9362])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-4/igt@xe_ccs@suspend-resume@xmajor-compressed-compfmt0-vram01-vram01.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@xe_ccs@suspend-resume@xmajor-compressed-compfmt0-vram01-vram01.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][134] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-ptl:          NOTRUN -> [SKIP][135] ([Intel XE#5764]) +9 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-small-external-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][136] ([Intel XE#8370]) +2 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@xe_evict@evict-small-external-multi-queue.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
    - shard-ptl:          NOTRUN -> [SKIP][137] ([Intel XE#6144])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html

  * igt@xe_exec_balancer@many-parallel-userptr-invalidate:
    - shard-ptl:          NOTRUN -> [SKIP][138] ([Intel XE#7482]) +19 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-1/igt@xe_exec_balancer@many-parallel-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][139] ([Intel XE#2322] / [Intel XE#7372]) +7 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-ptl:          NOTRUN -> [SKIP][140] ([Intel XE#5575] / [Intel XE#7484]) +6 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][141] ([Intel XE#8374]) +11 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][142] ([Intel XE#8374]) +5 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_multi_queue@exec-sanity:
    - shard-ptl:          NOTRUN -> [SKIP][143] ([Intel XE#8364]) +27 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-1/igt@xe_exec_multi_queue@exec-sanity.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#8364]) +23 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_reset@cm-multi-queue-gt-reset:
    - shard-ptl:          NOTRUN -> [SKIP][145] ([Intel XE#8369]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@xe_exec_reset@cm-multi-queue-gt-reset.html

  * igt@xe_exec_reset@multi-queue-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][146] ([Intel XE#8369])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@xe_exec_reset@multi-queue-close-fd.html

  * igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][147] ([Intel XE#9331]) +53 other tests dmesg-warn
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html

  * igt@xe_exec_system_allocator@prefetch-sys-benchmark:
    - shard-bmg:          [PASS][148] -> [DMESG-WARN][149] ([Intel XE#9309] / [Intel XE#9331])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-9/igt@xe_exec_system_allocator@prefetch-sys-benchmark.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-10/igt@xe_exec_system_allocator@prefetch-sys-benchmark.html

  * igt@xe_exec_system_allocator@process-many-large-mmap-nomemset:
    - shard-bmg:          [PASS][150] -> [DMESG-WARN][151] ([Intel XE#9331]) +206 other tests dmesg-warn
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-8/igt@xe_exec_system_allocator@process-many-large-mmap-nomemset.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_exec_system_allocator@process-many-large-mmap-nomemset.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [FAIL][152] ([Intel XE#9096])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-bmg:          [PASS][153] -> [FAIL][154] ([Intel XE#9096])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-7/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-6/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][155] ([Intel XE#8378]) +10 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr:
    - shard-ptl:          NOTRUN -> [SKIP][156] ([Intel XE#8378]) +9 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          NOTRUN -> [SKIP][157] ([Intel XE#6281] / [Intel XE#7426])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-10/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-ptl:          NOTRUN -> [SKIP][158] ([Intel XE#5712])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][159] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-2/igt@xe_media_fill@media-fill.html
    - shard-ptl:          NOTRUN -> [SKIP][160] ([Intel XE#5830] / [Intel XE#7453])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-7/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@pci-membarrier:
    - shard-ptl:          NOTRUN -> [SKIP][161] ([Intel XE#5100] / [Intel XE#7408])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@xe_mmap@pci-membarrier.html

  * igt@xe_mmap@vram:
    - shard-ptl:          NOTRUN -> [SKIP][162] ([Intel XE#5776])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_mmap@vram.html

  * igt@xe_multigpu_svm@mgpu-coherency-conflict:
    - shard-ptl:          NOTRUN -> [SKIP][163] ([Intel XE#6964])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_multigpu_svm@mgpu-coherency-conflict.html

  * igt@xe_multigpu_svm@mgpu-latency-copy-basic:
    - shard-bmg:          NOTRUN -> [SKIP][164] ([Intel XE#6964]) +2 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_multigpu_svm@mgpu-latency-copy-basic.html

  * igt@xe_noexec_ping_pong@basic:
    - shard-ptl:          NOTRUN -> [SKIP][165] ([Intel XE#6259] / [Intel XE#7406])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_noexec_ping_pong@basic.html

  * igt@xe_page_reclaim@many-vma-same-bo:
    - shard-ptl:          NOTRUN -> [SKIP][166] ([Intel XE#7793]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@xe_page_reclaim@many-vma-same-bo.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          NOTRUN -> [SKIP][167] ([Intel XE#1420] / [Intel XE#7590])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-ptl:          NOTRUN -> [SKIP][168] ([Intel XE#5780] / [Intel XE#7590])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-bmg:          NOTRUN -> [SKIP][169] ([Intel XE#7590]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-4/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_pat@xa-app-transient-media-on:
    - shard-ptl:          NOTRUN -> [SKIP][170] ([Intel XE#7590])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@xe_pat@xa-app-transient-media-on.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          NOTRUN -> [SKIP][171] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-ptl:          NOTRUN -> [SKIP][172] ([Intel XE#5741])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pm@s3-vm-bind-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][173] ([Intel XE#6867])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@xe_pm@s3-vm-bind-prefetch.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-ptl:          NOTRUN -> [ABORT][174] ([Intel XE#9362])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@xe_pm@s4-vm-bind-userptr.html
    - shard-lnl:          [PASS][175] -> [ABORT][176] ([Intel XE#9362]) +3 other tests abort
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-lnl-5/igt@xe_pm@s4-vm-bind-userptr.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-5/igt@xe_pm@s4-vm-bind-userptr.html

  * igt@xe_prefetch_fault@prefetch-fault:
    - shard-ptl:          NOTRUN -> [SKIP][177] ([Intel XE#7599])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-2/igt@xe_prefetch_fault@prefetch-fault.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][178] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-10/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][179] ([Intel XE#944])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-5/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-ptl:          NOTRUN -> [SKIP][180] ([Intel XE#6019]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer:
    - shard-ptl:          NOTRUN -> [SKIP][181] ([Intel XE#7892])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-4/igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer.html

  
#### Possible fixes ####

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-ptl:          [FAIL][182] -> [PASS][183]
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][184] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][185] +1 other test pass
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
    - shard-ptl:          [ABORT][186] ([Intel XE#9362]) -> [PASS][187] +8 other tests pass
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-8/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-5/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][188] ([Intel XE#301]) -> [PASS][189] +1 other test pass
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-ptl:          [SKIP][190] ([Intel XE#7308]) -> [PASS][191]
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-ptl-4/igt@kms_hdmi_inject@inject-audio.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-ptl-8/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [FAIL][192] ([Intel XE#8399]) -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-lnl-8/igt@kms_pm_dc@dc5-psr.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-bmg:          [ABORT][194] ([Intel XE#9362]) -> [PASS][195] +1 other test pass
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-1/igt@kms_vblank@ts-continuation-suspend.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-9/igt@kms_vblank@ts-continuation-suspend.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][196] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-3/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_system_allocator@process-many-stride-malloc-prefetch-madvise:
    - shard-bmg:          [DMESG-WARN][198] ([Intel XE#9309]) -> [PASS][199] +1 other test pass
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-10/igt@xe_exec_system_allocator@process-many-stride-malloc-prefetch-madvise.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-10/igt@xe_exec_system_allocator@process-many-stride-malloc-prefetch-madvise.html

  * igt@xe_exec_system_allocator@threads-many-stride-free-nomemset:
    - shard-bmg:          [DMESG-WARN][200] ([Intel XE#9331]) -> [PASS][201] +195 other tests pass
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-1/igt@xe_exec_system_allocator@threads-many-stride-free-nomemset.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_exec_system_allocator@threads-many-stride-free-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-stride-malloc-prefetch-madvise:
    - shard-bmg:          [DMESG-WARN][202] ([Intel XE#9309] / [Intel XE#9331]) -> [PASS][203] +1 other test pass
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-stride-malloc-prefetch-madvise.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-8/igt@xe_exec_system_allocator@threads-many-stride-malloc-prefetch-madvise.html

  * igt@xe_module_load@reload-no-display:
    - shard-bmg:          [ABORT][204] ([Intel XE#8007]) -> [PASS][205] +2 other tests pass
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-9/igt@xe_module_load@reload-no-display.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@xe_module_load@reload-no-display.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-bmg:          [INCOMPLETE][206] ([Intel XE#8175]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-6/igt@xe_pm@s3-vm-bind-userptr.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-7/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_sriov_vram@vf-access-after-resize-down:
    - shard-bmg:          [FAIL][208] ([Intel XE#7992]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-4/igt@xe_sriov_vram@vf-access-after-resize-down.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-1/igt@xe_sriov_vram@vf-access-after-resize-down.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][210] ([Intel XE#301]) -> [FAIL][211] ([Intel XE#301] / [Intel XE#3149])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][212] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][213] ([Intel XE#2509] / [Intel XE#7437])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9109/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5712]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5712
  [Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5765]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5765
  [Intel XE#5776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5776
  [Intel XE#5780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5780
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
  [Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
  [Intel XE#5830]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5830
  [Intel XE#5832]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5832
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5850
  [Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
  [Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
  [Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
  [Intel XE#5947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5947
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
  [Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
  [Intel XE#6259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6259
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6293
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6813
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6867]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6867
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
  [Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7225]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7225
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
  [Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
  [Intel XE#7406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7406
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7426
  [Intel XE#7428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7428
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7447
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7467
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7795]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7795
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8175]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8175
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8586
  [Intel XE#8695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8695
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
  [Intel XE#9009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9009
  [Intel XE#9093]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9093
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9205]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9205
  [Intel XE#9259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9259
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9287]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9287
  [Intel XE#9309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9309
  [Intel XE#9313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9313
  [Intel XE#9319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9319
  [Intel XE#9331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9331
  [Intel XE#9333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9333
  [Intel XE#9346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9346
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_9109 -> IGTPW_15885
  * Linux: xe-5807-3413ca5893855693d3cc12697713842547261439 -> xe-5810-7cdd31de20cd320f9a1539bb5c3949275326f017

  IGTPW_15885: 562a7eb5931347113b319d03004edf87b6843196 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_9109: 65f84b280be2caf8ce376295d97987a808affdee @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5807-3413ca5893855693d3cc12697713842547261439: 3413ca5893855693d3cc12697713842547261439
  xe-5810-7cdd31de20cd320f9a1539bb5c3949275326f017: 7cdd31de20cd320f9a1539bb5c3949275326f017

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15885/index.html

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Re: [PATCH i-g-t v5 5/5] tests/intel: Add oversubscribe concurrent bind stress subtest

[Sharma, Nishit]

On 9/22/2026 4:34 PM, Sobin Thomas wrote:
> Add test for oversubscribing VRAM in multi process environment that
> creates VM, bind large BOs and submit workloads nearly simultaneously.
>
> Previous coverage lacked a scenario combining multi-process bind
> with VRAM oversubscription. This generates memory pressure with
> multi-process VM Bind activity and concurrent submission, exercising
> the bind pipeline under eviction pressure.
>
> v3: Fixed minor nits
> v4: Refactoring of the create_bo ( Nishit)
>      Fix child process exit deadlock in release_ready_processes() (Nishit)
>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>   tests/intel/xe_bo_alloc.c | 533 +++++++++++++++++++++++++++++++++++++-
>   1 file changed, 532 insertions(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
> index d8368087b..2ee468c62 100644
> --- a/tests/intel/xe_bo_alloc.c
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -29,6 +29,17 @@
>   #define THREAD_VA_STRIDE GB(1)
>   #define SZ_4K_SHIFT	12
>   #define MAX_ALLOCATIONS 50000
> +#define INT_ADD_CNT 4
> +#define TIMEOUT_NS (30ULL * 1000000000ULL)
> +#define MAX_SRAM_TEST_SIZE GB(32)
> +#define GPR_RX_ADDR(x)          (0x600 + (x) * 8)
> +#define MAX_PROCS 20
> +
> +#define EXEC_DATA_ADDR		0x100000ULL
> +#define EXEC_RESULT_ADDR	0x200000ULL
> +#define EXEC_BATCH_ADDR		0x300000ULL
> +#define EXEC_UFENCE_ADDR	0x400000ULL
> +#define STRESS_BIND_ADDR	0x40000000ULL
>   
>   /**
>    * SUBTEST: all-sizes-once
> @@ -76,14 +87,48 @@
>    * Description: Test 50 random BO allocation sizes in test table with a thread per engine,
>    * leak the binding, unaligned bind addresses
>    * Test category: stress test
> + *
> + * SUBTEST: test_vm_oversubscribe_concurrent_bind
> + * Description: Test enough random BO allocation sizes, bound as arrays of binds, to trigger
> + * evictions with 2 processes per engine, leak the BO munmap / gem close, unaligned bind addresses
> + * Test category: stress test
>    */
>   
>   #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
>   #define MIN_BUFS_PER_PROC 2
>   
>   #define N_ALLOC_SIZES	256
> +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
> +
>   static uint64_t *alloc_sizes;
>   
> +struct gem_bo {
> +	uint32_t handle;
> +	uint64_t size;
> +	uint32_t *ptr;
> +	uint64_t addr;
> +};
> +
> +struct xe_oversubscribe_ctx {
> +	uint32_t vm_id;
> +	uint32_t exec_queue_id;
> +};
> +
> +struct mem_bind_sync {
> +	struct gem_bo *bufs;
> +	int n_bufs;
> +	uint64_t *binds_ufence;
> +};
> +
> +struct process_data {
> +	pthread_mutex_t mutex;
> +	pthread_cond_t cond;
> +	int ready;
> +	int failed;
> +	pthread_barrier_t barrier;
> +	bool go;
> +};
> +
>   /*
>    * Data-driven subtest matrix.
>    *
> @@ -103,7 +148,8 @@ enum test_type {
>   	TYPE_ALL_SIZES,
>   	TYPE_RANDOM_SIZE,
>   	TYPE_ARRAY_BIND,
> -	TYPE_THREAD
> +	TYPE_THREAD,
> +	TYPE_OVERSUBSCRIBE,
>   };
>   
>   struct test_case {
> @@ -114,6 +160,14 @@ struct test_case {
>   	bool requires_evict_ram;
>   };
>   
> +struct oversubscribe_params {
> +	int n_proc;
> +	int n_vram_bufs;
> +	int n_sram_bufs;
> +	uint64_t vram_size;
> +	uint64_t sram_size;
> +	uint64_t total_vram_demand;
> +};
>   #define LEAK_BINDING		(0x1 << 0)
>   #define LEAK_BO			(0x1 << 1)
>   #define EVICT			(0x1 << 2)
> @@ -244,6 +298,478 @@ static int __xe_vm_bind_array(int fd, uint32_t vm,
>   	return 0;
>   }
>   
> +static void init_pdata(struct process_data *pdata)
> +{
> +	pthread_mutexattr_t mattr;
> +	pthread_condattr_t cattr;
> +
> +	pthread_mutexattr_init(&mattr);
> +	igt_assert_eq(pthread_mutexattr_setpshared(&mattr, PTHREAD_PROCESS_SHARED), 0);
> +	igt_assert_eq(pthread_mutexattr_setrobust(&mattr, PTHREAD_MUTEX_ROBUST), 0);
> +	igt_assert_eq(pthread_mutex_init(&pdata->mutex, &mattr), 0);
> +	pthread_mutexattr_destroy(&mattr);
> +
> +	pthread_condattr_init(&cattr);
> +	igt_assert_eq(pthread_condattr_setpshared(&cattr, PTHREAD_PROCESS_SHARED), 0);
> +	igt_assert_eq(pthread_cond_init(&pdata->cond, &cattr), 0);
> +	pthread_condattr_destroy(&cattr);
> +	pdata->ready = 0;
> +	pdata->failed = 0;
> +	pdata->go = false;
> +}
> +
> +static void process_ready_and_wait(struct process_data *pdata)
> +{
> +	int ret = pthread_mutex_lock(&pdata->mutex);
> +
> +	if (ret == EOWNERDEAD)
> +		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
> +	else
> +		igt_assert_eq(ret, 0);
> +	pdata->ready++;
> +	pthread_cond_broadcast(&pdata->cond);
> +	while (!pdata->go)
> +		pthread_cond_wait(&pdata->cond, &pdata->mutex);
> +	pthread_mutex_unlock(&pdata->mutex);
> +}
> +
> +static void process_setup_failed(struct process_data *pdata)
> +{
> +	int ret = pthread_mutex_lock(&pdata->mutex);
> +
> +	if (ret == EOWNERDEAD)
> +		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
> +	else
> +		igt_assert_eq(ret, 0);
> +	pdata->failed++;
> +	pthread_cond_broadcast(&pdata->cond);
> +	pthread_mutex_unlock(&pdata->mutex);
> +}
> +
> +static void release_ready_processes(struct process_data *pdata, int n_proc)
> +{
> +	struct timespec timeout;
> +	int ret;
> +
> +	ret = pthread_mutex_lock(&pdata->mutex);
> +	if (ret == EOWNERDEAD)
> +		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
release_ready_processes() asserts on EOWNERDEAD which cancels out the 
robust-mutex fix, If a child dies holding the mutex (exactly the case 
robust mutexes exist for),

the parent aborts instead of recovering, it should be

while (pdata->ready + pdata->failed < n_proc) {
         ret = pthread_cond_timedwait(&pdata->cond, &pdata->mutex, 
&timeout);
         if (ret == EOWNERDEAD) {
igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
             continue;

else ......

> +	else
> +		igt_assert_eq(ret, 0);
> +
> +	clock_gettime(CLOCK_REALTIME, &timeout);
> +	timeout.tv_sec += 30;
> +	/*
> +	 * Wait until all children have either reached VM Bind rendevouz
> +	 * Or, failed setup and exited the test path.
> +	 */
> +	while (pdata->ready + pdata->failed < n_proc) {
> +		ret = pthread_cond_timedwait(&pdata->cond, &pdata->mutex, &timeout);
> +		if (ret == EOWNERDEAD) {
> +			igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
> +		} else if (ret == ETIMEDOUT) {

After ETIMEDOUT, the parent sets pdata->go = true unconditionally, 
Children still stuck in setup (that never reached the rendezvous) get 
released

and proceed into bind_bos() / exec with a partially initialized state. 
On timeout you should mark the run as failed rather than letting 
stragglers run:

pdata->failed = n_proc;   /* stop stragglers proceeding */

> +			igt_warn("Timeout waiting for the child process: ready=%d, failed =%d, expected=%d",
> +			pdata->ready, pdata->failed, n_proc);
> +			break;
> +		}
> +		igt_assert_eq(ret, 0);
> +	}
> +
> +	igt_debug("Process rendezvous: ready=%d failed=%d total = %d\n",
> +		  pdata->ready, pdata->failed, n_proc);
> +
> +	/* Release every successful child into VM_Bind at same time*/
> +	pdata->go = true;
> +	pthread_cond_broadcast(&pdata->cond);
> +	pthread_mutex_unlock(&pdata->mutex);
> +}
> +
> +static int build_add_batch(struct gem_bo *batch_bo, struct gem_bo *integers_bo,
> +			   struct gem_bo *result_bo, int ints_to_add)
> +{
> +	int pos = 0;
> +	int i;
> +	uint64_t tmp_addr;
> +
> +	batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | MI_LRI_LRM_CS_MMIO | 2;
> +	batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
> +	tmp_addr = integers_bo->addr + 0 * sizeof(uint32_t);
> +	batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
> +	batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
> +	for (i = 1; i < ints_to_add; i++) {
> +		/* r1 = integers_bo[i] */
> +		batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | MI_LRI_LRM_CS_MMIO | 2;
> +		batch_bo->ptr[pos++] = GPR_RX_ADDR(1);
> +		tmp_addr = integers_bo->addr + i * sizeof(uint32_t);
> +		batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
> +		batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
> +		/* r0 = r0 + r1 */
> +		batch_bo->ptr[pos++] = MI_MATH(4);
> +		batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(0));
> +		batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(1));
> +		batch_bo->ptr[pos++] = MI_MATH_ADD;
> +		batch_bo->ptr[pos++] = MI_MATH_STORE(MI_MATH_REG(0), MI_MATH_REG_ACCU);
> +	}
> +	/* result_bo[0] = r0 */
> +	batch_bo->ptr[pos++] = MI_STORE_REGISTER_MEM_GEN8 | MI_LRI_LRM_CS_MMIO;
> +	batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
> +	tmp_addr = result_bo->addr + 0 * sizeof(uint32_t);
> +	batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
> +	batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
> +
> +	batch_bo->ptr[pos++] = MI_BATCH_BUFFER_END;
> +	while (pos % 4 != 0)
> +		batch_bo->ptr[pos++] = MI_NOOP;
> +	return pos;
> +}
> +
> +static void create_exec_queue(int fd, struct xe_oversubscribe_ctx *ctx)
> +{
> +	ctx->exec_queue_id = xe_exec_queue_create(fd, ctx->vm_id,
> +						  &xe_engine(fd, 0)->instance, 0);
> +}
> +
> +static uint64_t *
> +vm_bind_bo_batch(int fd, struct xe_oversubscribe_ctx *ctx, struct gem_bo *bos, int size,
> +		 int *out_err)
> +{
> +	uint64_t *ufence;
> +	struct drm_xe_sync bind_sync;
> +	struct drm_xe_vm_bind_op *binds;
> +	int i;
> +
> +	binds = calloc(size, sizeof(*binds));
> +	igt_assert(binds);
> +
> +	ufence = calloc(1, sizeof(*ufence));
> +	igt_assert(ufence);
> +	bind_sync = (struct drm_xe_sync) {
> +		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.addr = to_user_pointer(ufence),
> +		.timeline_value = 1,
> +	};
> +
> +	for (i = 0; i < size; i++) {
> +		binds[i] = (struct drm_xe_vm_bind_op) {
> +			.obj = bos[i].handle,
> +			.obj_offset = 0,
> +			.range = bos[i].size,
> +			.addr = bos[i].addr,
> +			.op = DRM_XE_VM_BIND_OP_MAP,
> +			.flags = 0,
> +		};
> +	}
> +	*out_err = __xe_vm_bind_array(fd, ctx->vm_id, binds, size, &bind_sync, 1);
> +	free(binds);
> +	return ufence;
> +}
> +
> +/* Returns 1 (caller should skip exec) on an allowed OOM error, 0 otherwise. */
> +static int bind_bos(int fd, struct xe_oversubscribe_ctx *ctx, struct gem_bo *bufs,
> +		    struct mem_bind_sync *bind, int *bind_err, bool allow_oom)
> +{
> +	if (!bind->n_bufs)
> +		return 0;
> +
> +	bind->binds_ufence = vm_bind_bo_batch(fd, ctx, bufs, bind->n_bufs, bind_err);
> +
> +	if (*bind_err) {
> +		if (allow_oom) {
> +			igt_assert_f(*bind_err == -ENOMEM || *bind_err == -ENOSPC,
> +				     "Unexpected bind error: %d (%s)\n",
> +				     *bind_err, strerror(-*bind_err));
> +			igt_debug("Bind failed with expected OOM (%s), skipping exec\n",
> +				  strerror(-*bind_err));
> +			return 1;
> +		}
> +
> +		igt_assert_f(false, "Unexpected bind error: %d", *bind_err);
> +	}
> +
> +	xe_wait_ufence(fd, bind->binds_ufence, 1, 0, TIMEOUT_NS);
> +	return 0;
> +}
> +
> +static int fill_random_integers(struct gem_bo *int_bo, int ints_to_add)
> +{
> +	uint32_t expected_result = 0;
> +	char expr[256];
> +	int len = 0;
> +
> +	for (int i = 0; i < ints_to_add; i++) {
> +		uint32_t random_int = rand() % 8;
> +
> +		int_bo->ptr[i] = random_int;
> +		expected_result += random_int;
> +
> +		len += snprintf(expr + len, sizeof(expr) - len, "%s%u",
> +				i ? " + " : "", random_int);
> +	}
> +	igt_debug("%s = %u\n", expr, expected_result);
> +	return expected_result;
> +}
> +
> +static void cleanup_bo_resources(int fd, struct gem_bo *bo)
> +{
> +	if (bo->ptr) {
> +		igt_assert_eq(munmap(bo->ptr, bo->size), 0);
> +		bo->ptr = NULL;
> +	}
> +	if (bo->handle)
> +		gem_close(fd, bo->handle);
> +}
> +
> +static int create_test_bos(int fd, struct xe_oversubscribe_ctx *ctx,
> +			   struct mem_bind_sync *bind, uint32_t placement,
> +			   uint64_t *addr)
> +{
> +	const char *mem_type = (placement & vram_memory(fd, 0)) ? "VRAM" : "SRAM";
> +	int ret;
> +
> +	for (int i = 0; i < bind->n_bufs; i++) {
> +		struct gem_bo *bo = &bind->bufs[i];
> +
> +		bo->size = GB(1);
> +		ret = __xe_bo_create_caching(fd, ctx->vm_id, bo->size, placement, 0,
> +					     DRM_XE_GEM_CPU_CACHING_WC, &bo->handle);
> +		if (ret) {
> +			int saved_errno = errno; /* capture before anything can clobber it */
> +
> +			bind->n_bufs = i;
> +			if (saved_errno == ENOMEM || saved_errno == ENOSPC) {
> +				/* Continue on OOM, expected when oversubscribing the VM */
> +				igt_debug("%s allocation failed at buffer %d (OOM)\n", mem_type, i);
> +				break;
> +			}
> +			/* We are returning as this is a fail scenario */
> +			igt_warn("%s allocation failed at buffer %d: %s\n",
> +				 mem_type, i, strerror(saved_errno));
> +			return -saved_errno;
> +		}
> +		bo->ptr = NULL;
> +		bo->addr = *addr;
> +		*addr += bo->size;
> +		igt_debug("%s buffer %d created at 0x%016lx\n", mem_type, i, bo->addr);
> +	}
> +	return 0;
> +}
> +
> +static void cleanup_sram_vram_objs(int fd, struct mem_bind_sync *vram_bind,
> +				   struct mem_bind_sync *sram_bind)
> +{
> +	for (int i = 0; i < vram_bind->n_bufs; i++)
> +		gem_close(fd, vram_bind->bufs[i].handle);
> +	for (int i = 0; i < sram_bind->n_bufs; i++)
> +		gem_close(fd, sram_bind->bufs[i].handle);
> +	free(vram_bind->bufs);
> +	free(sram_bind->bufs);
> +	if (vram_bind->binds_ufence)
> +		free(vram_bind->binds_ufence);
> +	if (sram_bind->binds_ufence)
> +		free(sram_bind->binds_ufence);
> +}
> +
> +static void create_bo(int fd, uint32_t vm, struct gem_bo *bo, uint64_t size,
> +		      uint64_t addr, bool map_now)
> +{
> +	bo->size = ALIGN(size, 4096);
> +	bo->handle = xe_bo_create_caching(fd, vm, bo->size, system_memory(fd), 0,
> +					  DRM_XE_GEM_CPU_CACHING_WC);
> +	igt_assert(bo->handle);
> +	bo->addr = addr;
> +	if (map_now) {
> +		bo->ptr = xe_bo_map(fd, bo->handle, bo->size);
> +		igt_assert(bo->ptr != MAP_FAILED);
> +	} else {
> +		bo->ptr = NULL;
> +	}
> +}
> +
> +static bool calc_oversubscribe_params(int fd, struct oversubscribe_params *p)
> +{
> +	uint64_t target_vram, target_sram;
> +	uint64_t total_vram_bufs, total_sram_bufs, max_by_mem;
> +
> +	p->vram_size =  xe_visible_available_vram_size(fd, 0);
> +	p->sram_size = (uint64_t)igt_get_avail_ram_mb() << 20;
> +	/*
> +	 * Dynamically cap VRAM oversubscription so the overflow into system
> +	 * RAM stays within 25% of available RAM. On small-VRAM platforms
> +	 * the 2x target fits within the cap and behavior is
> +	 * unchanged; on large-VRAM platforms (e.g. PVC) this prevents OOM.
> +	 */
> +
> +	target_vram = min(p->vram_size * 2, p->vram_size + p->sram_size / 4);
> +	target_sram = min_t(uint64_t, p->sram_size * 50 / 100,
> +			    MAX_SRAM_TEST_SIZE);
> +	total_vram_bufs = target_vram / GB(1);
> +	total_sram_bufs = target_sram / GB(1);
> +	max_by_mem = min(total_vram_bufs / MIN_BUFS_PER_PROC,
> +			 total_sram_bufs / MIN_BUFS_PER_PROC);
> +
> +	p->n_proc = min_t(int, max_by_mem, MAX_PROCS);
> +	if (p->n_proc <= 0)
> +		return false;
> +	p->n_vram_bufs = max_t(int, 2, total_vram_bufs / p->n_proc);
> +	p->n_sram_bufs = max_t(int, 2, total_sram_bufs / p->n_proc);
> +	p->total_vram_demand = (uint64_t)p->n_proc * p->n_vram_bufs * GB(1);
> +	return true;
> +}
> +
> +static void test_vm_oversubscribe_concurrent_bind(int fd)
> +{
> +	struct oversubscribe_params p;
> +	struct process_data *pdata;
> +
> +	igt_require_f(calc_oversubscribe_params(fd, &p),
> +		      "Not enough VRAM/RAM for oversubscription test\n");
> +
> +	igt_debug("VRAM size: %" PRIu64 "MB, System RAM available: %" PRIu64 "MB\n",
> +		  p.vram_size >> 20, p.sram_size >> 20);
> +
> +	igt_debug("n_proc = %d\n", p.n_proc);
> +	igt_debug("VRAM: %" PRIu64 "GB\n", p.vram_size >> 30);
> +	igt_debug("VRAM demand: %" PRIu64 "MB (%.2fx oversubscription)\n",
> +		  p.total_vram_demand >> 20, (double)p.total_vram_demand / p.vram_size);
> +	igt_debug("Processes=%d VRAM_bufs=%d SRAM_bufs=%d\n", p.n_proc,
> +		  p.n_vram_bufs, p.n_sram_bufs);
> +
> +	pdata = mmap(NULL, sizeof(*pdata), PROT_READ | PROT_WRITE,
> +		     MAP_SHARED | MAP_ANONYMOUS, -1, 0);
> +	igt_assert(pdata != MAP_FAILED);
> +	init_pdata(pdata);
> +
> +	igt_fork(child, p.n_proc) {
> +		struct xe_oversubscribe_ctx ctx = {0};
> +		int rc, ret, fd_c;
> +		uint64_t addr = STRESS_BIND_ADDR;
> +		uint32_t expected_result = 0;
> +		struct gem_bo integers_bo = {0}, result_bo = {0}, batch_bo = {0};
> +		struct gem_bo *vram_bufs, *sram_bufs;
> +		int pos = 0;
> +		struct mem_bind_sync vram_bind = {0};
> +		struct mem_bind_sync sram_bind = {0};
> +		struct drm_xe_sync batch_syncs[1];
> +		struct drm_xe_exec exec;
> +		struct gem_bo ufence_bo = {0};
> +		int vram_bind_err = 0, sram_bind_err = 0;
> +
> +		vram_bufs = calloc(p.n_vram_bufs, sizeof(*vram_bufs));
> +		sram_bufs = calloc(p.n_sram_bufs, sizeof(*sram_bufs));
> +		srand(child);
> +
> +		fd_c = drm_open_driver(DRIVER_XE);
> +
> +		igt_assert(vram_bufs && sram_bufs);
> +
> +		ctx.vm_id = xe_vm_create(fd_c, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0);

The VM is created with only DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, but you 
then use xe_vm_bind_lr_sync()

and a DRM_XE_SYNC_TYPE_USER_FENCE out-sync on DRM_IOCTL_XE_EXEC.

LR/user-fence submission paths typically require 
DRM_XE_VM_CREATE_FLAG_LR_MODE.

Confirm the exec queue/VM are actually long-running; otherwise the exec 
user-fence may never

signal and xe_wait_ufence will hit TIMEOUT_NS. This is the most likely 
source of an intermittent hang under pressure.
> +		create_exec_queue(fd_c, &ctx);
> +		vram_bind.bufs = vram_bufs;
> +		vram_bind.n_bufs = p.n_vram_bufs;
> +		sram_bind.bufs = sram_bufs;
> +		sram_bind.n_bufs = p.n_sram_bufs;
> +
> +		ret = create_test_bos(fd_c, &ctx, &vram_bind, vram_memory(fd_c, 0), &addr);
> +		if (ret) {
> +			process_setup_failed(pdata);
> +			goto cleanup;
> +		}
> +
> +		ret = create_test_bos(fd_c, &ctx, &sram_bind, system_memory(fd_c), &addr);
> +		if (ret) {
> +			process_setup_failed(pdata);
> +			goto cleanup;
> +		}
> +
> +		if (!vram_bind.n_bufs || !sram_bind.n_bufs) {
> +			igt_debug("No BOs allocated; VRAM/SRAM unavailable, skipping\n");
> +			process_setup_failed(pdata);
> +			goto cleanup;
> +		}
> +
> +		/*
> +		 * All allocations are complete. Report Ready and wait until every
> +		 * child has either reached this point or repported a setup failure.
> +		 */
> +
> +		 process_ready_and_wait(pdata);
> +
> +		/*
> +		 * VM_Bind starts only after the parent releases all ready
> +		 * childen.
> +		 */
> +
> +		if (bind_bos(fd_c, &ctx, vram_bufs, &vram_bind, &vram_bind_err, true))
> +			goto cleanup;
> +
> +		if (bind_bos(fd_c, &ctx, sram_bufs, &sram_bind, &sram_bind_err, false))
> +			goto cleanup;
> +
> +		create_bo(fd_c, ctx.vm_id, &integers_bo, 4096, EXEC_DATA_ADDR, true);
> +		expected_result = fill_random_integers(&integers_bo, INT_ADD_CNT);
> +		igt_debug("%d\n", expected_result);
> +		create_bo(fd_c, ctx.vm_id, &result_bo, 4096, EXEC_RESULT_ADDR, false);
> +		create_bo(fd_c, ctx.vm_id, &batch_bo, 4096, EXEC_BATCH_ADDR, true);
> +		pos = build_add_batch(&batch_bo, &integers_bo, &result_bo, INT_ADD_CNT);
> +
> +		igt_assert(pos * sizeof(int) <= batch_bo.size);
> +
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, integers_bo.handle, 0, integers_bo.addr,
> +				   integers_bo.size, 0);
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, result_bo.handle, 0, result_bo.addr,
> +				   result_bo.size, 0);
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, batch_bo.handle, 0, batch_bo.addr,
> +				   batch_bo.size, 0);
> +		create_bo(fd_c, ctx.vm_id, &ufence_bo, 4096, EXEC_UFENCE_ADDR, true);
> +
> +		memset(ufence_bo.ptr, 0, ufence_bo.size);
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, ufence_bo.handle, 0, ufence_bo.addr,
> +				   ufence_bo.size, 0);
> +
> +		batch_syncs[0] = (struct drm_xe_sync){
> +			.type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +			.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +			.addr = ufence_bo.addr,
> +			.timeline_value = USER_FENCE_VALUE,
> +		};
> +
> +		exec = (struct drm_xe_exec) {
> +			.exec_queue_id = ctx.exec_queue_id,
> +			.num_syncs = 1,
> +			.syncs = (uintptr_t)batch_syncs,
> +			.address = batch_bo.addr,
> +			.num_batch_buffer = 1,
> +		};
> +
> +		rc = igt_ioctl(fd_c, DRM_IOCTL_XE_EXEC, &exec);
> +		igt_assert_f(rc == 0, "xe_exec failed unexpectedly: %s (%d)\n",
> +			     strerror(errno), errno);
> +		xe_wait_ufence(fd_c, (uint64_t *)ufence_bo.ptr, USER_FENCE_VALUE, ctx.exec_queue_id,
> +			       TIMEOUT_NS);
> +		result_bo.ptr = xe_bo_map(fd_c, result_bo.handle, result_bo.size);
> +		igt_assert(result_bo.ptr != MAP_FAILED);
> +		igt_assert_eq(result_bo.ptr[0], expected_result);
> +cleanup:
> +		cleanup_bo_resources(fd_c, &ufence_bo);
> +		cleanup_bo_resources(fd_c, &result_bo);
> +		cleanup_bo_resources(fd_c, &batch_bo);
> +		cleanup_bo_resources(fd_c, &integers_bo);
> +		cleanup_sram_vram_objs(fd_c, &vram_bind, &sram_bind);
> +		xe_exec_queue_destroy(fd_c, ctx.exec_queue_id);
> +		xe_vm_destroy(fd_c, ctx.vm_id);
> +		drm_close_driver(fd_c);
> +	}
> +
> +	release_ready_processes(pdata, p.n_proc);
> +	igt_waitchildren();
> +	igt_reset_timeout();
> +
> +	pthread_cond_destroy(&pdata->cond);
> +	pthread_mutex_destroy(&pdata->mutex);
> +	igt_assert_eq(munmap(pdata, sizeof(*pdata)), 0);
> +}
> +
>   static void alloc_sizes_init(void)
>   {
>   	int i;
> @@ -986,6 +1512,7 @@ static const struct test_case test_matrix[] = {
>   	{ "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING, TYPE_THREAD, false },
>   	{ "threads-leak-binding-rand-sizes-50-unaligned", 50, LEAK_BINDING | UNALIGNED,
>   	  TYPE_THREAD, false },
> +	{ "test_vm_oversubscribe_concurrent_bind", 0, 0, TYPE_OVERSUBSCRIBE, false},
>   };
>   
>   int igt_main()
> @@ -1011,6 +1538,10 @@ int igt_main()
>   				run_threaded_bo_alloc_test(fd, t->count, t->flags);
>   			}
>   			break;
> +		case TYPE_OVERSUBSCRIBE:
> +			igt_subtest_f("%s", t->name)
> +				test_vm_oversubscribe_concurrent_bind(fd);
> +			break;
>   		case TYPE_ALL_SIZES:
>   		case TYPE_RANDOM_SIZE:
>   		case TYPE_ARRAY_BIND:

RE: [PATCH i-g-t v5 1/5] tests/intel: add BO allocation stress coverage

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Thomas, Sobin <sobin.thomas@intel.com>
> Sent: 22 September 2026 16:35
> To: igt-dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
> Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t v5 1/5] tests/intel: add BO allocation stress coverage
> 
> Add a new xe_bo_alloc test excercising BO allocation, VM bind, mapping and
> execution across a range of BO sizes.
> The test runs once per GT rather than once per engine, making sure that on multi-
> tile platforms every GT/VRAM region is excercised. This stress test exercises
> concurrent buffer allocation all the sizes at once.
> 
> This provide coverage for different BO allocation stress scenarios
> 
> v3: renamed the sub test functions.
> v4: Addressed nits (kamil)
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>  tests/intel/xe_bo_alloc.c | 598 ++++++++++++++++++++++++++++++++++++++
>  tests/meson.build         |   1 +
>  2 files changed, 599 insertions(+)
>  create mode 100644 tests/intel/xe_bo_alloc.c
> 
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c new file mode
> 100644 index 000000000..8680fe518
> --- /dev/null
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -0,0 +1,598 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +/**
> + * TEST: xe_bo_alloc
> + * Category: Core
> + * Mega feature: General
> + * Sub-category: Memory
> + * Functionality: BO allocation
> + * Description: Tests for buffer object allocation in Xe driver  */
> +
> +#include <errno.h>
> +#include <fcntl.h>
> +#include <sys/mman.h>
> +
> +#include "igt.h"
> +
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#include "xe_drm.h"
> +#define BO_BIND_BASE_ADDR	0x1a0000ull
> +#define THREAD_VA_STRIDE GB(1)
> +#define SZ_4K_SHIFT	12
> +#define MAX_ALLOCATIONS 50000
> +
> +/**
> + * SUBTEST: all-sizes-once
> + * Description: Test all BO allocations sizes in test table
> + * Test category: functionality test
> + */
> +
> +#define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) #define
> +MIN_BUFS_PER_PROC 2
> +
> +#define N_ALLOC_SIZES	256
> +static uint64_t *alloc_sizes;
> +
> +/*
> + * Data-driven subtest matrix.
> + *
> + * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly
> +one
> + * engine per invocation, so they're wired up as a dynamic child
> +subtest
> + * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
> + *
> + * TYPE_THREAD are deliberately NOT split per engine here:
> + * threads() already do their own xe_for_each_engine() to spawn one
> + * thread per engine internally. Wrapping those in a second, outer
> + * per-engine loop would run the full all-engine fan-out
> + * once for every engine on the machine, multiplying the runtime by the
> + * engine count and re-exercising every engine N times over. So these
> + * stay flat, single subtests.
> + */
> +enum test_type {
> +	TYPE_ALL_SIZES,
> +};
> +
> +struct test_case {
> +	const char *name;
> +	int count; /* -1 means "until vram_per_process is hit" */
> +	uint32_t flags;
> +	enum test_type type;
> +	bool requires_evict_ram;
> +};
> +
> +#define LEAK_BINDING		(0x1 << 0)
> +#define LEAK_BO			(0x1 << 1)
> +#define EVICT			(0x1 << 2)
> +#define UNALIGNED		(0x1 << 3)
> +#define ARRAY_BIND    (0x1 << 4)

> +
> +/*
> + * Represents a single BO under test: its reserved VA range, the BO
> +handle,
> + * the CPU mapping obtained after binding, and its size. The prepare /
> +bind
> + * / execute steps below all operate on arrays of this struct so that
> +the
> + * same code path drives both a single BO (the original subtests) and
> +an
> + * "array of binds" of several BOs at once (the new array-binds subtests).
> + */
> +struct bo_alloc {
> +	void *va_reserve;	/* raw mmap() reservation, kept only so it can
> +				 * be released again; never touched directly.
> +				 */
> +	size_t va_reserve_size;
> +	void *va;		/* fixed CPU mapping address used by mmap */
> +	uint64_t gpu_va;	/* GPU virtual address used by VM_BIND */
> +	void *map;		/* CPU mapping of the BO, valid after bind */
> +	uint64_t bo_size;
> +	uint32_t bo;
> +};
> +
> +struct bo_group {
> +	struct bo_alloc *bos;
> +	int n_bos;
> +};
> +
> +struct batch_data {
> +	uint32_t batch[16];
> +	uint64_t pad;
> +	uint32_t data;
> +};
> +
Overall code in this commit looks fine, small NITS are there.
struct bo_group, MAX_ALLOCATIONS, MIN_BUFS_PER_PROC, THREAD_VA_STRIDE are not being this commit can be introduced wherever used.
> +/*
> + * Reserve a chunk of process address space to use as the VM bind
> +address
> + * for a BO, and hand back a pointer inside it aligned either to
> +bo_size
> + * ("aligned" case) or to 64K ("unaligned" case, i.e. deliberately not
> + * aligned to bo_size).
> + *
> + * This replaces the previous use of aligned_alloc(bo_size, bo_size):
> + * aligned_alloc() requires size to be a multiple of alignment, which
> + * doesn't hold for most entries in alloc_sizes[] (multiples of 64K,
> +not
> + * generally powers of two), so the old "aligned" path was silently
> + * returning a mis-aligned pointer for the majority of sizes tested.
> + * Reserving with PROT_NONE also avoids committing real memory that
> +just
> + * gets thrown away once xe_bo_map_fixed() replaces it with the BO mapping.
> + */
> +static void bo_alloc_reserve_va(struct bo_alloc *b, uint32_t flags,
> +uint64_t va_base) {
> +	uint64_t align = (flags & UNALIGNED) ? SZ_64K : b->bo_size;
> +	size_t reserve_size = b->bo_size + align;
> +	uintptr_t addr;
> +	uintptr_t aligned_addr;
> +	void *reserve;
> +
> +	/*
> +	 * Keep each BO reservation in the caller-selected VA window so threads
> +	 * and per-process tests do not clash on random mmap addresses. The
> +	 * unaligned case still uses a 64 KiB alignment while the fixed address is
> +	 * only a hint to keep the ranges stable and non-overlapping.
> +	 */
> +	addr = ALIGN(va_base, align);
> +	reserve = mmap((void *)addr, reserve_size, PROT_NONE,
> +		       MAP_PRIVATE | MAP_ANONYMOUS |
> MAP_FIXED_NOREPLACE, -1, 0);
> +	if (reserve == MAP_FAILED) {
> +		reserve = mmap(NULL, reserve_size, PROT_NONE,
> +			       MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
> +		igt_assert(reserve != MAP_FAILED);
> +		addr = (uintptr_t)reserve;
> +	}
> +
> +	b->va_reserve = reserve;
> +	b->va_reserve_size = reserve_size;
> +
> +	addr = (uintptr_t)reserve;
> +
> +	/*
> +	 * Round up to the next multiple of 'align'.
> +	 * Works for arbitrary alignments, not just powers of two.
> +	 */
> +	aligned_addr = ((addr + align - 1) / align) * align;
> +
> +	b->va = (void *)aligned_addr;
> +	b->gpu_va = to_user_pointer(b->va);
> +
> +	igt_debug("reserve=0x%llx align=0x%llx bo_size=0x%llx\n", (unsigned
> long long)addr,
> +		  (unsigned long long)align, (unsigned long long)b->bo_size);
> +
> +	igt_assert_eq_u64(b->gpu_va % align, 0); }
> +
> +static void alloc_sizes_init(void)
> +{
> +	int i;
> +
> +	alloc_sizes = malloc(sizeof(*alloc_sizes) * N_ALLOC_SIZES);
> +
> +	/* For now just do increments of 64k */
> +	for (i = 0; i < N_ALLOC_SIZES; ++i)
> +		alloc_sizes[i] = 0x10000ull * (i + 1); }
> +
> +static void alloc_sizes_fini(void)
> +{
> +	free(alloc_sizes);
> +}
> +
> +
> +static uint32_t wkey = 0xc0ffeeull;
> +#define WRITE_VALUE(page)	(((wkey) << 8) | (page))
> +
> +static void check_exec_data(void *ptr, int n_pages) {
> +	int i;
> +
> +	for (i = 0; i < n_pages; ++i) {
> +		struct batch_data *data = ptr + i * SZ_4K;
> +
> +		igt_assert_eq(data->data, WRITE_VALUE(i));
> +	}
> +}
> +
> +static void bo_alloc_release_va(struct bo_alloc *b) {
> +	if (!b->va_reserve || !b->va_reserve_size)
> +		return;
> +	munmap(b->va_reserve, b->va_reserve_size);
> +	b->va_reserve = NULL;
> +	b->va_reserve_size = 0;
> +}
> +
> +/*
> + * PREPARE step: allocate the VA range and create the BO. Doesn't touch
> +the
> + * GPU. vm is passed through unbound to xe_bo_create() exactly as before:
> + * non-evict BOs are created VM-private, evict BOs are created external
> +so
> + * they can be freely rebound after being evicted.
> + */
> +static void create_bo_arr(int fd, uint32_t vm, struct bo_alloc *bos,  int n_bos,
> uint16_t gt_id,
> +			  uint32_t flags, uint64_t start_va) {
> +	uint64_t alignment = xe_get_default_alignment(fd);
> +	uint32_t create_flags;
> +	int i;
> +
> +	igt_assert(n_bos > 0);
> +	create_flags = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> +
> +	for (i = 0; i < n_bos; i++) {
> +		igt_assert_f(bos[i].bo_size,
> +			     "BO[%d] has zero size\n", i);
> +
> +		bos[i].bo_size = ALIGN(bos[i].bo_size, alignment);
> +		bo_alloc_reserve_va(&bos[i], flags, start_va + (i * alignment));
> +		bos[i].map = NULL;
> +
> +		bos[i].bo = xe_bo_create(fd, vm,
> +					 bos[i].bo_size,
> +					 vram_if_possible(fd, gt_id),
> +					 create_flags);
> +
> +		igt_assert_f(bos[i].bo,
> +			     "Failed to create BO[%d]: gt=%u size=%#llx
> gpu_va=%#llx\n",
> +			     i, gt_id, (unsigned long long)bos[i].bo_size,
> +			     (unsigned long long)bos[i].gpu_va);
> +	}
> +}
> +
> +/*
> + * BIND step: bind one or more BOs as a single array-of-binds ioctl
> +call
> + * (see __xe_vm_bind_array() above), replacing the previous open-coded
> + * xe_vm_bind_sync() called once per BO.
> + */
> +static int test_bind_individual(int fd, uint32_t vm, struct bo_alloc
> +*bos, int n_bos) {
> +	struct drm_xe_sync sync = {
> +		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.handle = syncobj_create(fd, 0),
> +	};
> +	int i, ret, j;
> +
> +	for (i = 0; i < n_bos; i++) {
> +		struct drm_xe_sync *bind_sync = NULL;
> +		uint32_t num_syncs = 0;
> +
> +		igt_debug("bind[%d/%d] size=%llu MiB va=0x%llx bo=%u\n", i,
> n_bos,
> +			  (unsigned long long)(bos[i].bo_size >> 20),
> +			  (unsigned long long)bos[i].gpu_va,
> +			  bos[i].bo);
> +
> +		/*
> +		 * Signal only after the last async bind.
> +		 * VM bind operations on the same VM are ordered.
> +		 */
> +		if (i == n_bos - 1) {
> +			bind_sync = &sync;
> +			num_syncs = 1;
> +		}
> +
> +		ret = __xe_vm_bind(fd, vm, 0, bos[i].bo, 0, bos[i].gpu_va,
> bos[i].bo_size,
> +				   DRM_XE_VM_BIND_OP_MAP, 0, bind_sync,
> num_syncs, 0,
> +				   (uint8_t)-1, 0);
> +		if (ret == -ENOMEM || ret == -ENOSPC) {
> +			igt_debug("VM Bind failed at BO[%d]: ret=%d errno=%d
> (%s)\n",
> +				  i, ret, errno, strerror(-ret));
> +			for (j = 0; j < i; j++)
> +				xe_vm_unbind_sync(fd, vm, 0, bos[j].gpu_va,
> bos[j].bo_size);
> +			syncobj_destroy(fd, sync.handle);
> +			return ret;
> +		}
> +		igt_assert_eq(ret, 0);
> +	}
> +
> +	igt_assert_f(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL),
> +		     "Timed out waiting for async VM binds\n");
> +
> +	syncobj_destroy(fd, sync.handle);
> +
> +	return 0;
> +}
> +
> +static int test_bind(int fd, uint32_t vm, struct bo_alloc *bos, int
> +n_bos, uint32_t flags) {
> +		return test_bind_individual(fd, vm, bos, n_bos); }
> +Check indentation in return line.
> +/*
> + * UNBIND step: unbind each BO synchronously.
> + * This path intentionally avoids array-unbind ioctls for stability.
> + * BO in the batch.
> + */
> +static void test_unbind(int fd, uint32_t vm, struct bo_alloc *bos, int
> +n_bos) {
> +	int i;
> +
> +	igt_assert(n_bos > 0);
> +
> +	for (i = 0; i < n_bos; ++i)
> +		xe_vm_unbind_sync(fd, vm, 0, bos[i].gpu_va, bos[i].bo_size); }
> +
> +/*
> + * Map every BO after binding.
> + *
> + * gpu_va is also used as the fixed CPU virtual address, following the
> + * original test design.
> + */
> +static void test_map_bos(int fd, struct bo_alloc *bos, int n_bos) {
> +	int i;
> +
> +	for (i = 0; i < n_bos; i++) {
> +		bos[i].map = xe_bo_map_fixed(fd,
> +					     bos[i].bo,
> +					     bos[i].bo_size,
> +					     bos[i].gpu_va);
> +
> +		igt_assert_f(bos[i].map != MAP_FAILED,
> +			     "Failed to map BO[%d]: bo=%u size=%#llx
> address=%#llx\n",
> +			     i, bos[i].bo,
> +			     (unsigned long long)bos[i].bo_size,
> +			     (unsigned long long)bos[i].gpu_va);
> +	}
> +}
> +
> +/*
> + * Build and submit one batch for every 4 KiB page of one BO.
> + */
> +static void execute_bo(int fd, uint32_t exec_queue,
> +		       struct bo_alloc *bo)
> +{
> +	struct drm_xe_sync sync = {
> +		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.handle = syncobj_create(fd, 0),
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.exec_queue_id = exec_queue,
> +		.num_syncs = 0,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	const uint64_t batch_offset =
> +		offsetof(struct batch_data, batch);
> +	const uint64_t data_offset =
> +		offsetof(struct batch_data, data);
> +	int n_pages = bo->bo_size >> SZ_4K_SHIFT;
> +	int i;
> +
> +	for (i = 0; i < n_pages; i++) {
> +		struct batch_data *data;
> +		uint64_t page_addr;
> +		uint64_t batch_addr;
> +		uint64_t data_addr;
> +		int b = 0;
> +
> +		data = (void *)((char *)bo->map + i * SZ_4K);
> +
> +		page_addr = bo->gpu_va + (i * SZ_4K);
> +		batch_addr = page_addr + batch_offset;
> +		data_addr = page_addr + data_offset;
> +
> +		memset(data, 0, sizeof(*data));
> +
> +		data->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> +		data->batch[b++] = lower_32_bits(data_addr);
> +		data->batch[b++] = upper_32_bits(data_addr);
> +		data->batch[b++] = WRITE_VALUE(i);
> +		data->batch[b++] = MI_BATCH_BUFFER_END;
> +
> +		igt_assert(b <= ARRAY_SIZE(data->batch));
> +
> +		exec.address = batch_addr;
> +
> +		/*
> +		 * Signal only after the final page submission.
> +		 */
> +		exec.num_syncs = i == n_pages - 1 ? 1 : 0;
> +
> +		xe_exec(fd, &exec);
> +	}
> +
> +	igt_assert_f(syncobj_wait(fd, &sync.handle, 1,
> +				  INT64_MAX, 0, NULL),
> +		     "Timed out waiting for BO execution\n");
> +
> +	check_exec_data(bo->map, n_pages);
> +
> +	syncobj_destroy(fd, sync.handle);
> +}
> +
> +static void execute_multi_bos(int fd, uint32_t exec_queue,
> +			      struct bo_alloc *bos, int n_bos) {
> +	int i;
> +
> +	test_map_bos(fd, bos, n_bos);
> +
> +	for (i = 0; i < n_bos; i++)
> +		execute_bo(fd, exec_queue, &bos[i]);
> +}
> +
> +static void bo_release(int fd, struct bo_alloc *b) {
> +	if (b->map)
> +		munmap(b->map, b->bo_size);
> +	if (b->bo)
> +		gem_close(fd, b->bo);
> +	bo_alloc_release_va(b);
> +}
> +
> +/*
> + * Runs prepare + bind + execute for n_bos BOs at once (n_bos == 1
> + * reproduces the original single-BO behaviour). If LEAK_BINDING is not
> + * set, unbinds afterwards. If LEAK_BO is set, the BOs are left mapped
> +and
> + * bound and returned to the caller (as an array the caller owns and
> +must
> + * eventually pass to check_leak_multi_group()/free()); otherwise
> +they're torn down
> + * immediately and NULL is returned.
> + */
> +static struct bo_alloc *test_alloc_sizes(int fd, uint32_t vm, uint32_t exec_q,
> +					 uint16_t gt_id, uint64_t *sizes,
> +					 int n_bos, uint32_t flags,  uint64_t
> va_base) {
> +	struct bo_alloc *bos;
> +	int i, ret;
> +
> +	bos = calloc(n_bos, sizeof(*bos));
> +	igt_assert(bos);
> +
> +	for (i = 0; i < n_bos; ++i)
> +		bos[i].bo_size = sizes[i];
> +
> +	create_bo_arr(fd, vm, bos, n_bos, gt_id, flags, va_base);
> +	ret = test_bind(fd, vm, bos, n_bos, flags);
> +	if (ret == -ENOMEM || ret == -ENOSPC)
> +		goto cleanup;
> +
> +	igt_assert_eq(ret, 0);
> +	execute_multi_bos(fd, exec_q, bos, n_bos);
> +
> +	if (!(flags & LEAK_BINDING))
> +		test_unbind(fd, vm, bos, n_bos);
> +
> +cleanup:
> +
> +	if (ret || !(flags & LEAK_BO)) {
> +		for (i = 0; i < n_bos; ++i)
> +			bo_release(fd, &bos[i]);
> +		free(bos);
> +		return NULL;
> +	}
> +
> +	return bos;
> +}
> +
> +/* Thin single-BO wrapper: keeps the existing call sites unchanged. */
> +static struct bo_alloc *test_alloc_size(int fd, uint32_t vm, uint32_t q,
> +					uint16_t gt_id, uint64_t bo_size,
> +					uint32_t flags, uint64_t va_base)
> +{
> +	struct bo_alloc *bos = test_alloc_sizes(fd, vm, q, gt_id, &bo_size,
> +						1, flags, va_base);
> +
> +	/* Caller only ever gets/frees a single struct, so unwrap it. */
> +	if (bos) {
> +		struct bo_alloc *b = malloc(sizeof(*b));
> +
> +		igt_assert(b);
> +		*b = bos[0];
> +		free(bos);
> +		return b;
> +	}
> +
> +	return NULL;
> +}
> +
> +static void all_sizes_once(int fd, struct drm_xe_engine_class_instance
> +*hwe) {
> +	uint32_t vm, q;
> +	int i;
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	q =  xe_exec_queue_create(fd, vm, hwe, 0);
> +
> +	for (i = 0; i < N_ALLOC_SIZES; ++i)
> +		test_alloc_size(fd, vm, q, hwe->gt_id, alloc_sizes[i], 0,
> +BO_BIND_BASE_ADDR);
> +
> +	xe_exec_queue_destroy(fd, q);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint16_t seen_gt[64];
> +	int n_seen = 0, j;
> +	bool dup;
> +
> +	if (t->requires_evict_ram) {
> +		igt_require(xe_has_vram(fd));
> +		igt_require(igt_get_avail_ram_mb() >=
> +			    (xe_visible_vram_size(fd, 0) >> 20) / 2);
> +	}
> +
> +	/*
> +	 * These tests only care about which GT (and  therefore which VRAM
> region,
> +	 * via gt_id -> vram_if_possible()) the BO ends up on, not which specific
> +	 * engine issues the exec. So run once per distinct gt_id instead of once
> +	 * per engine: on single-GT parts that's one dynamic child same as before,
> +	 * and on multi-tile parts it exercises every tile's VRAM instead of silently
> +	 * only ever hitting whichever GT the first engine happened to belong to
> +	 */
> +	xe_for_each_engine(fd, hwe) {
> +		dup = false;
> +
> +		for (j = 0; j < n_seen; ++j) {
> +			if (seen_gt[j] == hwe->gt_id) {
> +				dup = true;
> +				break;
> +			}
> +		}
> +		if (dup)
> +			continue;
> +
> +		igt_assert(n_seen < ARRAY_SIZE(seen_gt));
> +		seen_gt[n_seen++] = hwe->gt_id;
> +
> +		igt_dynamic_f("gt%u", hwe->gt_id) {
> +			switch (t->type) {
> +			case TYPE_ALL_SIZES:
> +				all_sizes_once(fd, hwe);
> +				break;
> +			default:
> +				break;
> +
> +			}
> +		}
> +	}
> +}
> +
> +/*
> + * Data-driven subtest matrix.
> + *
> + * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly
> +one
> + * engine per invocation, so they're wired up as a dynamic child
> +subtest
> + * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
> + *
> + * TYPE_THREAD / TYPE_PROCESS are deliberately NOT split per engine here:
> + * threads() and processes() already do their own xe_for_each_engine()
> +to
> + * spawn one thread/process per engine internally. Wrapping those in a
> + * second, outer per-engine loop would run the full all-engine fan-out
> + * once for every engine on the machine, multiplying the runtime by the
> + * engine count and re-exercising every engine N times over. So these
> + * stay flat, single subtests.
> + */
> +
> +static const struct test_case test_matrix[] = {
> +	{ "all-sizes-once", 0, 0, TYPE_ALL_SIZES, false }, };
> +
> +int igt_main()
> +{
> +	int fd, i;
> +
> +	igt_fixture() {
> +		fd = drm_open_driver(DRIVER_XE);
> +		alloc_sizes_init();
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(test_matrix); ++i) {
> +		const struct test_case *t = &test_matrix[i];
> +
> +		switch (t->type) {
> +		case TYPE_ALL_SIZES:
> +			igt_subtest_with_dynamic_f("%s", t->name)
> +				run_gt_dynamic_subtests(fd, t);
> +		}
> +	}
> +
> +	igt_fixture() {
> +		alloc_sizes_fini();
> +		drm_close_driver(fd);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build index 4f5c9be7b..f3e1802fd
> 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -283,6 +283,7 @@ intel_kms_progs = [
> 
>  intel_xe_progs = [
>  	'xe_wedged',
> +        'xe_bo_alloc',
uses spaces instead of a tab, inconsistent use.
>  	'xe_ccs',
>  	'xe_create',
>  	'xe_compute',
> --
> 2.52.0

RE: [PATCH i-g-t v5 2/5] tests/intel: Add random-size BO leak tests

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Thomas, Sobin <sobin.thomas@intel.com>
> Sent: 22 September 2026 16:35
> To: igt-dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
> Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t v5 2/5] tests/intel: Add random-size BO leak tests
> 
> Add new RANDOM_SIZE subtests exercising randomly sized BO allocation This
> test excercises allocation, execution, validation and cleanup paths across a wider
> mix of BO size, helping to detect issues that may only appear with specific size
> combinations.
> 
> Add the following subtests:
> - rand-sizes-10
> - rand-sizes-100
> - rand-sizes-100-unaligned
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>  tests/intel/xe_bo_alloc.c | 126 ++++++++++++++++++++++++++++++++++----
>  1 file changed, 115 insertions(+), 11 deletions(-)
> 
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c index
> 8680fe518..bd5bf5a33 100644
> --- a/tests/intel/xe_bo_alloc.c
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -34,6 +34,20 @@
>   * SUBTEST: all-sizes-once
>   * Description: Test all BO allocations sizes in test table
>   * Test category: functionality test
> + *
> + * SUBTEST: rand-sizes-10
> + * Description: Test 10 random BO allocation sizes in test table
> + * Test category: functionality test
> + *
> + * SUBTEST: rand-sizes-100
> + * Description: Test 100 random BO allocation sizes in test table
> + * Test category: functionality test
> + *
> + * SUBTEST: rand-sizes-100-unaligned
> + * Description: Test 100 random BO allocation sizes in test table,
> + unaligned bind addresses
> + * Test category: functionality test
> + *
> + *
>   */
> 
>  #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) @@ -45,7 +59,7 @@ static
> uint64_t *alloc_sizes;
>  /*
>   * Data-driven subtest matrix.
>   *
> - * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly one
> + * TYPE_ALL_SIZES / TYPE_RANDOM_SIZE / TYPE_ARRAY_BIND all exercise
> + exactly one
>   * engine per invocation, so they're wired up as a dynamic child subtest
>   * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
>   *
> @@ -59,6 +73,7 @@ static uint64_t *alloc_sizes;
>   */
>  enum test_type {
>  	TYPE_ALL_SIZES,
> +	TYPE_RANDOM_SIZE,
>  };
> 
>  struct test_case {
> @@ -337,6 +352,15 @@ static void test_map_bos(int fd, struct bo_alloc *bos, int
> n_bos)
>  	}
>  }
> 
> +static void bo_release(int fd, struct bo_alloc *b) {
> +	if (b->map)
> +		munmap(b->map, b->bo_size);
> +	if (b->bo)
> +		gem_close(fd, b->bo);
> +	bo_alloc_release_va(b);
> +}
> +
>  /*
>   * Build and submit one batch for every 4 KiB page of one BO.
>   */
> @@ -414,15 +438,6 @@ static void execute_multi_bos(int fd, uint32_t
> exec_queue,
>  		execute_bo(fd, exec_queue, &bos[i]);
>  }
> 
> -static void bo_release(int fd, struct bo_alloc *b) -{
> -	if (b->map)
> -		munmap(b->map, b->bo_size);
> -	if (b->bo)
> -		gem_close(fd, b->bo);
> -	bo_alloc_release_va(b);
> -}
> -
>  /*
>   * Runs prepare + bind + execute for n_bos BOs at once (n_bos == 1
>   * reproduces the original single-BO behaviour). If LEAK_BINDING is not @@ -
> 488,6 +503,88 @@ static struct bo_alloc *test_alloc_size(int fd, uint32_t vm,
> uint32_t q,
>  	return NULL;
>  }
> 
> +static void validate_bo_leak(int fd, uint32_t vm, struct bo_alloc *bos,
> +			     int n_bos, uint32_t flags)
> +{
> +	int i;
> +
> +	for (i = 0; i < n_bos; ++i)
> +		check_exec_data(bos[i].map, bos[i].bo_size >> SZ_4K_SHIFT);
> +
> +	/* Migrate the whole group back into VRAM, recheck */
> +	if (flags & EVICT) {
> +		igt_assert_eq(test_bind(fd, vm, bos, n_bos, flags), 0);
> +
> +		for (i = 0; i < n_bos; ++i)
> +			check_exec_data(bos[i].map, bos[i].bo_size >>
> SZ_4K_SHIFT);
> +
> +		test_unbind(fd, vm, bos, n_bos);
> +	}
> +
> +	for (i = 0; i < n_bos; ++i)
> +		bo_release(fd, &bos[i]);
> +}
> +
> +static void check_leak_multi_group(int fd, uint32_t vm, struct bo_group
> **groups,
> +				   int count, uint32_t flags)
> +{
> +	int i;
> +
> +	for (i = 0; i < count; ++i) {
> +		if (!groups[i])
> +			continue;
> +
> +		validate_bo_leak(fd, vm, groups[i]->bos, groups[i]->n_bos, flags);
> +		free(groups[i]);
> +	}
> +}
> +
> +static void alloc_rand_size_bos(int fd, struct drm_xe_engine_class_instance
> *hwe,
> +				int count, uint64_t vram_per_process,
> pthread_barrier_t *barrier,
> +				uint32_t flags)
> +{
> +	struct bo_group **leaks = NULL;
> +	uint32_t vm, q, bo_size;
> +	uint64_t vram_used = 0;
> +	int i, max_batches = (count == -1) ? MAX_ALLOCATIONS : count;
> +
> +	igt_assert(count > 0 || (flags & EVICT && flags & LEAK_BO));
> +	leaks = malloc(sizeof(*leaks) * max_batches);
> +	igt_assert(leaks);
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	q =  xe_exec_queue_create(fd, vm, hwe, 0);
> +
> +	for (i = 0; i < count || vram_used < vram_per_process; ++i) {
> +		struct bo_alloc *bo;
> +
> +		bo_size = alloc_sizes[rand() % N_ALLOC_SIZES];
> +
> +		igt_assert(i < max_batches);
> +		bo = test_alloc_size(fd, vm, q, hwe->gt_id, bo_size, flags,
> +				     BO_BIND_BASE_ADDR);
> +		if (bo) {
> +			leaks[i] = malloc(sizeof(*leaks[i]));
> +			igt_assert(leaks[i]);
> +
> +			leaks[i]->bos = bo;
> +			leaks[i]->n_bos = 1;
> + 
> +			vram_used += bo->bo_size;

Currently, the test only does similar to alloc_all_size but does with random size, leak is not happening.
As LEAK_BO flag is not set in any of the three subtests, 
Code related to LEAK case is never being executed, it always goes to else case.
validate_leak_bo will not execute. So, LEAK_BO need to be set.

> +		} else {
> +			leaks[i] = NULL;
> +		}
> +	}
> +
> +	if (barrier)
> +		pthread_barrier_wait(barrier);
> +	check_leak_multi_group(fd, vm, leaks, i, flags);
> +
> +	xe_exec_queue_destroy(fd, q);
> +	xe_vm_destroy(fd, vm);
> +	free(leaks);
> +}
> +
>  static void all_sizes_once(int fd, struct drm_xe_engine_class_instance *hwe)  {
>  	uint32_t vm, q;
> @@ -544,6 +641,9 @@ static void run_gt_dynamic_subtests(int fd, const struct
> test_case *t)
>  			case TYPE_ALL_SIZES:
>  				all_sizes_once(fd, hwe);
>  				break;
> +			case TYPE_RANDOM_SIZE:
> +				alloc_rand_size_bos(fd, hwe, t->count, 0, NULL,
> t->flags);
> +				break;
>  			default:
>  				break;
> 
> @@ -555,7 +655,7 @@ static void run_gt_dynamic_subtests(int fd, const struct
> test_case *
>  /*
>   * Data-driven subtest matrix.
>   *
> - * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise exactly one
> + * TYPE_ALL_SIZES / TYPE_RANDOM_SIZE / TYPE_ARRAY_BIND all exercise
> + exactly one
>   * engine per invocation, so they're wired up as a dynamic child subtest
>   * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
>   *
> @@ -570,6 +670,9 @@ static void run_gt_dynamic_subtests(int fd, const struct
> test_case *t)
> 
>  static const struct test_case test_matrix[] = {
>  	{ "all-sizes-once", 0, 0, TYPE_ALL_SIZES, false },
> +	{ "rand-sizes-10", 10, 0, TYPE_RANDOM_SIZE, false },
> +	{ "rand-sizes-100", 100, 0, TYPE_RANDOM_SIZE, false },
> +	{ "rand-sizes-100-unaligned", 100, UNALIGNED, TYPE_RANDOM_SIZE,
> false
> +},
>  };
> 
>  int igt_main()
> @@ -586,6 +689,7 @@ int igt_main()
> 
>  		switch (t->type) {
>  		case TYPE_ALL_SIZES:
> +		case TYPE_RANDOM_SIZE:
>  			igt_subtest_with_dynamic_f("%s", t->name)
>  				run_gt_dynamic_subtests(fd, t);
>  		}
> --
> 2.52.0

RE: [PATCH i-g-t v5 2/5] tests/intel: Add random-size BO leak tests

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Dandamudi, Priyanka
> Sent: 01 October 2026 12:20
> To: Thomas, Sobin <sobin.thomas@intel.com>; igt-dev@lists.freedesktop.org;
> Brost, Matthew <matthew.brost@intel.com>
> Cc: Sharma, Nishit <nishit.sharma@intel.com>
> Subject: RE: [PATCH i-g-t v5 2/5] tests/intel: Add random-size BO leak tests
> 
> 
> 
> > -----Original Message-----
> > From: Thomas, Sobin <sobin.thomas@intel.com>
> > Sent: 22 September 2026 16:35
> > To: igt-dev@lists.freedesktop.org; Brost, Matthew
> > <matthew.brost@intel.com>
> > Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka
> > <priyanka.dandamudi@intel.com>
> > Subject: [PATCH i-g-t v5 2/5] tests/intel: Add random-size BO leak
> > tests
> >
> > Add new RANDOM_SIZE subtests exercising randomly sized BO allocation
> > This test excercises allocation, execution, validation and cleanup
> > paths across a wider mix of BO size, helping to detect issues that may
> > only appear with specific size combinations.
> >
> > Add the following subtests:
> > - rand-sizes-10
> > - rand-sizes-100
> > - rand-sizes-100-unaligned
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> > ---
> >  tests/intel/xe_bo_alloc.c | 126
> > ++++++++++++++++++++++++++++++++++----
> >  1 file changed, 115 insertions(+), 11 deletions(-)
> >
> > diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
> > index
> > 8680fe518..bd5bf5a33 100644
> > --- a/tests/intel/xe_bo_alloc.c
> > +++ b/tests/intel/xe_bo_alloc.c
> > @@ -34,6 +34,20 @@
> >   * SUBTEST: all-sizes-once
> >   * Description: Test all BO allocations sizes in test table
> >   * Test category: functionality test
> > + *
> > + * SUBTEST: rand-sizes-10
> > + * Description: Test 10 random BO allocation sizes in test table
> > + * Test category: functionality test
> > + *
> > + * SUBTEST: rand-sizes-100
> > + * Description: Test 100 random BO allocation sizes in test table
> > + * Test category: functionality test
> > + *
> > + * SUBTEST: rand-sizes-100-unaligned
> > + * Description: Test 100 random BO allocation sizes in test table,
> > + unaligned bind addresses
> > + * Test category: functionality test
> > + *
> > + *
> >   */
> >
> >  #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) @@ -45,7 +59,7 @@
> > static uint64_t *alloc_sizes;
> >  /*
> >   * Data-driven subtest matrix.
> >   *
> > - * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise
> > exactly one
> > + * TYPE_ALL_SIZES / TYPE_RANDOM_SIZE / TYPE_ARRAY_BIND all exercise
> > + exactly one
> >   * engine per invocation, so they're wired up as a dynamic child subtest
> >   * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
> >   *
> > @@ -59,6 +73,7 @@ static uint64_t *alloc_sizes;
> >   */
> >  enum test_type {
> >  	TYPE_ALL_SIZES,
> > +	TYPE_RANDOM_SIZE,
> >  };
> >
> >  struct test_case {
> > @@ -337,6 +352,15 @@ static void test_map_bos(int fd, struct bo_alloc
> > *bos, int
> > n_bos)
> >  	}
> >  }
> >
> > +static void bo_release(int fd, struct bo_alloc *b) {
> > +	if (b->map)
> > +		munmap(b->map, b->bo_size);
> > +	if (b->bo)
> > +		gem_close(fd, b->bo);
> > +	bo_alloc_release_va(b);
> > +}
> > +
> >  /*
> >   * Build and submit one batch for every 4 KiB page of one BO.
> >   */
> > @@ -414,15 +438,6 @@ static void execute_multi_bos(int fd, uint32_t
> > exec_queue,
> >  		execute_bo(fd, exec_queue, &bos[i]);  }
> >
> > -static void bo_release(int fd, struct bo_alloc *b) -{
> > -	if (b->map)
> > -		munmap(b->map, b->bo_size);
> > -	if (b->bo)
> > -		gem_close(fd, b->bo);
> > -	bo_alloc_release_va(b);
> > -}
> > -
> >  /*
> >   * Runs prepare + bind + execute for n_bos BOs at once (n_bos == 1
> >   * reproduces the original single-BO behaviour). If LEAK_BINDING is
> > not @@ -
> > 488,6 +503,88 @@ static struct bo_alloc *test_alloc_size(int fd,
> > uint32_t vm, uint32_t q,
> >  	return NULL;
> >  }
> >
> > +static void validate_bo_leak(int fd, uint32_t vm, struct bo_alloc *bos,
> > +			     int n_bos, uint32_t flags)
> > +{
> > +	int i;
> > +
> > +	for (i = 0; i < n_bos; ++i)
> > +		check_exec_data(bos[i].map, bos[i].bo_size >> SZ_4K_SHIFT);
> > +
> > +	/* Migrate the whole group back into VRAM, recheck */
> > +	if (flags & EVICT) {
> > +		igt_assert_eq(test_bind(fd, vm, bos, n_bos, flags), 0);
EVICT is not required in this commit as its not being set or used anywhere.
> > +
> > +		for (i = 0; i < n_bos; ++i)
> > +			check_exec_data(bos[i].map, bos[i].bo_size >>
> > SZ_4K_SHIFT);
> > +
> > +		test_unbind(fd, vm, bos, n_bos);
> > +	}
> > +
> > +	for (i = 0; i < n_bos; ++i)
> > +		bo_release(fd, &bos[i]);
> > +}
> > +
> > +static void check_leak_multi_group(int fd, uint32_t vm, struct
> > +bo_group
> > **groups,
> > +				   int count, uint32_t flags)
> > +{
> > +	int i;
> > +
> > +	for (i = 0; i < count; ++i) {
> > +		if (!groups[i])
> > +			continue;
> > +
> > +		validate_bo_leak(fd, vm, groups[i]->bos, groups[i]->n_bos, flags);
> > +		free(groups[i]);
> > +	}
> > +}
> > +
> > +static void alloc_rand_size_bos(int fd, struct
> > +drm_xe_engine_class_instance
> > *hwe,
> > +				int count, uint64_t vram_per_process,
> > pthread_barrier_t *barrier,
> > +				uint32_t flags)
> > +{
> > +	struct bo_group **leaks = NULL;
> > +	uint32_t vm, q, bo_size;
> > +	uint64_t vram_used = 0;
> > +	int i, max_batches = (count == -1) ? MAX_ALLOCATIONS : count;
> > +
> > +	igt_assert(count > 0 || (flags & EVICT && flags & LEAK_BO));
> > +	leaks = malloc(sizeof(*leaks) * max_batches);
> > +	igt_assert(leaks);
> > +
> > +	vm = xe_vm_create(fd, 0, 0);
> > +	q =  xe_exec_queue_create(fd, vm, hwe, 0);
> > +
> > +	for (i = 0; i < count || vram_used < vram_per_process; ++i) {
> > +		struct bo_alloc *bo;
> > +
> > +		bo_size = alloc_sizes[rand() % N_ALLOC_SIZES];
> > +
> > +		igt_assert(i < max_batches);
> > +		bo = test_alloc_size(fd, vm, q, hwe->gt_id, bo_size, flags,
> > +				     BO_BIND_BASE_ADDR);
> > +		if (bo) {
> > +			leaks[i] = malloc(sizeof(*leaks[i]));
> > +			igt_assert(leaks[i]);
> > +
> > +			leaks[i]->bos = bo;
> > +			leaks[i]->n_bos = 1;
> > +
> > +			vram_used += bo->bo_size;
> 
> Currently, the test only does similar to alloc_all_size but does with random size,
> leak is not happening.
> As LEAK_BO flag is not set in any of the three subtests, Code related to LEAK case
> is never being executed, it always goes to else case.
> validate_leak_bo will not execute. So, LEAK_BO need to be set.
> 
> > +		} else {
> > +			leaks[i] = NULL;
> > +		}
> > +	}
> > +
> > +	if (barrier)
> > +		pthread_barrier_wait(barrier);
pthread usage is not necessary here, I see its not used anywhere.
> > +	check_leak_multi_group(fd, vm, leaks, i, flags);
> > +
> > +	xe_exec_queue_destroy(fd, q);
> > +	xe_vm_destroy(fd, vm);
> > +	free(leaks);
> > +}
> > +
> >  static void all_sizes_once(int fd, struct drm_xe_engine_class_instance *hwe)  {
> >  	uint32_t vm, q;
> > @@ -544,6 +641,9 @@ static void run_gt_dynamic_subtests(int fd, const
> > struct test_case *t)
> >  			case TYPE_ALL_SIZES:
> >  				all_sizes_once(fd, hwe);
> >  				break;
> > +			case TYPE_RANDOM_SIZE:
> > +				alloc_rand_size_bos(fd, hwe, t->count, 0, NULL,
> > t->flags);
> > +				break;
> >  			default:
> >  				break;
> >
> > @@ -555,7 +655,7 @@ static void run_gt_dynamic_subtests(int fd, const
> > struct test_case *
> >  /*
> >   * Data-driven subtest matrix.
> >   *
> > - * TYPE_ALL_SIZES / TYPE_SINGLE / TYPE_ARRAY_BIND all exercise
> > exactly one
> > + * TYPE_ALL_SIZES / TYPE_RANDOM_SIZE / TYPE_ARRAY_BIND all exercise
> > + exactly one
> >   * engine per invocation, so they're wired up as a dynamic child subtest
> >   * per engine below (igt_subtest_with_dynamic_f() + igt_dynamic_f()).
> >   *
> > @@ -570,6 +670,9 @@ static void run_gt_dynamic_subtests(int fd, const
> > struct test_case *t)
> >
> >  static const struct test_case test_matrix[] = {
> >  	{ "all-sizes-once", 0, 0, TYPE_ALL_SIZES, false },
> > +	{ "rand-sizes-10", 10, 0, TYPE_RANDOM_SIZE, false },
> > +	{ "rand-sizes-100", 100, 0, TYPE_RANDOM_SIZE, false },
> > +	{ "rand-sizes-100-unaligned", 100, UNALIGNED, TYPE_RANDOM_SIZE,
> > false
> > +},
> >  };
> >
> >  int igt_main()
> > @@ -586,6 +689,7 @@ int igt_main()
> >
> >  		switch (t->type) {
> >  		case TYPE_ALL_SIZES:
> > +		case TYPE_RANDOM_SIZE:
> >  			igt_subtest_with_dynamic_f("%s", t->name)
> >  				run_gt_dynamic_subtests(fd, t);
> >  		}
> > --
> > 2.52.0

RE: [PATCH i-g-t v5 3/5] tests/intel: Add array-of-binds random-size allocation tests

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Thomas, Sobin <sobin.thomas@intel.com>
> Sent: 22 September 2026 16:35
> To: igt-dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
> Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t v5 3/5] tests/intel: Add array-of-binds random-size
> allocation tests
> 
> Add new array-binds-rand-sizes-* subtests that allocate batches of random-sized
> BOs and bind them using a single array-of-binds operation.
> 
> The new tests allocate 10 BOs per batch and exercise both aligned and unaligned
> bind addresses. This extends existing eviction coverage by verifying that BOs with
> varying sizes can be bound, managed and evicted correctly when submitted as a
> single bind array rather than individual bind operations.
> 
> Introduce alloc_random_size_bos_array_bind(), which mirrors the existing
> random-size allocation flow while grouping multiple BOs into a single array bind
> submission. This is particularly useful for eviction testing where a set of BOs
> needs to be resident or evicted as a unit.
> 
> The tests are intended to provide additional coverage for array-of-binds handling
> under random allocation patterns and VRAM pressure scenarios.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>  tests/intel/xe_bo_alloc.c | 177 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 177 insertions(+)
> 
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c index
> bd5bf5a33..343d07626 100644
> --- a/tests/intel/xe_bo_alloc.c
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -47,7 +47,15 @@
>   * Description: Test 100 random BO allocation sizes in test table, unaligned bind
> addresses
>   * Test category: functionality test
>   *
> + * SUBTEST: array-binds-rand-sizes-10
> + * Description: Test 10 batches of 10 random BO allocation sizes each
> + bound together as a
> + * single array of binds
> + * Test category: functionality test
>   *
> + * SUBTEST: array-binds-rand-sizes-10-unaligned
> + * Description: Test 10 batches of 10 random BO allocation sizes bound
> + together as a single
> + * array of binds, unaligned bind addresses
> + * Test category: functionality test
>   */
> 
>  #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) @@ -74,6 +82,7 @@ static
> uint64_t *alloc_sizes;  enum test_type {
>  	TYPE_ALL_SIZES,
>  	TYPE_RANDOM_SIZE,
> +	TYPE_ARRAY_BIND
>  };
> 
>  struct test_case {
> @@ -178,6 +187,28 @@ static void bo_alloc_reserve_va(struct bo_alloc *b,
> uint32_t flags, uint64_t va_
>  	igt_assert_eq_u64(b->gpu_va % align, 0);  }
> 
> +static int __xe_vm_bind_array(int fd, uint32_t vm,
> +			      struct drm_xe_vm_bind_op *bind_ops,
> +			      uint32_t num_bind, struct drm_xe_sync *sync,
> +			      uint32_t num_syncs)
> +{
> +	struct drm_xe_vm_bind bind = {
> +		.vm_id = vm,
> +		.num_binds = num_bind,
> +		.vector_of_binds = (uintptr_t)bind_ops,
> +		.num_syncs = num_syncs,
> +		.syncs = (uintptr_t)sync,
> +		.exec_queue_id = 0,
> +	};
> +
> +	igt_assert(num_bind > 0);
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind))
> +		return -errno;
> +
> +	return 0;
> +}
> +
>  static void alloc_sizes_init(void)
>  {
>  	int i;
> @@ -254,6 +285,7 @@ static void create_bo_arr(int fd, uint32_t vm, struct
> bo_alloc *bos,  int n_bos,
>  	}
>  }
> 
> +
>  /*
>   * BIND step: bind one or more BOs as a single array-of-binds ioctl call
>   * (see __xe_vm_bind_array() above), replacing the previous open-coded @@ -
> 308,8 +340,72 @@ static int test_bind_individual(int fd, uint32_t vm, struct
> bo_alloc *bos, int n
>  	return 0;
>  }
> 
> +static int test_bind_array(int fd, uint32_t vm,
> +			   struct bo_alloc *bos, int n_bos)
> +{
> +	struct drm_xe_vm_bind_op *bind_ops;
> +	struct drm_xe_sync sync = {
> +		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.handle = syncobj_create(fd, 0),
> +	};
> +	int i, ret;
> +
> +	igt_assert(n_bos > 0);
> +
> +	bind_ops = calloc(n_bos, sizeof(*bind_ops));
> +	igt_assert(bind_ops);
> +
> +	for (i = 0; i < n_bos; i++) {
> +		igt_assert_f(bos[i].bo,
> +			     "BO[%d] was not created before bind\n", i);
> +
> +		igt_assert_f(bos[i].bo_size,
> +			     "BO[%d] has zero size\n", i);
> +
> +		bind_ops[i] = (struct drm_xe_vm_bind_op) {
> +			.obj = bos[i].bo,
> +			.obj_offset = 0,
> +			.range = bos[i].bo_size,
> +			.addr = bos[i].gpu_va,
> +			.op = DRM_XE_VM_BIND_OP_MAP,
> +			.flags = 0,
> +		};
> +
> +		igt_debug("Bind op[%d]: bo=%u size=%#llx addr=%#llx\n",
> +			  i,
> +			  bos[i].bo,
> +			  (unsigned long long)bos[i].bo_size,
> +			  (unsigned long long)bos[i].gpu_va);
> +	}
> +
> +	ret = __xe_vm_bind_array(fd, vm, bind_ops, n_bos, &sync, 1);
> +	if (ret) {
> +		if (ret == -ENOMEM || ret == -ENOSPC) {
> +			syncobj_destroy(fd, sync.handle);
> +			free(bind_ops);
> +			return ret;
> +		}
> +
> +		igt_assert_f(false, "Array VM_BIND failed: ret=%d errno=%d
> (%s)\n",
> +			     ret, errno, strerror(errno));
> +	}
> +
> +	igt_assert_f(syncobj_wait(fd, &sync.handle, 1,
> +				  INT64_MAX, 0, NULL),
> +		     "Timed out waiting for array VM_BIND\n");
> +
> +	syncobj_destroy(fd, sync.handle);
> +	free(bind_ops);
> +
> +	return 0;
> +}
> +
>  static int test_bind(int fd, uint32_t vm, struct bo_alloc *bos, int n_bos, uint32_t
> flags)  {
> +	if (flags & ARRAY_BIND)
> +		return test_bind_array(fd, vm, bos, n_bos);
> +	else
>  		return test_bind_individual(fd, vm, bos, n_bos);  }
> 
> @@ -600,6 +696,76 @@ static void all_sizes_once(int fd, struct
> drm_xe_engine_class_instance *hwe)
>  	xe_vm_destroy(fd, vm);
>  }
> 
> +/*
> + * Same idea as alloc_rand_size_bos(), but each iteration binds
> +N_BOS_PER_BIND BOs
> + * together via a single array-of-binds call instead of one at a time.
> + * Used by the array-binds-* subtests, in particular the eviction
> +stress
> + * test where several BOs need to be resident (or evicted) as a unit.
> + */
> +#define N_BOS_PER_BIND	10
> +
> +static void alloc_random_size_bos_array_bind(int fd, struct
> drm_xe_engine_class_instance *hwe,
> +					     int count, uint64_t
> vram_per_process,
> +					     pthread_barrier_t *barrier, uint32_t
> flags,
> +					     unsigned int *seed)
> +{
> +	struct bo_group **leaks = NULL;
> +	uint32_t vm, exec_queue;
> +	uint64_t vram_used = 0;
> +	int i, max_batches = (count == -1) ? MAX_ALLOCATIONS : count;
> +	int n_batches = 0;
> +
> +	igt_debug("count=%d max_batches=%d vram_per_process=%llu
> flags=%x\n",
> +		  count, max_batches, (unsigned long long)vram_per_process,
> flags);
> +
> +	igt_assert(count > 0 || (flags & EVICT && flags & LEAK_BO));
> +
> +	leaks = malloc(sizeof(*leaks) * max_batches);
> +	igt_assert(leaks);
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	exec_queue =  xe_exec_queue_create(fd, vm, hwe, 0);
> +
> +	for (i = 0; i < count || vram_used < vram_per_process; ++i) {
> +		uint64_t sizes[N_BOS_PER_BIND];
> +		struct bo_alloc *bos;
> +		int j;
> +
> +		for (j = 0; j < N_BOS_PER_BIND; ++j)
> +			sizes[j] = alloc_sizes[rand_r(seed) % N_ALLOC_SIZES];
> +
> +		igt_assert_f(i < max_batches, "Failed to reach %llu bytes of
> VRAM pressure "
> +			     " after %d batches (currently reached %llu bytes)\n",
> +			     (unsigned long long)vram_per_process, max_batches,
> +			     (unsigned long long)vram_used);
> +
> +		bos = test_alloc_sizes(fd, vm, exec_queue, hwe->gt_id, sizes,
> +				       N_BOS_PER_BIND, flags,
> BO_BIND_BASE_ADDR);
> +		if (bos) {
> +			leaks[i] = malloc(sizeof(*leaks[i]));
> +			igt_assert(leaks[i]);
> +
> +			leaks[i]->bos = bos;
> +			leaks[i]->n_bos = N_BOS_PER_BIND;
> +			n_batches++;
> +
> +			for (j = 0; j < N_BOS_PER_BIND; ++j)
> +				vram_used += bos[j].bo_size;
> +		} else {
> +			leaks[i] = NULL;
> +		}
> +	}
> +
> +	if (barrier)
> +		pthread_barrier_wait(barrier);
> +
> +	check_leak_multi_group(fd, vm, leaks, n_batches, flags);

It should be i instead of n_batches as if it goes else case in one of the case then that is not counted.
check_leak_multi_group(fd, vm, leaks, i, flags);
> +
> +	xe_exec_queue_destroy(fd, exec_queue);
> +	xe_vm_destroy(fd, vm);
> +	free(leaks);
> +}
> +
>  static void run_gt_dynamic_subtests(int fd, const struct test_case *t)  {
>  	struct drm_xe_engine_class_instance *hwe; @@ -644,6 +810,13 @@
> static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
>  			case TYPE_RANDOM_SIZE:
>  				alloc_rand_size_bos(fd, hwe, t->count, 0, NULL,
> t->flags);
>  				break;
> +			case TYPE_ARRAY_BIND: {
> +				unsigned int seed = hwe->gt_id + 1;
> +
> +				alloc_random_size_bos_array_bind(fd, hwe, t-
> >count, 0, NULL,
> +								 t->flags,
> &seed);
> +				break;
> +			}
>  			default:
>  				break;
> 
> @@ -673,6 +846,9 @@ static const struct test_case test_matrix[] = {
>  	{ "rand-sizes-10", 10, 0, TYPE_RANDOM_SIZE, false },
>  	{ "rand-sizes-100", 100, 0, TYPE_RANDOM_SIZE, false },
>  	{ "rand-sizes-100-unaligned", 100, UNALIGNED, TYPE_RANDOM_SIZE,
> false },
> +	{ "array-binds-rand-sizes-10", 10, ARRAY_BIND, TYPE_ARRAY_BIND, true
> },
> +	{ "array-binds-rand-sizes-10-unaligned", 10,  ARRAY_BIND | UNALIGNED,
> TYPE_ARRAY_BIND,
> +	  true },
>  };
> 
>  int igt_main()
> @@ -690,6 +866,7 @@ int igt_main()
>  		switch (t->type) {
>  		case TYPE_ALL_SIZES:
>  		case TYPE_RANDOM_SIZE:
> +		case TYPE_ARRAY_BIND:
>  			igt_subtest_with_dynamic_f("%s", t->name)
>  				run_gt_dynamic_subtests(fd, t);
>  		}
> --
> 2.52.0

RE: [PATCH i-g-t v5 4/5] tests/intel: Add threaded random-size allocation stress tests

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Thomas, Sobin <sobin.thomas@intel.com>
> Sent: 22 September 2026 16:35
> To: igt-dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
> Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t v5 4/5] tests/intel: Add threaded random-size allocation
> stress tests
> 
> Add a new TYPE_THREAD test mode that creates a worker thread per available
> engine and performs random-sized BO allocations concurrently.
> 
> Each thread creates its own VM and execution queue and exercises the existing
> allocation path with both aligned and unaligned bind addresses.
> Additional variants cover leaked bindings.
> 
> These tests provide additional stress coverage for concurrent BO allocation and
> VM bind activity across multiple engines.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>  tests/intel/xe_bo_alloc.c | 149 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 148 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c index
> 343d07626..d8368087b 100644
> --- a/tests/intel/xe_bo_alloc.c
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -56,6 +56,26 @@
>   * Description: Test 10 batches of 10 random BO allocation sizes bound together
> as a single
>   * array of binds, unaligned bind addresses
>   * Test category: functionality test
> + *
> + *
> + * SUBTEST: threads-rand-sizes-50
> + * Description: Test 50 random bo allocation sizes in test table with a
> + thread per engine
> + * test category: stress test
> + *
> + * SUBTEST: threads-rand-sizes-50-unaligned
> + * Description: Test 50 random bo allocation sizes in test table with a
> + thread per engine,
> + * unaligned bind addresses
> + * test category: stress test
> + *
> + * SUBTEST: threads-leak-binding-rand-sizes-50
> + * Description: Test 50 random BO allocation sizes in test table with a
> + thread per engine,
> + * leak the binding
> + * Test category: stress test
> + *
> + * SUBTEST: threads-leak-binding-rand-sizes-50-unaligned
> + * Description: Test 50 random BO allocation sizes in test table with a
> + thread per engine,
> + * leak the binding, unaligned bind addresses
> + * Test category: stress test
>   */
> 
>  #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) @@ -82,7 +102,8 @@ static
> uint64_t *alloc_sizes;  enum test_type {
>  	TYPE_ALL_SIZES,
>  	TYPE_RANDOM_SIZE,
> -	TYPE_ARRAY_BIND
> +	TYPE_ARRAY_BIND,
> +	TYPE_THREAD
>  };
> 
>  struct test_case {
> @@ -129,6 +150,20 @@ struct batch_data {
>  	uint32_t data;
>  };
> 
> +struct thread_data {
> +	uint64_t va_base;
> +	pthread_t thread;
> +	pthread_mutex_t *mutex;
> +	pthread_cond_t *cond;
> +	struct drm_xe_engine_class_instance *hwe;
> +	int fd;
> +	int count;
> +	uint32_t vm;
> +	uint32_t flags;
> +	unsigned int seed;
seed variable is not used anywhere in this commit.
> +	bool *go;
> +};
> +
>  /*
>   * Reserve a chunk of process address space to use as the VM bind address
>   * for a BO, and hand back a pointer inside it aligned either to bo_size @@ -766,6
> +801,103 @@ static void alloc_random_size_bos_array_bind(int fd, struct
> drm_xe_engine_class_
>  	free(leaks);
>  }
> 
> +static void *bo_alloc_thread_fn(void *data) {
> +	struct thread_data *t = data;
> +	uint32_t q;
> +	int i;
> +
> +	igt_assert(!(t->flags & LEAK_BO));
> +
> +	pthread_mutex_lock(t->mutex);
> +	while (!*t->go)
> +		pthread_cond_wait(t->cond, t->mutex);
> +	pthread_mutex_unlock(t->mutex);
> +
> +	q =  xe_exec_queue_create(t->fd, t->vm, t->hwe, 0);
> +
> +	for (i = 0; i < t->count; ++i)
> +		test_alloc_size(t->fd, t->vm, q, t->hwe->gt_id,
> +				alloc_sizes[rand() % N_ALLOC_SIZES], here  rand_r(&t->seed) can be used instead of global rand()
> +				t->flags, t->va_base);
Same va_base is being. t->va_base is set once per thread and never advanced between the 50 iterations.
threads-rand-sizes-50 is fine as it binds and unbinds+releases after each iteration but for leak it might collide with previous one.
> +
> +	xe_exec_queue_destroy(t->fd, q);
> +
> +	return NULL;
> +}
> +
> +static void run_threaded_bo_alloc_test(int fd, int count, uint32_t
> +flags) {
> +	struct drm_xe_engine_class_instance *hwe;
> +	struct drm_xe_engine_class_instance **engines;
> +	struct thread_data *threads_data;
> +	pthread_mutex_t mutex;
> +	pthread_cond_t cond;
> +	bool begin_work = false;
> +	int n_found = 0, n_threads = 0, i, ret;
> +
> +	xe_for_each_engine(fd, hwe)
> +		n_found++;
> +
> +	igt_assert(n_found > 0);
> +
> +	engines = calloc(n_found, sizeof(*engines));
> +	igt_assert(engines);
> +
> +	i = 0;
> +	xe_for_each_engine(fd, hwe)
> +		engines[i++] = hwe;
> +
> +	threads_data = calloc(n_found, sizeof(*threads_data));
> +	igt_assert(threads_data);
> +
> +	pthread_mutex_init(&mutex, 0);
> +	pthread_cond_init(&cond, 0);
> +
> +	for (i = 0; i < n_found; ++i) {
> +		threads_data[i].mutex = &mutex;
> +		threads_data[i].cond = &cond;
> +		/* reuse engine 0 if only one exists */
> +		threads_data[i].hwe = engines[i % n_found];
Here i%n_found is not required just i is enough as both are same.
> +		threads_data[i].fd = fd;
> +		threads_data[i].count = count;
> +		threads_data[i].vm = xe_vm_create(fd, 0, 0);
> +		threads_data[i].flags = flags;
> +		threads_data[i].go = &begin_work;
> +		threads_data[i].seed = i + 1;
> +		threads_data[i].va_base = BO_BIND_BASE_ADDR + (uint64_t)i *
> THREAD_VA_STRIDE;
> +		ret = pthread_create(&threads_data[i].thread, 0,
> bo_alloc_thread_fn,
> +				     &threads_data[i]);
> +		if (ret)
> +			break;
> +		n_threads++;
> +	}
> +
> +	ret = pthread_mutex_lock(&mutex);
> +	igt_assert_eq(ret, 0);
> +	begin_work = true;
> +	ret = pthread_cond_broadcast(&cond);
> +	igt_assert_eq(ret, 0);
> +	ret = pthread_mutex_unlock(&mutex);
> +	igt_assert_eq(ret, 0);
> +
> +	for (i = 0; i < n_threads; ++i) {
> +		ret = pthread_join(threads_data[i].thread, NULL);
> +		igt_assert_eq(ret, 0);
> +	}
> +
> +	/* vm is created for every slot up to n_found regardless of thread
> creation success */
> +	for (i = 0; i < n_found; ++i)
> +		xe_vm_destroy(fd, threads_data[i].vm);
> +
> +	ret = pthread_cond_destroy(&cond);
> +	igt_assert_eq(ret, 0);
> +	ret = pthread_mutex_destroy(&mutex);
> +	igt_assert_eq(ret, 0);
> +	free(threads_data);
> +	free(engines);
> +}
> +
>  static void run_gt_dynamic_subtests(int fd, const struct test_case *t)  {
>  	struct drm_xe_engine_class_instance *hwe; @@ -849,6 +981,11 @@
> static const struct test_case test_matrix[] = {
>  	{ "array-binds-rand-sizes-10", 10, ARRAY_BIND, TYPE_ARRAY_BIND, true
> },
>  	{ "array-binds-rand-sizes-10-unaligned", 10,  ARRAY_BIND | UNALIGNED,
> TYPE_ARRAY_BIND,
>  	  true },
> +	{ "threads-rand-sizes-50", 50, 0, TYPE_THREAD, false },
> +	{ "threads-rand-sizes-50-unaligned", 50, UNALIGNED, TYPE_THREAD,
> false },
> +	{ "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING,
> TYPE_THREAD, false },
> +	{ "threads-leak-binding-rand-sizes-50-unaligned", 50, LEAK_BINDING |
> UNALIGNED,
> +	  TYPE_THREAD, false },
>  };
> 
>  int igt_main()
> @@ -864,6 +1001,16 @@ int igt_main()
>  		const struct test_case *t = &test_matrix[i];
> 
>  		switch (t->type) {
> +		case TYPE_THREAD:
> +			igt_subtest_f("%s", t->name) {
> +				if (t->requires_evict_ram) {
> +					igt_require(xe_has_vram(fd));
> +					igt_require(igt_get_avail_ram_mb() >=
> +						    (xe_visible_vram_size(fd, 0)
> >> 20) / 2);
> +				}
> +				run_threaded_bo_alloc_test(fd, t->count, t-
> >flags);
> +			}
> +			break;
>  		case TYPE_ALL_SIZES:
>  		case TYPE_RANDOM_SIZE:
>  		case TYPE_ARRAY_BIND:
> --
> 2.52.0

Re: [PATCH i-g-t v5 5/5] tests/intel: Add oversubscribe concurrent bind stress subtest

[Sharma, Nishit]

On 9/22/2026 4:34 PM, Sobin Thomas wrote:
> Add test for oversubscribing VRAM in multi process environment that
> creates VM, bind large BOs and submit workloads nearly simultaneously.
>
> Previous coverage lacked a scenario combining multi-process bind
> with VRAM oversubscription. This generates memory pressure with
> multi-process VM Bind activity and concurrent submission, exercising
> the bind pipeline under eviction pressure.
>
> v3: Fixed minor nits
> v4: Refactoring of the create_bo ( Nishit)
>      Fix child process exit deadlock in release_ready_processes() (Nishit)
>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>   tests/intel/xe_bo_alloc.c | 533 +++++++++++++++++++++++++++++++++++++-
>   1 file changed, 532 insertions(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
> index d8368087b..2ee468c62 100644
> --- a/tests/intel/xe_bo_alloc.c
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -29,6 +29,17 @@
>   #define THREAD_VA_STRIDE GB(1)
>   #define SZ_4K_SHIFT	12
>   #define MAX_ALLOCATIONS 50000
> +#define INT_ADD_CNT 4
> +#define TIMEOUT_NS (30ULL * 1000000000ULL)
> +#define MAX_SRAM_TEST_SIZE GB(32)
> +#define GPR_RX_ADDR(x)          (0x600 + (x) * 8)
> +#define MAX_PROCS 20
> +
> +#define EXEC_DATA_ADDR		0x100000ULL
> +#define EXEC_RESULT_ADDR	0x200000ULL
> +#define EXEC_BATCH_ADDR		0x300000ULL
> +#define EXEC_UFENCE_ADDR	0x400000ULL
> +#define STRESS_BIND_ADDR	0x40000000ULL
>   
>   /**
>    * SUBTEST: all-sizes-once
> @@ -76,14 +87,48 @@
>    * Description: Test 50 random BO allocation sizes in test table with a thread per engine,
>    * leak the binding, unaligned bind addresses
>    * Test category: stress test
> + *
> + * SUBTEST: test_vm_oversubscribe_concurrent_bind
> + * Description: Test enough random BO allocation sizes, bound as arrays of binds, to trigger
> + * evictions with 2 processes per engine, leak the BO munmap / gem close, unaligned bind addresses
> + * Test category: stress test
>    */
>   
>   #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
>   #define MIN_BUFS_PER_PROC 2
>   
>   #define N_ALLOC_SIZES	256
> +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
> +
>   static uint64_t *alloc_sizes;
>   
> +struct gem_bo {
> +	uint32_t handle;
> +	uint64_t size;
> +	uint32_t *ptr;
> +	uint64_t addr;
> +};
> +
> +struct xe_oversubscribe_ctx {
> +	uint32_t vm_id;
> +	uint32_t exec_queue_id;
> +};
> +
> +struct mem_bind_sync {
> +	struct gem_bo *bufs;
> +	int n_bufs;
> +	uint64_t *binds_ufence;
> +};
> +
> +struct process_data {
> +	pthread_mutex_t mutex;
> +	pthread_cond_t cond;
> +	int ready;
> +	int failed;
> +	pthread_barrier_t barrier;
barrier not initialized but used. I think it's not required
> +	bool go;
> +};
> +
>   /*
>    * Data-driven subtest matrix.
>    *
> @@ -103,7 +148,8 @@ enum test_type {
>   	TYPE_ALL_SIZES,
>   	TYPE_RANDOM_SIZE,
>   	TYPE_ARRAY_BIND,
> -	TYPE_THREAD
> +	TYPE_THREAD,
> +	TYPE_OVERSUBSCRIBE,
>   };
>   
>   struct test_case {
> @@ -114,6 +160,14 @@ struct test_case {
>   	bool requires_evict_ram;
>   };
>   
> +struct oversubscribe_params {
> +	int n_proc;
> +	int n_vram_bufs;
> +	int n_sram_bufs;
> +	uint64_t vram_size;
> +	uint64_t sram_size;
> +	uint64_t total_vram_demand;
> +};
>   #define LEAK_BINDING		(0x1 << 0)
>   #define LEAK_BO			(0x1 << 1)
>   #define EVICT			(0x1 << 2)
> @@ -244,6 +298,478 @@ static int __xe_vm_bind_array(int fd, uint32_t vm,
>   	return 0;
>   }
>   
> +static void init_pdata(struct process_data *pdata)
> +{
> +	pthread_mutexattr_t mattr;
> +	pthread_condattr_t cattr;
> +
> +	pthread_mutexattr_init(&mattr);
> +	igt_assert_eq(pthread_mutexattr_setpshared(&mattr, PTHREAD_PROCESS_SHARED), 0);
> +	igt_assert_eq(pthread_mutexattr_setrobust(&mattr, PTHREAD_MUTEX_ROBUST), 0);
> +	igt_assert_eq(pthread_mutex_init(&pdata->mutex, &mattr), 0);
> +	pthread_mutexattr_destroy(&mattr);
> +
> +	pthread_condattr_init(&cattr);
> +	igt_assert_eq(pthread_condattr_setpshared(&cattr, PTHREAD_PROCESS_SHARED), 0);
> +	igt_assert_eq(pthread_cond_init(&pdata->cond, &cattr), 0);
> +	pthread_condattr_destroy(&cattr);
> +	pdata->ready = 0;
> +	pdata->failed = 0;
> +	pdata->go = false;
> +}
> +
> +static void process_ready_and_wait(struct process_data *pdata)
> +{
> +	int ret = pthread_mutex_lock(&pdata->mutex);
> +
> +	if (ret == EOWNERDEAD)
> +		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
> +	else
> +		igt_assert_eq(ret, 0);
> +	pdata->ready++;
> +	pthread_cond_broadcast(&pdata->cond);
> +	while (!pdata->go)
> +		pthread_cond_wait(&pdata->cond, &pdata->mutex);
> +	pthread_mutex_unlock(&pdata->mutex);
> +}
> +
> +static void process_setup_failed(struct process_data *pdata)
> +{
> +	int ret = pthread_mutex_lock(&pdata->mutex);
> +
> +	if (ret == EOWNERDEAD)
> +		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
> +	else
> +		igt_assert_eq(ret, 0);
> +	pdata->failed++;
> +	pthread_cond_broadcast(&pdata->cond);
> +	pthread_mutex_unlock(&pdata->mutex);
> +}
> +
> +static void release_ready_processes(struct process_data *pdata, int n_proc)
> +{
> +	struct timespec timeout;
> +	int ret;
> +
> +	ret = pthread_mutex_lock(&pdata->mutex);
> +	if (ret == EOWNERDEAD)
> +		igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
> +	else
> +		igt_assert_eq(ret, 0);
> +
> +	clock_gettime(CLOCK_REALTIME, &timeout);
> +	timeout.tv_sec += 30;
> +	/*
> +	 * Wait until all children have either reached VM Bind rendevouz
> +	 * Or, failed setup and exited the test path.
> +	 */
> +	while (pdata->ready + pdata->failed < n_proc) {
> +		ret = pthread_cond_timedwait(&pdata->cond, &pdata->mutex, &timeout);
> +		if (ret == EOWNERDEAD) {
> +			igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);

If pthread_cond_timedwait() returned EOWNERDEAD (a lock holder died) 
code made the mutex consistent

but it is checking igt_assert_eq(ret, 0) which will fail as ret is still 
EOWNERDEAD, so in case of EOWNERDEAD it should continue to check

ret    if (ret == EOWNERDEAD) {

igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);

continue;                 /* re-check loop condition */

}

> +		} else if (ret == ETIMEDOUT) {
> +			igt_warn("Timeout waiting for the child process: ready=%d, failed =%d, expected=%d",
> +			pdata->ready, pdata->failed, n_proc);
> +			break;
> +		}
> +		igt_assert_eq(ret, 0);
> +	}
> +
> +	igt_debug("Process rendezvous: ready=%d failed=%d total = %d\n",
> +		  pdata->ready, pdata->failed, n_proc);
> +
> +	/* Release every successful child into VM_Bind at same time*/
> +	pdata->go = true;
> +	pthread_cond_broadcast(&pdata->cond);
> +	pthread_mutex_unlock(&pdata->mutex);
> +}
> +
> +static int build_add_batch(struct gem_bo *batch_bo, struct gem_bo *integers_bo,
> +			   struct gem_bo *result_bo, int ints_to_add)
> +{
> +	int pos = 0;
> +	int i;
> +	uint64_t tmp_addr;
> +
> +	batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | MI_LRI_LRM_CS_MMIO | 2;
> +	batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
> +	tmp_addr = integers_bo->addr + 0 * sizeof(uint32_t);
> +	batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
> +	batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
> +	for (i = 1; i < ints_to_add; i++) {
> +		/* r1 = integers_bo[i] */
> +		batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | MI_LRI_LRM_CS_MMIO | 2;
> +		batch_bo->ptr[pos++] = GPR_RX_ADDR(1);
> +		tmp_addr = integers_bo->addr + i * sizeof(uint32_t);
> +		batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
> +		batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
> +		/* r0 = r0 + r1 */
> +		batch_bo->ptr[pos++] = MI_MATH(4);
> +		batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(0));
> +		batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(1));
> +		batch_bo->ptr[pos++] = MI_MATH_ADD;
> +		batch_bo->ptr[pos++] = MI_MATH_STORE(MI_MATH_REG(0), MI_MATH_REG_ACCU);
> +	}
> +	/* result_bo[0] = r0 */
> +	batch_bo->ptr[pos++] = MI_STORE_REGISTER_MEM_GEN8 | MI_LRI_LRM_CS_MMIO;
> +	batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
> +	tmp_addr = result_bo->addr + 0 * sizeof(uint32_t);
> +	batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
> +	batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
> +
> +	batch_bo->ptr[pos++] = MI_BATCH_BUFFER_END;
> +	while (pos % 4 != 0)
> +		batch_bo->ptr[pos++] = MI_NOOP;
> +	return pos;
> +}
> +
> +static void create_exec_queue(int fd, struct xe_oversubscribe_ctx *ctx)
> +{
> +	ctx->exec_queue_id = xe_exec_queue_create(fd, ctx->vm_id,
> +						  &xe_engine(fd, 0)->instance, 0);
> +}
> +
> +static uint64_t *
> +vm_bind_bo_batch(int fd, struct xe_oversubscribe_ctx *ctx, struct gem_bo *bos, int size,
> +		 int *out_err)
> +{
> +	uint64_t *ufence;
> +	struct drm_xe_sync bind_sync;
> +	struct drm_xe_vm_bind_op *binds;
> +	int i;
> +
> +	binds = calloc(size, sizeof(*binds));
> +	igt_assert(binds);
> +
> +	ufence = calloc(1, sizeof(*ufence));
> +	igt_assert(ufence);
> +	bind_sync = (struct drm_xe_sync) {
> +		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.addr = to_user_pointer(ufence),
> +		.timeline_value = 1,
> +	};
> +
> +	for (i = 0; i < size; i++) {
> +		binds[i] = (struct drm_xe_vm_bind_op) {
> +			.obj = bos[i].handle,
> +			.obj_offset = 0,
> +			.range = bos[i].size,
> +			.addr = bos[i].addr,
> +			.op = DRM_XE_VM_BIND_OP_MAP,
> +			.flags = 0,
> +		};
> +	}
> +	*out_err = __xe_vm_bind_array(fd, ctx->vm_id, binds, size, &bind_sync, 1);
> +	free(binds);
> +	return ufence;
> +}
> +
> +/* Returns 1 (caller should skip exec) on an allowed OOM error, 0 otherwise. */
> +static int bind_bos(int fd, struct xe_oversubscribe_ctx *ctx, struct gem_bo *bufs,
> +		    struct mem_bind_sync *bind, int *bind_err, bool allow_oom)
> +{
> +	if (!bind->n_bufs)
> +		return 0;
> +
> +	bind->binds_ufence = vm_bind_bo_batch(fd, ctx, bufs, bind->n_bufs, bind_err);
> +
> +	if (*bind_err) {
> +		if (allow_oom) {
> +			igt_assert_f(*bind_err == -ENOMEM || *bind_err == -ENOSPC,
> +				     "Unexpected bind error: %d (%s)\n",
> +				     *bind_err, strerror(-*bind_err));
> +			igt_debug("Bind failed with expected OOM (%s), skipping exec\n",
> +				  strerror(-*bind_err));
> +			return 1;
> +		}
> +
> +		igt_assert_f(false, "Unexpected bind error: %d", *bind_err);
> +	}
> +
> +	xe_wait_ufence(fd, bind->binds_ufence, 1, 0, TIMEOUT_NS);
> +	return 0;
> +}
> +
> +static int fill_random_integers(struct gem_bo *int_bo, int ints_to_add)
> +{
> +	uint32_t expected_result = 0;
> +	char expr[256];
> +	int len = 0;
> +
> +	for (int i = 0; i < ints_to_add; i++) {
> +		uint32_t random_int = rand() % 8;
> +
> +		int_bo->ptr[i] = random_int;
> +		expected_result += random_int;
> +
> +		len += snprintf(expr + len, sizeof(expr) - len, "%s%u",
> +				i ? " + " : "", random_int);
> +	}
> +	igt_debug("%s = %u\n", expr, expected_result);
> +	return expected_result;
> +}
> +
> +static void cleanup_bo_resources(int fd, struct gem_bo *bo)
> +{
> +	if (bo->ptr) {
> +		igt_assert_eq(munmap(bo->ptr, bo->size), 0);
> +		bo->ptr = NULL;
> +	}
> +	if (bo->handle)
> +		gem_close(fd, bo->handle);
> +}
> +
> +static int create_test_bos(int fd, struct xe_oversubscribe_ctx *ctx,
> +			   struct mem_bind_sync *bind, uint32_t placement,
> +			   uint64_t *addr)
> +{
> +	const char *mem_type = (placement & vram_memory(fd, 0)) ? "VRAM" : "SRAM";
> +	int ret;
> +
> +	for (int i = 0; i < bind->n_bufs; i++) {
> +		struct gem_bo *bo = &bind->bufs[i];
> +
> +		bo->size = GB(1);
> +		ret = __xe_bo_create_caching(fd, ctx->vm_id, bo->size, placement, 0,
> +					     DRM_XE_GEM_CPU_CACHING_WC, &bo->handle);
> +		if (ret) {
> +			int saved_errno = errno; /* capture before anything can clobber it */
> +
> +			bind->n_bufs = i;
> +			if (saved_errno == ENOMEM || saved_errno == ENOSPC) {
> +				/* Continue on OOM, expected when oversubscribing the VM */
> +				igt_debug("%s allocation failed at buffer %d (OOM)\n", mem_type, i);
> +				break;
> +			}
> +			/* We are returning as this is a fail scenario */
> +			igt_warn("%s allocation failed at buffer %d: %s\n",
> +				 mem_type, i, strerror(saved_errno));
> +			return -saved_errno;
> +		}
> +		bo->ptr = NULL;
> +		bo->addr = *addr;
> +		*addr += bo->size;
> +		igt_debug("%s buffer %d created at 0x%016lx\n", mem_type, i, bo->addr);
> +	}
> +	return 0;
> +}
> +
> +static void cleanup_sram_vram_objs(int fd, struct mem_bind_sync *vram_bind,
> +				   struct mem_bind_sync *sram_bind)
> +{
> +	for (int i = 0; i < vram_bind->n_bufs; i++)
> +		gem_close(fd, vram_bind->bufs[i].handle);
> +	for (int i = 0; i < sram_bind->n_bufs; i++)
> +		gem_close(fd, sram_bind->bufs[i].handle);
> +	free(vram_bind->bufs);
> +	free(sram_bind->bufs);
> +	if (vram_bind->binds_ufence)
> +		free(vram_bind->binds_ufence);
> +	if (sram_bind->binds_ufence)
> +		free(sram_bind->binds_ufence);
> +}
> +
> +static void create_bo(int fd, uint32_t vm, struct gem_bo *bo, uint64_t size,
> +		      uint64_t addr, bool map_now)
> +{
> +	bo->size = ALIGN(size, 4096);
> +	bo->handle = xe_bo_create_caching(fd, vm, bo->size, system_memory(fd), 0,
> +					  DRM_XE_GEM_CPU_CACHING_WC);
> +	igt_assert(bo->handle);
> +	bo->addr = addr;
> +	if (map_now) {
> +		bo->ptr = xe_bo_map(fd, bo->handle, bo->size);
> +		igt_assert(bo->ptr != MAP_FAILED);
> +	} else {
> +		bo->ptr = NULL;
> +	}
> +}
> +
> +static bool calc_oversubscribe_params(int fd, struct oversubscribe_params *p)
> +{
> +	uint64_t target_vram, target_sram;
> +	uint64_t total_vram_bufs, total_sram_bufs, max_by_mem;
> +
> +	p->vram_size =  xe_visible_available_vram_size(fd, 0);

Sizing used xe_visible_available_vram_size() gives 
vram.cpu_visible_available; which can be small

to accomodate big BOs or 2x demand, it should be xe_available_vram_size 
which gives vram.total_available;

> +	p->sram_size = (uint64_t)igt_get_avail_ram_mb() << 20;
> +	/*
> +	 * Dynamically cap VRAM oversubscription so the overflow into system
> +	 * RAM stays within 25% of available RAM. On small-VRAM platforms
> +	 * the 2x target fits within the cap and behavior is
> +	 * unchanged; on large-VRAM platforms (e.g. PVC) this prevents OOM.
> +	 */
> +
> +	target_vram = min(p->vram_size * 2, p->vram_size + p->sram_size / 4);
> +	target_sram = min_t(uint64_t, p->sram_size * 50 / 100,
> +			    MAX_SRAM_TEST_SIZE);
> +	total_vram_bufs = target_vram / GB(1);
> +	total_sram_bufs = target_sram / GB(1);
> +	max_by_mem = min(total_vram_bufs / MIN_BUFS_PER_PROC,
> +			 total_sram_bufs / MIN_BUFS_PER_PROC);
> +
> +	p->n_proc = min_t(int, max_by_mem, MAX_PROCS);
> +	if (p->n_proc <= 0)

On low ram machines it might execute single-process but above in 
description mentioned 2 process, so

condition p->n_proc < 2 should be checked.

> +		return false;
> +	p->n_vram_bufs = max_t(int, 2, total_vram_bufs / p->n_proc);
> +	p->n_sram_bufs = max_t(int, 2, total_sram_bufs / p->n_proc);
> +	p->total_vram_demand = (uint64_t)p->n_proc * p->n_vram_bufs * GB(1);
> +	return true;
> +}
> +
> +static void test_vm_oversubscribe_concurrent_bind(int fd)
> +{
> +	struct oversubscribe_params p;
> +	struct process_data *pdata;
> +
> +	igt_require_f(calc_oversubscribe_params(fd, &p),
> +		      "Not enough VRAM/RAM for oversubscription test\n");
> +
> +	igt_debug("VRAM size: %" PRIu64 "MB, System RAM available: %" PRIu64 "MB\n",
> +		  p.vram_size >> 20, p.sram_size >> 20);
> +
> +	igt_debug("n_proc = %d\n", p.n_proc);
> +	igt_debug("VRAM: %" PRIu64 "GB\n", p.vram_size >> 30);
> +	igt_debug("VRAM demand: %" PRIu64 "MB (%.2fx oversubscription)\n",
> +		  p.total_vram_demand >> 20, (double)p.total_vram_demand / p.vram_size);
> +	igt_debug("Processes=%d VRAM_bufs=%d SRAM_bufs=%d\n", p.n_proc,
> +		  p.n_vram_bufs, p.n_sram_bufs);
> +
> +	pdata = mmap(NULL, sizeof(*pdata), PROT_READ | PROT_WRITE,
> +		     MAP_SHARED | MAP_ANONYMOUS, -1, 0);
> +	igt_assert(pdata != MAP_FAILED);
> +	init_pdata(pdata);
> +
> +	igt_fork(child, p.n_proc) {
> +		struct xe_oversubscribe_ctx ctx = {0};
> +		int rc, ret, fd_c;
> +		uint64_t addr = STRESS_BIND_ADDR;
> +		uint32_t expected_result = 0;
> +		struct gem_bo integers_bo = {0}, result_bo = {0}, batch_bo = {0};
> +		struct gem_bo *vram_bufs, *sram_bufs;
> +		int pos = 0;
> +		struct mem_bind_sync vram_bind = {0};
> +		struct mem_bind_sync sram_bind = {0};
> +		struct drm_xe_sync batch_syncs[1];
> +		struct drm_xe_exec exec;
> +		struct gem_bo ufence_bo = {0};
> +		int vram_bind_err = 0, sram_bind_err = 0;
> +
> +		vram_bufs = calloc(p.n_vram_bufs, sizeof(*vram_bufs));
> +		sram_bufs = calloc(p.n_sram_bufs, sizeof(*sram_bufs));
> +		srand(child);
> +
> +		fd_c = drm_open_driver(DRIVER_XE);
> +
> +		igt_assert(vram_bufs && sram_bufs);
> +
> +		ctx.vm_id = xe_vm_create(fd_c, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0);
> +		create_exec_queue(fd_c, &ctx);
> +		vram_bind.bufs = vram_bufs;
> +		vram_bind.n_bufs = p.n_vram_bufs;
> +		sram_bind.bufs = sram_bufs;
> +		sram_bind.n_bufs = p.n_sram_bufs;
> +
> +		ret = create_test_bos(fd_c, &ctx, &vram_bind, vram_memory(fd_c, 0), &addr);
> +		if (ret) {
> +			process_setup_failed(pdata);
> +			goto cleanup;
> +		}
> +
> +		ret = create_test_bos(fd_c, &ctx, &sram_bind, system_memory(fd_c), &addr);
> +		if (ret) {
> +			process_setup_failed(pdata);
> +			goto cleanup;
> +		}
> +
> +		if (!vram_bind.n_bufs || !sram_bind.n_bufs) {
> +			igt_debug("No BOs allocated; VRAM/SRAM unavailable, skipping\n");
> +			process_setup_failed(pdata);
> +			goto cleanup;
> +		}

When a child hit an allocation failure it called process_setup_failed(), 
jumped to cleanup, and exited normally (status 0).

The parent only waited for children to exit — it never checked whether 
any test executed. So a run where every child failed

still it'll be reported as PASS. Instead a counter e.g. failed_count 
should be incremented in process_setup_failed() and after cleanup:

failed_count value must be checked so that user knows during setup/bo 
creation fault happened

something like: igt_assert_f(pdata->fault_count == 0,
              "%d child(ren) hit unexpected setup errors\n", 
pdata->fault_count);

> +
> +		/*
> +		 * All allocations are complete. Report Ready and wait until every
> +		 * child has either reached this point or repported a setup failure.
> +		 */
> +
> +		 process_ready_and_wait(pdata);
> +
> +		/*
> +		 * VM_Bind starts only after the parent releases all ready
> +		 * childen.
> +		 */
> +
> +		if (bind_bos(fd_c, &ctx, vram_bufs, &vram_bind, &vram_bind_err, true))
> +			goto cleanup;
> +
> +		if (bind_bos(fd_c, &ctx, sram_bufs, &sram_bind, &sram_bind_err, false))
> +			goto cleanup;
> +
> +		create_bo(fd_c, ctx.vm_id, &integers_bo, 4096, EXEC_DATA_ADDR, true);
> +		expected_result = fill_random_integers(&integers_bo, INT_ADD_CNT);
> +		igt_debug("%d\n", expected_result);
> +		create_bo(fd_c, ctx.vm_id, &result_bo, 4096, EXEC_RESULT_ADDR, false);
> +		create_bo(fd_c, ctx.vm_id, &batch_bo, 4096, EXEC_BATCH_ADDR, true);
> +		pos = build_add_batch(&batch_bo, &integers_bo, &result_bo, INT_ADD_CNT);
> +
> +		igt_assert(pos * sizeof(int) <= batch_bo.size);
> +
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, integers_bo.handle, 0, integers_bo.addr,
> +				   integers_bo.size, 0);
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, result_bo.handle, 0, result_bo.addr,
> +				   result_bo.size, 0);
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, batch_bo.handle, 0, batch_bo.addr,
> +				   batch_bo.size, 0);
> +		create_bo(fd_c, ctx.vm_id, &ufence_bo, 4096, EXEC_UFENCE_ADDR, true);
> +
> +		memset(ufence_bo.ptr, 0, ufence_bo.size);
> +		xe_vm_bind_lr_sync(fd_c, ctx.vm_id, ufence_bo.handle, 0, ufence_bo.addr,
> +				   ufence_bo.size, 0);
> +
> +		batch_syncs[0] = (struct drm_xe_sync){
> +			.type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +			.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +			.addr = ufence_bo.addr,
> +			.timeline_value = USER_FENCE_VALUE,
> +		};
> +
> +		exec = (struct drm_xe_exec) {
> +			.exec_queue_id = ctx.exec_queue_id,
> +			.num_syncs = 1,
> +			.syncs = (uintptr_t)batch_syncs,
> +			.address = batch_bo.addr,
> +			.num_batch_buffer = 1,
> +		};
> +
> +		rc = igt_ioctl(fd_c, DRM_IOCTL_XE_EXEC, &exec);
> +		igt_assert_f(rc == 0, "xe_exec failed unexpectedly: %s (%d)\n",
> +			     strerror(errno), errno);
> +		xe_wait_ufence(fd_c, (uint64_t *)ufence_bo.ptr, USER_FENCE_VALUE, ctx.exec_queue_id,
> +			       TIMEOUT_NS);
> +		result_bo.ptr = xe_bo_map(fd_c, result_bo.handle, result_bo.size);
> +		igt_assert(result_bo.ptr != MAP_FAILED);
> +		igt_assert_eq(result_bo.ptr[0], expected_result);
Here child should report completion also, something like 
child_completion(pdata) { pdata->child_completed++;}
> +cleanup:
> +		cleanup_bo_resources(fd_c, &ufence_bo);
> +		cleanup_bo_resources(fd_c, &result_bo);
> +		cleanup_bo_resources(fd_c, &batch_bo);
> +		cleanup_bo_resources(fd_c, &integers_bo);
> +		cleanup_sram_vram_objs(fd_c, &vram_bind, &sram_bind);
> +		xe_exec_queue_destroy(fd_c, ctx.exec_queue_id);
> +		xe_vm_destroy(fd_c, ctx.vm_id);
> +		drm_close_driver(fd_c);
> +	}
> +
> +	release_ready_processes(pdata, p.n_proc);
> +	igt_waitchildren();

If a child is killed or blocked before reporting, the parent timed out 
after 30 s,

it releases the rest and calls igt_waitchildren() which could wait 
forever/hung. Here all forked children

should be killed first.

Both counters updated above will be checked in assertion to know the 
real cause of error

igt_assert_f(pdata->fault_count == 0,
              "%d child(ren) hit unexpected setup errors\n", 
pdata->fault_count);
igt_assert_f(pdata->child_completed >= 2,
              "Need >=2 processes to complete the oversubscribed submit, 
got %d\n",
              pdata->child_completed);

> +	igt_reset_timeout();
> +
> +	pthread_cond_destroy(&pdata->cond);
> +	pthread_mutex_destroy(&pdata->mutex);
> +	igt_assert_eq(munmap(pdata, sizeof(*pdata)), 0);
> +}
> +
>   static void alloc_sizes_init(void)
>   {
>   	int i;
> @@ -986,6 +1512,7 @@ static const struct test_case test_matrix[] = {
>   	{ "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING, TYPE_THREAD, false },
>   	{ "threads-leak-binding-rand-sizes-50-unaligned", 50, LEAK_BINDING | UNALIGNED,
>   	  TYPE_THREAD, false },
> +	{ "test_vm_oversubscribe_concurrent_bind", 0, 0, TYPE_OVERSUBSCRIBE, false},
>   };
>   
>   int igt_main()
> @@ -1011,6 +1538,10 @@ int igt_main()
>   				run_threaded_bo_alloc_test(fd, t->count, t->flags);
>   			}
>   			break;
> +		case TYPE_OVERSUBSCRIBE:
> +			igt_subtest_f("%s", t->name)
> +				test_vm_oversubscribe_concurrent_bind(fd);
> +			break;
>   		case TYPE_ALL_SIZES:
>   		case TYPE_RANDOM_SIZE:
>   		case TYPE_ARRAY_BIND:

Re: [PATCH i-g-t v5 5/5] tests/intel: Add oversubscribe concurrent bind stress subtest

[Thomas, Sobin]

[-- Attachment #1: Type: text/plain, Size: 29605 bytes --]

Hi Nishit,


Thanks for review  , Most of the changes will be taken care, please find 
inline response.


>> Add test for oversubscribing VRAM in multi process environment that
>> creates VM, bind large BOs and submit workloads nearly simultaneously.
>>
>> Previous coverage lacked a scenario combining multi-process bind
>> with VRAM oversubscription. This generates memory pressure with
>> multi-process VM Bind activity and concurrent submission, exercising
>> the bind pipeline under eviction pressure.
>>
>> v3: Fixed minor nits
>> v4: Refactoring of the create_bo ( Nishit)
>>      Fix child process exit deadlock in release_ready_processes() 
>> (Nishit)
>>
>> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
>> ---
>>   tests/intel/xe_bo_alloc.c | 533 +++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 532 insertions(+), 1 deletion(-)
>>
>> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c
>> index d8368087b..2ee468c62 100644
>> --- a/tests/intel/xe_bo_alloc.c
>> +++ b/tests/intel/xe_bo_alloc.c
>> @@ -29,6 +29,17 @@
>>   #define THREAD_VA_STRIDE GB(1)
>>   #define SZ_4K_SHIFT    12
>>   #define MAX_ALLOCATIONS 50000
>> +#define INT_ADD_CNT 4
>> +#define TIMEOUT_NS (30ULL * 1000000000ULL)
>> +#define MAX_SRAM_TEST_SIZE GB(32)
>> +#define GPR_RX_ADDR(x)          (0x600 + (x) * 8)
>> +#define MAX_PROCS 20
>> +
>> +#define EXEC_DATA_ADDR        0x100000ULL
>> +#define EXEC_RESULT_ADDR    0x200000ULL
>> +#define EXEC_BATCH_ADDR        0x300000ULL
>> +#define EXEC_UFENCE_ADDR    0x400000ULL
>> +#define STRESS_BIND_ADDR    0x40000000ULL
>>     /**
>>    * SUBTEST: all-sizes-once
>> @@ -76,14 +87,48 @@
>>    * Description: Test 50 random BO allocation sizes in test table 
>> with a thread per engine,
>>    * leak the binding, unaligned bind addresses
>>    * Test category: stress test
>> + *
>> + * SUBTEST: test_vm_oversubscribe_concurrent_bind
>> + * Description: Test enough random BO allocation sizes, bound as 
>> arrays of binds, to trigger
>> + * evictions with 2 processes per engine, leak the BO munmap / gem 
>> close, unaligned bind addresses
>> + * Test category: stress test
>>    */
>>     #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x))
>>   #define MIN_BUFS_PER_PROC 2
>>     #define N_ALLOC_SIZES    256
>> +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
>> +
>>   static uint64_t *alloc_sizes;
>>   +struct gem_bo {
>> +    uint32_t handle;
>> +    uint64_t size;
>> +    uint32_t *ptr;
>> +    uint64_t addr;
>> +};
>> +
>> +struct xe_oversubscribe_ctx {
>> +    uint32_t vm_id;
>> +    uint32_t exec_queue_id;
>> +};
>> +
>> +struct mem_bind_sync {
>> +    struct gem_bo *bufs;
>> +    int n_bufs;
>> +    uint64_t *binds_ufence;
>> +};
>> +
>> +struct process_data {
>> +    pthread_mutex_t mutex;
>> +    pthread_cond_t cond;
>> +    int ready;
>> +    int failed;
>> +    pthread_barrier_t barrier;
> barrier not initialized but used. I think it's not required


Agreed. This was missed, was part of  earlier patches in thread part. missed

>> +    bool go;
>> +};
>> +
>>   /*
>>    * Data-driven subtest matrix.
>>    *
>> @@ -103,7 +148,8 @@ enum test_type {
>>       TYPE_ALL_SIZES,
>>       TYPE_RANDOM_SIZE,
>>       TYPE_ARRAY_BIND,
>> -    TYPE_THREAD
>> +    TYPE_THREAD,
>> +    TYPE_OVERSUBSCRIBE,
>>   };
>>     struct test_case {
>> @@ -114,6 +160,14 @@ struct test_case {
>>       bool requires_evict_ram;
>>   };
>>   +struct oversubscribe_params {
>> +    int n_proc;
>> +    int n_vram_bufs;
>> +    int n_sram_bufs;
>> +    uint64_t vram_size;
>> +    uint64_t sram_size;
>> +    uint64_t total_vram_demand;
>> +};
>>   #define LEAK_BINDING        (0x1 << 0)
>>   #define LEAK_BO            (0x1 << 1)
>>   #define EVICT            (0x1 << 2)
>> @@ -244,6 +298,478 @@ static int __xe_vm_bind_array(int fd, uint32_t vm,
>>       return 0;
>>   }
>>   +static void init_pdata(struct process_data *pdata)
>> +{
>> +    pthread_mutexattr_t mattr;
>> +    pthread_condattr_t cattr;
>> +
>> +    pthread_mutexattr_init(&mattr);
>> +    igt_assert_eq(pthread_mutexattr_setpshared(&mattr, 
>> PTHREAD_PROCESS_SHARED), 0);
>> +    igt_assert_eq(pthread_mutexattr_setrobust(&mattr, 
>> PTHREAD_MUTEX_ROBUST), 0);
>> +    igt_assert_eq(pthread_mutex_init(&pdata->mutex, &mattr), 0);
>> +    pthread_mutexattr_destroy(&mattr);
>> +
>> +    pthread_condattr_init(&cattr);
>> +    igt_assert_eq(pthread_condattr_setpshared(&cattr, 
>> PTHREAD_PROCESS_SHARED), 0);
>> +    igt_assert_eq(pthread_cond_init(&pdata->cond, &cattr), 0);
>> +    pthread_condattr_destroy(&cattr);
>> +    pdata->ready = 0;
>> +    pdata->failed = 0;
>> +    pdata->go = false;
>> +}
>> +
>> +static void process_ready_and_wait(struct process_data *pdata)
>> +{
>> +    int ret = pthread_mutex_lock(&pdata->mutex);
>> +
>> +    if (ret == EOWNERDEAD)
>> + igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
>> +    else
>> +        igt_assert_eq(ret, 0);
>> +    pdata->ready++;
>> +    pthread_cond_broadcast(&pdata->cond);
>> +    while (!pdata->go)
>> +        pthread_cond_wait(&pdata->cond, &pdata->mutex);
>> +    pthread_mutex_unlock(&pdata->mutex);
>> +}
>> +
>> +static void process_setup_failed(struct process_data *pdata)
>> +{
>> +    int ret = pthread_mutex_lock(&pdata->mutex);
>> +
>> +    if (ret == EOWNERDEAD)
>> + igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
>> +    else
>> +        igt_assert_eq(ret, 0);
>> +    pdata->failed++;
>> +    pthread_cond_broadcast(&pdata->cond);
>> +    pthread_mutex_unlock(&pdata->mutex);
>> +}
>> +
>> +static void release_ready_processes(struct process_data *pdata, int 
>> n_proc)
>> +{
>> +    struct timespec timeout;
>> +    int ret;
>> +
>> +    ret = pthread_mutex_lock(&pdata->mutex);
>> +    if (ret == EOWNERDEAD)
>> + igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
>> +    else
>> +        igt_assert_eq(ret, 0);
>> +
>> +    clock_gettime(CLOCK_REALTIME, &timeout);
>> +    timeout.tv_sec += 30;
>> +    /*
>> +     * Wait until all children have either reached VM Bind rendevouz
>> +     * Or, failed setup and exited the test path.
>> +     */
>> +    while (pdata->ready + pdata->failed < n_proc) {
>> +        ret = pthread_cond_timedwait(&pdata->cond, &pdata->mutex, 
>> &timeout);
>> +        if (ret == EOWNERDEAD) {
>> + igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
>
> If pthread_cond_timedwait() returned EOWNERDEAD (a lock holder died) 
> code made the mutex consistent
>
> but it is checking igt_assert_eq(ret, 0) which will fail as ret is 
> still EOWNERDEAD, so in case of EOWNERDEAD it should continue to check
>
> ret    if (ret == EOWNERDEAD) {
>
> igt_assert_eq(pthread_mutex_consistent(&pdata->mutex), 0);
>
> continue;                 /* re-check loop condition */
* Sobin: Agreed . Will be taken care in next revision*
>
> }
>
>> +        } else if (ret == ETIMEDOUT) {
>> +            igt_warn("Timeout waiting for the child process: 
>> ready=%d, failed =%d, expected=%d",
>> +            pdata->ready, pdata->failed, n_proc);
>> +            break;
>> +        }
>> +        igt_assert_eq(ret, 0);
>> +    }
>> +
>> +    igt_debug("Process rendezvous: ready=%d failed=%d total = %d\n",
>> +          pdata->ready, pdata->failed, n_proc);
>> +
>> +    /* Release every successful child into VM_Bind at same time*/
>> +    pdata->go = true;
>> +    pthread_cond_broadcast(&pdata->cond);
>> +    pthread_mutex_unlock(&pdata->mutex);
>> +}
>> +
>> +static int build_add_batch(struct gem_bo *batch_bo, struct gem_bo 
>> *integers_bo,
>> +               struct gem_bo *result_bo, int ints_to_add)
>> +{
>> +    int pos = 0;
>> +    int i;
>> +    uint64_t tmp_addr;
>> +
>> +    batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | 
>> MI_LRI_LRM_CS_MMIO | 2;
>> +    batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
>> +    tmp_addr = integers_bo->addr + 0 * sizeof(uint32_t);
>> +    batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
>> +    batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
>> +    for (i = 1; i < ints_to_add; i++) {
>> +        /* r1 = integers_bo[i] */
>> +        batch_bo->ptr[pos++] = MI_LOAD_REGISTER_MEM_CMD | 
>> MI_LRI_LRM_CS_MMIO | 2;
>> +        batch_bo->ptr[pos++] = GPR_RX_ADDR(1);
>> +        tmp_addr = integers_bo->addr + i * sizeof(uint32_t);
>> +        batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
>> +        batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
>> +        /* r0 = r0 + r1 */
>> +        batch_bo->ptr[pos++] = MI_MATH(4);
>> +        batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, 
>> MI_MATH_REG(0));
>> +        batch_bo->ptr[pos++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, 
>> MI_MATH_REG(1));
>> +        batch_bo->ptr[pos++] = MI_MATH_ADD;
>> +        batch_bo->ptr[pos++] = MI_MATH_STORE(MI_MATH_REG(0), 
>> MI_MATH_REG_ACCU);
>> +    }
>> +    /* result_bo[0] = r0 */
>> +    batch_bo->ptr[pos++] = MI_STORE_REGISTER_MEM_GEN8 | 
>> MI_LRI_LRM_CS_MMIO;
>> +    batch_bo->ptr[pos++] = GPR_RX_ADDR(0);
>> +    tmp_addr = result_bo->addr + 0 * sizeof(uint32_t);
>> +    batch_bo->ptr[pos++] = tmp_addr & 0xFFFFFFFF;
>> +    batch_bo->ptr[pos++] = (tmp_addr >> 32) & 0xFFFFFFFF;
>> +
>> +    batch_bo->ptr[pos++] = MI_BATCH_BUFFER_END;
>> +    while (pos % 4 != 0)
>> +        batch_bo->ptr[pos++] = MI_NOOP;
>> +    return pos;
>> +}
>> +
>> +static void create_exec_queue(int fd, struct xe_oversubscribe_ctx *ctx)
>> +{
>> +    ctx->exec_queue_id = xe_exec_queue_create(fd, ctx->vm_id,
>> +                          &xe_engine(fd, 0)->instance, 0);
>> +}
>> +
>> +static uint64_t *
>> +vm_bind_bo_batch(int fd, struct xe_oversubscribe_ctx *ctx, struct 
>> gem_bo *bos, int size,
>> +         int *out_err)
>> +{
>> +    uint64_t *ufence;
>> +    struct drm_xe_sync bind_sync;
>> +    struct drm_xe_vm_bind_op *binds;
>> +    int i;
>> +
>> +    binds = calloc(size, sizeof(*binds));
>> +    igt_assert(binds);
>> +
>> +    ufence = calloc(1, sizeof(*ufence));
>> +    igt_assert(ufence);
>> +    bind_sync = (struct drm_xe_sync) {
>> +        .type = DRM_XE_SYNC_TYPE_USER_FENCE,
>> +        .flags = DRM_XE_SYNC_FLAG_SIGNAL,
>> +        .addr = to_user_pointer(ufence),
>> +        .timeline_value = 1,
>> +    };
>> +
>> +    for (i = 0; i < size; i++) {
>> +        binds[i] = (struct drm_xe_vm_bind_op) {
>> +            .obj = bos[i].handle,
>> +            .obj_offset = 0,
>> +            .range = bos[i].size,
>> +            .addr = bos[i].addr,
>> +            .op = DRM_XE_VM_BIND_OP_MAP,
>> +            .flags = 0,
>> +        };
>> +    }
>> +    *out_err = __xe_vm_bind_array(fd, ctx->vm_id, binds, size, 
>> &bind_sync, 1);
>> +    free(binds);
>> +    return ufence;
>> +}
>> +
>> +/* Returns 1 (caller should skip exec) on an allowed OOM error, 0 
>> otherwise. */
>> +static int bind_bos(int fd, struct xe_oversubscribe_ctx *ctx, struct 
>> gem_bo *bufs,
>> +            struct mem_bind_sync *bind, int *bind_err, bool allow_oom)
>> +{
>> +    if (!bind->n_bufs)
>> +        return 0;
>> +
>> +    bind->binds_ufence = vm_bind_bo_batch(fd, ctx, bufs, 
>> bind->n_bufs, bind_err);
>> +
>> +    if (*bind_err) {
>> +        if (allow_oom) {
>> +            igt_assert_f(*bind_err == -ENOMEM || *bind_err == -ENOSPC,
>> +                     "Unexpected bind error: %d (%s)\n",
>> +                     *bind_err, strerror(-*bind_err));
>> +            igt_debug("Bind failed with expected OOM (%s), skipping 
>> exec\n",
>> +                  strerror(-*bind_err));
>> +            return 1;
>> +        }
>> +
>> +        igt_assert_f(false, "Unexpected bind error: %d", *bind_err);
>> +    }
>> +
>> +    xe_wait_ufence(fd, bind->binds_ufence, 1, 0, TIMEOUT_NS);
>> +    return 0;
>> +}
>> +
>> +static int fill_random_integers(struct gem_bo *int_bo, int ints_to_add)
>> +{
>> +    uint32_t expected_result = 0;
>> +    char expr[256];
>> +    int len = 0;
>> +
>> +    for (int i = 0; i < ints_to_add; i++) {
>> +        uint32_t random_int = rand() % 8;
>> +
>> +        int_bo->ptr[i] = random_int;
>> +        expected_result += random_int;
>> +
>> +        len += snprintf(expr + len, sizeof(expr) - len, "%s%u",
>> +                i ? " + " : "", random_int);
>> +    }
>> +    igt_debug("%s = %u\n", expr, expected_result);
>> +    return expected_result;
>> +}
>> +
>> +static void cleanup_bo_resources(int fd, struct gem_bo *bo)
>> +{
>> +    if (bo->ptr) {
>> +        igt_assert_eq(munmap(bo->ptr, bo->size), 0);
>> +        bo->ptr = NULL;
>> +    }
>> +    if (bo->handle)
>> +        gem_close(fd, bo->handle);
>> +}
>> +
>> +static int create_test_bos(int fd, struct xe_oversubscribe_ctx *ctx,
>> +               struct mem_bind_sync *bind, uint32_t placement,
>> +               uint64_t *addr)
>> +{
>> +    const char *mem_type = (placement & vram_memory(fd, 0)) ? "VRAM" 
>> : "SRAM";
>> +    int ret;
>> +
>> +    for (int i = 0; i < bind->n_bufs; i++) {
>> +        struct gem_bo *bo = &bind->bufs[i];
>> +
>> +        bo->size = GB(1);
>> +        ret = __xe_bo_create_caching(fd, ctx->vm_id, bo->size, 
>> placement, 0,
>> +                         DRM_XE_GEM_CPU_CACHING_WC, &bo->handle);
>> +        if (ret) {
>> +            int saved_errno = errno; /* capture before anything can 
>> clobber it */
>> +
>> +            bind->n_bufs = i;
>> +            if (saved_errno == ENOMEM || saved_errno == ENOSPC) {
>> +                /* Continue on OOM, expected when oversubscribing 
>> the VM */
>> +                igt_debug("%s allocation failed at buffer %d 
>> (OOM)\n", mem_type, i);
>> +                break;
>> +            }
>> +            /* We are returning as this is a fail scenario */
>> +            igt_warn("%s allocation failed at buffer %d: %s\n",
>> +                 mem_type, i, strerror(saved_errno));
>> +            return -saved_errno;
>> +        }
>> +        bo->ptr = NULL;
>> +        bo->addr = *addr;
>> +        *addr += bo->size;
>> +        igt_debug("%s buffer %d created at 0x%016lx\n", mem_type, i, 
>> bo->addr);
>> +    }
>> +    return 0;
>> +}
>> +
>> +static void cleanup_sram_vram_objs(int fd, struct mem_bind_sync 
>> *vram_bind,
>> +                   struct mem_bind_sync *sram_bind)
>> +{
>> +    for (int i = 0; i < vram_bind->n_bufs; i++)
>> +        gem_close(fd, vram_bind->bufs[i].handle);
>> +    for (int i = 0; i < sram_bind->n_bufs; i++)
>> +        gem_close(fd, sram_bind->bufs[i].handle);
>> +    free(vram_bind->bufs);
>> +    free(sram_bind->bufs);
>> +    if (vram_bind->binds_ufence)
>> +        free(vram_bind->binds_ufence);
>> +    if (sram_bind->binds_ufence)
>> +        free(sram_bind->binds_ufence);
>> +}
>> +
>> +static void create_bo(int fd, uint32_t vm, struct gem_bo *bo, 
>> uint64_t size,
>> +              uint64_t addr, bool map_now)
>> +{
>> +    bo->size = ALIGN(size, 4096);
>> +    bo->handle = xe_bo_create_caching(fd, vm, bo->size, 
>> system_memory(fd), 0,
>> +                      DRM_XE_GEM_CPU_CACHING_WC);
>> +    igt_assert(bo->handle);
>> +    bo->addr = addr;
>> +    if (map_now) {
>> +        bo->ptr = xe_bo_map(fd, bo->handle, bo->size);
>> +        igt_assert(bo->ptr != MAP_FAILED);
>> +    } else {
>> +        bo->ptr = NULL;
>> +    }
>> +}
>> +
>> +static bool calc_oversubscribe_params(int fd, struct 
>> oversubscribe_params *p)
>> +{
>> +    uint64_t target_vram, target_sram;
>> +    uint64_t total_vram_bufs, total_sram_bufs, max_by_mem;
>> +
>> +    p->vram_size =  xe_visible_available_vram_size(fd, 0);
>
> Sizing used xe_visible_available_vram_size() gives 
> vram.cpu_visible_available; which can be small
>
> to accomodate big BOs or 2x demand, it should be 
> xe_available_vram_size which gives vram.total_available;
>
*Sobin: **We should take visible ram as  available vram can provide 
false  assumptions while allocating;
*

*This will help in early bail out if sufficient VRAM memory is not there. *

*If whole vram is given there will be more number of eviction and can 
cause more*

*probability of OOM.*


>> +    p->sram_size = (uint64_t)igt_get_avail_ram_mb() << 20;
>> +    /*
>> +     * Dynamically cap VRAM oversubscription so the overflow into 
>> system
>> +     * RAM stays within 25% of available RAM. On small-VRAM platforms
>> +     * the 2x target fits within the cap and behavior is
>> +     * unchanged; on large-VRAM platforms (e.g. PVC) this prevents OOM.
>> +     */
>> +
>> +    target_vram = min(p->vram_size * 2, p->vram_size + p->sram_size 
>> / 4);
>> +    target_sram = min_t(uint64_t, p->sram_size * 50 / 100,
>> +                MAX_SRAM_TEST_SIZE);
>> +    total_vram_bufs = target_vram / GB(1);
>> +    total_sram_bufs = target_sram / GB(1);
>> +    max_by_mem = min(total_vram_bufs / MIN_BUFS_PER_PROC,
>> +             total_sram_bufs / MIN_BUFS_PER_PROC);
>> +
>> +    p->n_proc = min_t(int, max_by_mem, MAX_PROCS);
>> +    if (p->n_proc <= 0)
>
> On low ram machines it might execute single-process but above in 
> description mentioned 2 process, so
>
> condition p->n_proc < 2 should be checked.
> Agreed: This will be taken care.
>> +        return false;
>> +    p->n_vram_bufs = max_t(int, 2, total_vram_bufs / p->n_proc);
>> +    p->n_sram_bufs = max_t(int, 2, total_sram_bufs / p->n_proc);
>> +    p->total_vram_demand = (uint64_t)p->n_proc * p->n_vram_bufs * 
>> GB(1);
>> +    return true;
>> +}
>> +
>> +static void test_vm_oversubscribe_concurrent_bind(int fd)
>> +{
>> +    struct oversubscribe_params p;
>> +    struct process_data *pdata;
>> +
>> +    igt_require_f(calc_oversubscribe_params(fd, &p),
>> +              "Not enough VRAM/RAM for oversubscription test\n");
>> +
>> +    igt_debug("VRAM size: %" PRIu64 "MB, System RAM available: %" 
>> PRIu64 "MB\n",
>> +          p.vram_size >> 20, p.sram_size >> 20);
>> +
>> +    igt_debug("n_proc = %d\n", p.n_proc);
>> +    igt_debug("VRAM: %" PRIu64 "GB\n", p.vram_size >> 30);
>> +    igt_debug("VRAM demand: %" PRIu64 "MB (%.2fx oversubscription)\n",
>> +          p.total_vram_demand >> 20, (double)p.total_vram_demand / 
>> p.vram_size);
>> +    igt_debug("Processes=%d VRAM_bufs=%d SRAM_bufs=%d\n", p.n_proc,
>> +          p.n_vram_bufs, p.n_sram_bufs);
>> +
>> +    pdata = mmap(NULL, sizeof(*pdata), PROT_READ | PROT_WRITE,
>> +             MAP_SHARED | MAP_ANONYMOUS, -1, 0);
>> +    igt_assert(pdata != MAP_FAILED);
>> +    init_pdata(pdata);
>> +
>> +    igt_fork(child, p.n_proc) {
>> +        struct xe_oversubscribe_ctx ctx = {0};
>> +        int rc, ret, fd_c;
>> +        uint64_t addr = STRESS_BIND_ADDR;
>> +        uint32_t expected_result = 0;
>> +        struct gem_bo integers_bo = {0}, result_bo = {0}, batch_bo = 
>> {0};
>> +        struct gem_bo *vram_bufs, *sram_bufs;
>> +        int pos = 0;
>> +        struct mem_bind_sync vram_bind = {0};
>> +        struct mem_bind_sync sram_bind = {0};
>> +        struct drm_xe_sync batch_syncs[1];
>> +        struct drm_xe_exec exec;
>> +        struct gem_bo ufence_bo = {0};
>> +        int vram_bind_err = 0, sram_bind_err = 0;
>> +
>> +        vram_bufs = calloc(p.n_vram_bufs, sizeof(*vram_bufs));
>> +        sram_bufs = calloc(p.n_sram_bufs, sizeof(*sram_bufs));
>> +        srand(child);
>> +
>> +        fd_c = drm_open_driver(DRIVER_XE);
>> +
>> +        igt_assert(vram_bufs && sram_bufs);
>> +
>> +        ctx.vm_id = xe_vm_create(fd_c, 
>> DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0);
>> +        create_exec_queue(fd_c, &ctx);
>> +        vram_bind.bufs = vram_bufs;
>> +        vram_bind.n_bufs = p.n_vram_bufs;
>> +        sram_bind.bufs = sram_bufs;
>> +        sram_bind.n_bufs = p.n_sram_bufs;
>> +
>> +        ret = create_test_bos(fd_c, &ctx, &vram_bind, 
>> vram_memory(fd_c, 0), &addr);
>> +        if (ret) {
>> +            process_setup_failed(pdata);
>> +            goto cleanup;
>> +        }
>> +
>> +        ret = create_test_bos(fd_c, &ctx, &sram_bind, 
>> system_memory(fd_c), &addr);
>> +        if (ret) {
>> +            process_setup_failed(pdata);
>> +            goto cleanup;
>> +        }
>> +
>> +        if (!vram_bind.n_bufs || !sram_bind.n_bufs) {
>> +            igt_debug("No BOs allocated; VRAM/SRAM unavailable, 
>> skipping\n");
>> +            process_setup_failed(pdata);
>> +            goto cleanup;
>> +        }
>
> When a child hit an allocation failure it called 
> process_setup_failed(), jumped to cleanup, and exited normally (status 
> 0).
>
> The parent only waited for children to exit — it never checked whether 
> any test executed. So a run where every child failed
>
> still it'll be reported as PASS. Instead a counter e.g. failed_count 
> should be incremented in process_setup_failed() and after cleanup:
>
> failed_count value must be checked so that user knows during setup/bo 
> creation fault happened
>
> something like: igt_assert_f(pdata->fault_count == 0,
>              "%d child(ren) hit unexpected setup errors\n", 
> pdata->fault_count);

*Sobin: *=> We are creating multiple process and will be doing bind at 
rendezvous  .

Some process can fail due to lack of SRAM / VRAM that will be skipped 
unless we get a

real fault for those conditions assertion is handled .

We can track the process based on OOM as some child process can fail 
with OOM

>> +
>> +        /*
>> +         * All allocations are complete. Report Ready and wait until 
>> every
>> +         * child has either reached this point or repported a setup 
>> failure.
>> +         */
>> +
>> +         process_ready_and_wait(pdata);
>> +
>> +        /*
>> +         * VM_Bind starts only after the parent releases all ready
>> +         * childen.
>> +         */
>> +
>> +        if (bind_bos(fd_c, &ctx, vram_bufs, &vram_bind, 
>> &vram_bind_err, true))
>> +            goto cleanup;
>> +
>> +        if (bind_bos(fd_c, &ctx, sram_bufs, &sram_bind, 
>> &sram_bind_err, false))
>> +            goto cleanup;
>> +
>> +        create_bo(fd_c, ctx.vm_id, &integers_bo, 4096, 
>> EXEC_DATA_ADDR, true);
>> +        expected_result = fill_random_integers(&integers_bo, 
>> INT_ADD_CNT);
>> +        igt_debug("%d\n", expected_result);
>> +        create_bo(fd_c, ctx.vm_id, &result_bo, 4096, 
>> EXEC_RESULT_ADDR, false);
>> +        create_bo(fd_c, ctx.vm_id, &batch_bo, 4096, EXEC_BATCH_ADDR, 
>> true);
>> +        pos = build_add_batch(&batch_bo, &integers_bo, &result_bo, 
>> INT_ADD_CNT);
>> +
>> +        igt_assert(pos * sizeof(int) <= batch_bo.size);
>> +
>> +        xe_vm_bind_lr_sync(fd_c, ctx.vm_id, integers_bo.handle, 0, 
>> integers_bo.addr,
>> +                   integers_bo.size, 0);
>> +        xe_vm_bind_lr_sync(fd_c, ctx.vm_id, result_bo.handle, 0, 
>> result_bo.addr,
>> +                   result_bo.size, 0);
>> +        xe_vm_bind_lr_sync(fd_c, ctx.vm_id, batch_bo.handle, 0, 
>> batch_bo.addr,
>> +                   batch_bo.size, 0);
>> +        create_bo(fd_c, ctx.vm_id, &ufence_bo, 4096, 
>> EXEC_UFENCE_ADDR, true);
>> +
>> +        memset(ufence_bo.ptr, 0, ufence_bo.size);
>> +        xe_vm_bind_lr_sync(fd_c, ctx.vm_id, ufence_bo.handle, 0, 
>> ufence_bo.addr,
>> +                   ufence_bo.size, 0);
>> +
>> +        batch_syncs[0] = (struct drm_xe_sync){
>> +            .type = DRM_XE_SYNC_TYPE_USER_FENCE,
>> +            .flags = DRM_XE_SYNC_FLAG_SIGNAL,
>> +            .addr = ufence_bo.addr,
>> +            .timeline_value = USER_FENCE_VALUE,
>> +        };
>> +
>> +        exec = (struct drm_xe_exec) {
>> +            .exec_queue_id = ctx.exec_queue_id,
>> +            .num_syncs = 1,
>> +            .syncs = (uintptr_t)batch_syncs,
>> +            .address = batch_bo.addr,
>> +            .num_batch_buffer = 1,
>> +        };
>> +
>> +        rc = igt_ioctl(fd_c, DRM_IOCTL_XE_EXEC, &exec);
>> +        igt_assert_f(rc == 0, "xe_exec failed unexpectedly: %s (%d)\n",
>> +                 strerror(errno), errno);
>> +        xe_wait_ufence(fd_c, (uint64_t *)ufence_bo.ptr, 
>> USER_FENCE_VALUE, ctx.exec_queue_id,
>> +                   TIMEOUT_NS);
>> +        result_bo.ptr = xe_bo_map(fd_c, result_bo.handle, 
>> result_bo.size);
>> +        igt_assert(result_bo.ptr != MAP_FAILED);
>> +        igt_assert_eq(result_bo.ptr[0], expected_result);
> Here child should report completion also, something like 
> child_completion(pdata) { pdata->child_completed++;}

  Agreed/


>> +cleanup:
>> +        cleanup_bo_resources(fd_c, &ufence_bo);
>> +        cleanup_bo_resources(fd_c, &result_bo);
>> +        cleanup_bo_resources(fd_c, &batch_bo);
>> +        cleanup_bo_resources(fd_c, &integers_bo);
>> +        cleanup_sram_vram_objs(fd_c, &vram_bind, &sram_bind);
>> +        xe_exec_queue_destroy(fd_c, ctx.exec_queue_id);
>> +        xe_vm_destroy(fd_c, ctx.vm_id);
>> +        drm_close_driver(fd_c);
>> +    }
>> +
>> +    release_ready_processes(pdata, p.n_proc);
>> +    igt_waitchildren();
>
> If a child is killed or blocked before reporting, the parent timed out 
> after 30 s,
>
> it releases the rest and calls igt_waitchildren() which could wait 
> forever/hung. Here all forked children
>
> should be killed first.

Agreed . The child process will be killed after 60 seconds of hang in 
child process.

We will be using  igt_waitchildren_timeout

>
> Both counters updated above will be checked in assertion to know the 
> real cause of error
>
> igt_assert_f(pdata->fault_count == 0,
>              "%d child(ren) hit unexpected setup errors\n", 
> pdata->fault_count);

  => fault count will take count of the number of child process that got 
failed with reason other than OOM.

As discussed offline we can summarize the count in the summary at the end


for e.g.:->


Starting subtest: test_vm_oversubscribe_concurrent_bind
Oversubscribe summary : 7 processes
Setup Faulted (unexpected error): 0
Setup skipped (OOM cases) 0
Bind failed (ENOMEM/ENOSPC) 0


> igt_assert_f(pdata->child_completed >= 2,
>              "Need >=2 processes to complete the oversubscribed 
> submit, got %d\n",
>              pdata->child_completed);
>
>> +    igt_reset_timeout();
>> +
>> +    pthread_cond_destroy(&pdata->cond);
>> +    pthread_mutex_destroy(&pdata->mutex);
>> +    igt_assert_eq(munmap(pdata, sizeof(*pdata)), 0);
>> +}
>> +
>>   static void alloc_sizes_init(void)
>>   {
>>       int i;
>> @@ -986,6 +1512,7 @@ static const struct test_case test_matrix[] = {
>>       { "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING, 
>> TYPE_THREAD, false },
>>       { "threads-leak-binding-rand-sizes-50-unaligned", 50, 
>> LEAK_BINDING | UNALIGNED,
>>         TYPE_THREAD, false },
>> +    { "test_vm_oversubscribe_concurrent_bind", 0, 0, 
>> TYPE_OVERSUBSCRIBE, false},
>>   };
>>     int igt_main()
>> @@ -1011,6 +1538,10 @@ int igt_main()
>>                   run_threaded_bo_alloc_test(fd, t->count, t->flags);
>>               }
>>               break;
>> +        case TYPE_OVERSUBSCRIBE:
>> +            igt_subtest_f("%s", t->name)
>> +                test_vm_oversubscribe_concurrent_bind(fd);
>> +            break;
>>           case TYPE_ALL_SIZES:
>>           case TYPE_RANDOM_SIZE:
>>           case TYPE_ARRAY_BIND:

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Re: [PATCH i-g-t v5 4/5] tests/intel: Add threaded random-size allocation stress tests

[Thomas, Sobin]

On 10/5/2026 12:26 PM, Dandamudi, Priyanka wrote:
>
>> -----Original Message-----
>> From: Thomas, Sobin <sobin.thomas@intel.com>
>> Sent: 22 September 2026 16:35
>> To: igt-dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
>> Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka
>> <priyanka.dandamudi@intel.com>
>> Subject: [PATCH i-g-t v5 4/5] tests/intel: Add threaded random-size allocation
>> stress tests
>>
>> Add a new TYPE_THREAD test mode that creates a worker thread per available
>> engine and performs random-sized BO allocations concurrently.
>>
>> Each thread creates its own VM and execution queue and exercises the existing
>> allocation path with both aligned and unaligned bind addresses.
>> Additional variants cover leaked bindings.
>>
>> These tests provide additional stress coverage for concurrent BO allocation and
>> VM bind activity across multiple engines.
>>
>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
>> ---
>>   tests/intel/xe_bo_alloc.c | 149 +++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 148 insertions(+), 1 deletion(-)
>>
>> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c index
>> 343d07626..d8368087b 100644
>> --- a/tests/intel/xe_bo_alloc.c
>> +++ b/tests/intel/xe_bo_alloc.c
>> @@ -56,6 +56,26 @@
>>    * Description: Test 10 batches of 10 random BO allocation sizes bound together
>> as a single
>>    * array of binds, unaligned bind addresses
>>    * Test category: functionality test
>> + *
>> + *
>> + * SUBTEST: threads-rand-sizes-50
>> + * Description: Test 50 random bo allocation sizes in test table with a
>> + thread per engine
>> + * test category: stress test
>> + *
>> + * SUBTEST: threads-rand-sizes-50-unaligned
>> + * Description: Test 50 random bo allocation sizes in test table with a
>> + thread per engine,
>> + * unaligned bind addresses
>> + * test category: stress test
>> + *
>> + * SUBTEST: threads-leak-binding-rand-sizes-50
>> + * Description: Test 50 random BO allocation sizes in test table with a
>> + thread per engine,
>> + * leak the binding
>> + * Test category: stress test
>> + *
>> + * SUBTEST: threads-leak-binding-rand-sizes-50-unaligned
>> + * Description: Test 50 random BO allocation sizes in test table with a
>> + thread per engine,
>> + * leak the binding, unaligned bind addresses
>> + * Test category: stress test
>>    */
>>
>>   #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) @@ -82,7 +102,8 @@ static
>> uint64_t *alloc_sizes;  enum test_type {
>>   	TYPE_ALL_SIZES,
>>   	TYPE_RANDOM_SIZE,
>> -	TYPE_ARRAY_BIND
>> +	TYPE_ARRAY_BIND,
>> +	TYPE_THREAD
>>   };
>>
>>   struct test_case {
>> @@ -129,6 +150,20 @@ struct batch_data {
>>   	uint32_t data;
>>   };
>>
>> +struct thread_data {
>> +	uint64_t va_base;
>> +	pthread_t thread;
>> +	pthread_mutex_t *mutex;
>> +	pthread_cond_t *cond;
>> +	struct drm_xe_engine_class_instance *hwe;
>> +	int fd;
>> +	int count;
>> +	uint32_t vm;
>> +	uint32_t flags;
>> +	unsigned int seed;
> seed variable is not used anywhere in this commit.


Will be reused in next series along with rand

>> +	bool *go;
>> +};
>> +
>>   /*
>>    * Reserve a chunk of process address space to use as the VM bind address
>>    * for a BO, and hand back a pointer inside it aligned either to bo_size @@ -766,6
>> +801,103 @@ static void alloc_random_size_bos_array_bind(int fd, struct
>> drm_xe_engine_class_
>>   	free(leaks);
>>   }
>>
>> +static void *bo_alloc_thread_fn(void *data) {
>> +	struct thread_data *t = data;
>> +	uint32_t q;
>> +	int i;
>> +
>> +	igt_assert(!(t->flags & LEAK_BO));
>> +
>> +	pthread_mutex_lock(t->mutex);
>> +	while (!*t->go)
>> +		pthread_cond_wait(t->cond, t->mutex);
>> +	pthread_mutex_unlock(t->mutex);
>> +
>> +	q =  xe_exec_queue_create(t->fd, t->vm, t->hwe, 0);
>> +
>> +	for (i = 0; i < t->count; ++i)
>> +		test_alloc_size(t->fd, t->vm, q, t->hwe->gt_id,
>> +				alloc_sizes[rand() % N_ALLOC_SIZES], here  rand_r(&t->seed) can be used instead of global rand()
>> +				t->flags, t->va_base);
> Same va_base is being. t->va_base is set once per thread and never advanced between the 50 iterations.
> threads-rand-sizes-50 is fine as it binds and unbinds+releases after each iteration but for leak it might collide with previous one.

Agreed: Will make changes


>> +
>> +	xe_exec_queue_destroy(t->fd, q);
>> +
>> +	return NULL;
>> +}
>> +
>> +static void run_threaded_bo_alloc_test(int fd, int count, uint32_t
>> +flags) {
>> +	struct drm_xe_engine_class_instance *hwe;
>> +	struct drm_xe_engine_class_instance **engines;
>> +	struct thread_data *threads_data;
>> +	pthread_mutex_t mutex;
>> +	pthread_cond_t cond;
>> +	bool begin_work = false;
>> +	int n_found = 0, n_threads = 0, i, ret;
>> +
>> +	xe_for_each_engine(fd, hwe)
>> +		n_found++;
>> +
>> +	igt_assert(n_found > 0);
>> +
>> +	engines = calloc(n_found, sizeof(*engines));
>> +	igt_assert(engines);
>> +
>> +	i = 0;
>> +	xe_for_each_engine(fd, hwe)
>> +		engines[i++] = hwe;
>> +
>> +	threads_data = calloc(n_found, sizeof(*threads_data));
>> +	igt_assert(threads_data);
>> +
>> +	pthread_mutex_init(&mutex, 0);
>> +	pthread_cond_init(&cond, 0);
>> +
>> +	for (i = 0; i < n_found; ++i) {
>> +		threads_data[i].mutex = &mutex;
>> +		threads_data[i].cond = &cond;
>> +		/* reuse engine 0 if only one exists */
>> +		threads_data[i].hwe = engines[i % n_found];
> Here i%n_found is not required just i is enough as both are same.
Agreed
>> +		threads_data[i].fd = fd;
>> +		threads_data[i].count = count;
>> +		threads_data[i].vm = xe_vm_create(fd, 0, 0);
>> +		threads_data[i].flags = flags;
>> +		threads_data[i].go = &begin_work;
>> +		threads_data[i].seed = i + 1;
>> +		threads_data[i].va_base = BO_BIND_BASE_ADDR + (uint64_t)i *
>> THREAD_VA_STRIDE;
>> +		ret = pthread_create(&threads_data[i].thread, 0,
>> bo_alloc_thread_fn,
>> +				     &threads_data[i]);
>> +		if (ret)
>> +			break;
>> +		n_threads++;
>> +	}
>> +
>> +	ret = pthread_mutex_lock(&mutex);
>> +	igt_assert_eq(ret, 0);
>> +	begin_work = true;
>> +	ret = pthread_cond_broadcast(&cond);
>> +	igt_assert_eq(ret, 0);
>> +	ret = pthread_mutex_unlock(&mutex);
>> +	igt_assert_eq(ret, 0);
>> +
>> +	for (i = 0; i < n_threads; ++i) {
>> +		ret = pthread_join(threads_data[i].thread, NULL);
>> +		igt_assert_eq(ret, 0);
>> +	}
>> +
>> +	/* vm is created for every slot up to n_found regardless of thread
>> creation success */
>> +	for (i = 0; i < n_found; ++i)
>> +		xe_vm_destroy(fd, threads_data[i].vm);
>> +
>> +	ret = pthread_cond_destroy(&cond);
>> +	igt_assert_eq(ret, 0);
>> +	ret = pthread_mutex_destroy(&mutex);
>> +	igt_assert_eq(ret, 0);
>> +	free(threads_data);
>> +	free(engines);
>> +}
>> +
>>   static void run_gt_dynamic_subtests(int fd, const struct test_case *t)  {
>>   	struct drm_xe_engine_class_instance *hwe; @@ -849,6 +981,11 @@
>> static const struct test_case test_matrix[] = {
>>   	{ "array-binds-rand-sizes-10", 10, ARRAY_BIND, TYPE_ARRAY_BIND, true
>> },
>>   	{ "array-binds-rand-sizes-10-unaligned", 10,  ARRAY_BIND | UNALIGNED,
>> TYPE_ARRAY_BIND,
>>   	  true },
>> +	{ "threads-rand-sizes-50", 50, 0, TYPE_THREAD, false },
>> +	{ "threads-rand-sizes-50-unaligned", 50, UNALIGNED, TYPE_THREAD,
>> false },
>> +	{ "threads-leak-binding-rand-sizes-50", 50, LEAK_BINDING,
>> TYPE_THREAD, false },
>> +	{ "threads-leak-binding-rand-sizes-50-unaligned", 50, LEAK_BINDING |
>> UNALIGNED,
>> +	  TYPE_THREAD, false },
>>   };
>>
>>   int igt_main()
>> @@ -864,6 +1001,16 @@ int igt_main()
>>   		const struct test_case *t = &test_matrix[i];
>>
>>   		switch (t->type) {
>> +		case TYPE_THREAD:
>> +			igt_subtest_f("%s", t->name) {
>> +				if (t->requires_evict_ram) {
>> +					igt_require(xe_has_vram(fd));
>> +					igt_require(igt_get_avail_ram_mb() >=
>> +						    (xe_visible_vram_size(fd, 0)
>>>> 20) / 2);
>> +				}
>> +				run_threaded_bo_alloc_test(fd, t->count, t-
>>> flags);
>> +			}
>> +			break;
>>   		case TYPE_ALL_SIZES:
>>   		case TYPE_RANDOM_SIZE:
>>   		case TYPE_ARRAY_BIND:
>> --
>> 2.52.0

RE: [PATCH i-g-t v5 3/5] tests/intel: Add array-of-binds random-size allocation tests

[Thomas, Sobin]

Thanks Priyanka , please find response inline 

-----Original Message-----
From: Dandamudi, Priyanka <priyanka.dandamudi@intel.com> 
Sent: Monday, October 5, 2026 11:51 AM
To: Thomas, Sobin <sobin.thomas@intel.com>; igt-dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
Cc: Sharma, Nishit <nishit.sharma@intel.com>
Subject: RE: [PATCH i-g-t v5 3/5] tests/intel: Add array-of-binds random-size allocation tests



> -----Original Message-----
> From: Thomas, Sobin <sobin.thomas@intel.com>
> Sent: 22 September 2026 16:35
> To: igt-dev@lists.freedesktop.org; Brost, Matthew 
> <matthew.brost@intel.com>
> Cc: Sharma, Nishit <nishit.sharma@intel.com>; Dandamudi, Priyanka 
> <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t v5 3/5] tests/intel: Add array-of-binds 
> random-size allocation tests
> 
> Add new array-binds-rand-sizes-* subtests that allocate batches of 
> random-sized BOs and bind them using a single array-of-binds operation.
> 
> The new tests allocate 10 BOs per batch and exercise both aligned and 
> unaligned bind addresses. This extends existing eviction coverage by 
> verifying that BOs with varying sizes can be bound, managed and 
> evicted correctly when submitted as a single bind array rather than individual bind operations.
> 
> Introduce alloc_random_size_bos_array_bind(), which mirrors the 
> existing random-size allocation flow while grouping multiple BOs into 
> a single array bind submission. This is particularly useful for 
> eviction testing where a set of BOs needs to be resident or evicted as a unit.
> 
> The tests are intended to provide additional coverage for 
> array-of-binds handling under random allocation patterns and VRAM pressure scenarios.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Sobin Thomas <sobin.thomas@intel.com>
> ---
>  tests/intel/xe_bo_alloc.c | 177 
> ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 177 insertions(+)
> 
> diff --git a/tests/intel/xe_bo_alloc.c b/tests/intel/xe_bo_alloc.c 
> index
> bd5bf5a33..343d07626 100644
> --- a/tests/intel/xe_bo_alloc.c
> +++ b/tests/intel/xe_bo_alloc.c
> @@ -47,7 +47,15 @@
>   * Description: Test 100 random BO allocation sizes in test table, 
> unaligned bind addresses
>   * Test category: functionality test
>   *
> + * SUBTEST: array-binds-rand-sizes-10
> + * Description: Test 10 batches of 10 random BO allocation sizes each 
> + bound together as a
> + * single array of binds
> + * Test category: functionality test
>   *
> + * SUBTEST: array-binds-rand-sizes-10-unaligned
> + * Description: Test 10 batches of 10 random BO allocation sizes 
> + bound together as a single
> + * array of binds, unaligned bind addresses
> + * Test category: functionality test
>   */
> 
>  #define GB(x) (1024ULL * 1024ULL * 1024ULL * (x)) @@ -74,6 +82,7 @@ 
> static uint64_t *alloc_sizes;  enum test_type {
>  	TYPE_ALL_SIZES,
>  	TYPE_RANDOM_SIZE,
> +	TYPE_ARRAY_BIND
>  };
> 
>  struct test_case {
> @@ -178,6 +187,28 @@ static void bo_alloc_reserve_va(struct bo_alloc 
> *b, uint32_t flags, uint64_t va_
>  	igt_assert_eq_u64(b->gpu_va % align, 0);  }
> 
> +static int __xe_vm_bind_array(int fd, uint32_t vm,
> +			      struct drm_xe_vm_bind_op *bind_ops,
> +			      uint32_t num_bind, struct drm_xe_sync *sync,
> +			      uint32_t num_syncs)
> +{
> +	struct drm_xe_vm_bind bind = {
> +		.vm_id = vm,
> +		.num_binds = num_bind,
> +		.vector_of_binds = (uintptr_t)bind_ops,
> +		.num_syncs = num_syncs,
> +		.syncs = (uintptr_t)sync,
> +		.exec_queue_id = 0,
> +	};
> +
> +	igt_assert(num_bind > 0);
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind))
> +		return -errno;
> +
> +	return 0;
> +}
> +
>  static void alloc_sizes_init(void)
>  {
>  	int i;
> @@ -254,6 +285,7 @@ static void create_bo_arr(int fd, uint32_t vm, 
> struct bo_alloc *bos,  int n_bos,
>  	}
>  }
> 
> +
>  /*
>   * BIND step: bind one or more BOs as a single array-of-binds ioctl call
>   * (see __xe_vm_bind_array() above), replacing the previous 
> open-coded @@ -
> 308,8 +340,72 @@ static int test_bind_individual(int fd, uint32_t vm, 
> struct bo_alloc *bos, int n
>  	return 0;
>  }
> 
> +static int test_bind_array(int fd, uint32_t vm,
> +			   struct bo_alloc *bos, int n_bos) {
> +	struct drm_xe_vm_bind_op *bind_ops;
> +	struct drm_xe_sync sync = {
> +		.type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.handle = syncobj_create(fd, 0),
> +	};
> +	int i, ret;
> +
> +	igt_assert(n_bos > 0);
> +
> +	bind_ops = calloc(n_bos, sizeof(*bind_ops));
> +	igt_assert(bind_ops);
> +
> +	for (i = 0; i < n_bos; i++) {
> +		igt_assert_f(bos[i].bo,
> +			     "BO[%d] was not created before bind\n", i);
> +
> +		igt_assert_f(bos[i].bo_size,
> +			     "BO[%d] has zero size\n", i);
> +
> +		bind_ops[i] = (struct drm_xe_vm_bind_op) {
> +			.obj = bos[i].bo,
> +			.obj_offset = 0,
> +			.range = bos[i].bo_size,
> +			.addr = bos[i].gpu_va,
> +			.op = DRM_XE_VM_BIND_OP_MAP,
> +			.flags = 0,
> +		};
> +
> +		igt_debug("Bind op[%d]: bo=%u size=%#llx addr=%#llx\n",
> +			  i,
> +			  bos[i].bo,
> +			  (unsigned long long)bos[i].bo_size,
> +			  (unsigned long long)bos[i].gpu_va);
> +	}
> +
> +	ret = __xe_vm_bind_array(fd, vm, bind_ops, n_bos, &sync, 1);
> +	if (ret) {
> +		if (ret == -ENOMEM || ret == -ENOSPC) {
> +			syncobj_destroy(fd, sync.handle);
> +			free(bind_ops);
> +			return ret;
> +		}
> +
> +		igt_assert_f(false, "Array VM_BIND failed: ret=%d errno=%d
> (%s)\n",
> +			     ret, errno, strerror(errno));
> +	}
> +
> +	igt_assert_f(syncobj_wait(fd, &sync.handle, 1,
> +				  INT64_MAX, 0, NULL),
> +		     "Timed out waiting for array VM_BIND\n");
> +
> +	syncobj_destroy(fd, sync.handle);
> +	free(bind_ops);
> +
> +	return 0;
> +}
> +
>  static int test_bind(int fd, uint32_t vm, struct bo_alloc *bos, int 
> n_bos, uint32_t
> flags)  {
> +	if (flags & ARRAY_BIND)
> +		return test_bind_array(fd, vm, bos, n_bos);
> +	else
>  		return test_bind_individual(fd, vm, bos, n_bos);  }
> 
> @@ -600,6 +696,76 @@ static void all_sizes_once(int fd, struct 
> drm_xe_engine_class_instance *hwe)
>  	xe_vm_destroy(fd, vm);
>  }
> 
> +/*
> + * Same idea as alloc_rand_size_bos(), but each iteration binds 
> +N_BOS_PER_BIND BOs
> + * together via a single array-of-binds call instead of one at a time.
> + * Used by the array-binds-* subtests, in particular the eviction 
> +stress
> + * test where several BOs need to be resident (or evicted) as a unit.
> + */
> +#define N_BOS_PER_BIND	10
> +
> +static void alloc_random_size_bos_array_bind(int fd, struct
> drm_xe_engine_class_instance *hwe,
> +					     int count, uint64_t
> vram_per_process,
> +					     pthread_barrier_t *barrier, uint32_t
> flags,
> +					     unsigned int *seed)
> +{
> +	struct bo_group **leaks = NULL;
> +	uint32_t vm, exec_queue;
> +	uint64_t vram_used = 0;
> +	int i, max_batches = (count == -1) ? MAX_ALLOCATIONS : count;
> +	int n_batches = 0;
> +
> +	igt_debug("count=%d max_batches=%d vram_per_process=%llu
> flags=%x\n",
> +		  count, max_batches, (unsigned long long)vram_per_process,
> flags);
> +
> +	igt_assert(count > 0 || (flags & EVICT && flags & LEAK_BO));
> +
> +	leaks = malloc(sizeof(*leaks) * max_batches);
> +	igt_assert(leaks);
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	exec_queue =  xe_exec_queue_create(fd, vm, hwe, 0);
> +
> +	for (i = 0; i < count || vram_used < vram_per_process; ++i) {
> +		uint64_t sizes[N_BOS_PER_BIND];
> +		struct bo_alloc *bos;
> +		int j;
> +
> +		for (j = 0; j < N_BOS_PER_BIND; ++j)
> +			sizes[j] = alloc_sizes[rand_r(seed) % N_ALLOC_SIZES];
> +
> +		igt_assert_f(i < max_batches, "Failed to reach %llu bytes of
> VRAM pressure "
> +			     " after %d batches (currently reached %llu bytes)\n",
> +			     (unsigned long long)vram_per_process, max_batches,
> +			     (unsigned long long)vram_used);
> +
> +		bos = test_alloc_sizes(fd, vm, exec_queue, hwe->gt_id, sizes,
> +				       N_BOS_PER_BIND, flags,
> BO_BIND_BASE_ADDR);
> +		if (bos) {
> +			leaks[i] = malloc(sizeof(*leaks[i]));
> +			igt_assert(leaks[i]);
> +
> +			leaks[i]->bos = bos;
> +			leaks[i]->n_bos = N_BOS_PER_BIND;
> +			n_batches++;
> +
> +			for (j = 0; j < N_BOS_PER_BIND; ++j)
> +				vram_used += bos[j].bo_size;
> +		} else {
> +			leaks[i] = NULL;
> +		}
> +	}
> +
> +	if (barrier)
> +		pthread_barrier_wait(barrier);
> +
> +	check_leak_multi_group(fd, vm, leaks, n_batches, flags);

It should be i instead of n_batches as if it goes else case in one of the case then that is not counted.
check_leak_multi_group(fd, vm, leaks, i, flags);
Replaced i with n_batches.
> +
> +	xe_exec_queue_destroy(fd, exec_queue);
> +	xe_vm_destroy(fd, vm);
> +	free(leaks);
> +}
> +
>  static void run_gt_dynamic_subtests(int fd, const struct test_case *t)  {
>  	struct drm_xe_engine_class_instance *hwe; @@ -644,6 +810,13 @@ 
> static void run_gt_dynamic_subtests(int fd, const struct test_case *t)
>  			case TYPE_RANDOM_SIZE:
>  				alloc_rand_size_bos(fd, hwe, t->count, 0, NULL,
> t->flags);
>  				break;
> +			case TYPE_ARRAY_BIND: {
> +				unsigned int seed = hwe->gt_id + 1;
> +
> +				alloc_random_size_bos_array_bind(fd, hwe, t-
> >count, 0, NULL,
> +								 t->flags,
> &seed);
> +				break;
> +			}
>  			default:
>  				break;
> 
> @@ -673,6 +846,9 @@ static const struct test_case test_matrix[] = {
>  	{ "rand-sizes-10", 10, 0, TYPE_RANDOM_SIZE, false },
>  	{ "rand-sizes-100", 100, 0, TYPE_RANDOM_SIZE, false },
>  	{ "rand-sizes-100-unaligned", 100, UNALIGNED, TYPE_RANDOM_SIZE, 
> false },
> +	{ "array-binds-rand-sizes-10", 10, ARRAY_BIND, TYPE_ARRAY_BIND, true
> },
> +	{ "array-binds-rand-sizes-10-unaligned", 10,  ARRAY_BIND | 
> +UNALIGNED,
> TYPE_ARRAY_BIND,
> +	  true },
>  };
> 
>  int igt_main()
> @@ -690,6 +866,7 @@ int igt_main()
>  		switch (t->type) {
>  		case TYPE_ALL_SIZES:
>  		case TYPE_RANDOM_SIZE:
> +		case TYPE_ARRAY_BIND:
>  			igt_subtest_with_dynamic_f("%s", t->name)
>  				run_gt_dynamic_subtests(fd, t);
>  		}
> --
> 2.52.0