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From: Tushar Dave <tdave@nvidia.com>
To: qemu-devel@nongnu.org
Cc: mst@redhat.com, philmd@oss.qualcomm.com, zhao1.liu@intel.com,
	yishaih@nvidia.com, alwilliamson@nvidia.com, jgg@nvidia.com,
	skolothumtho@nvidia.com
Subject: [PATCH 0/3] pcie/acs: configurable ACS capabilities for root and downstream ports
Date: Tue, 22 Sep 2026 16:50:05 -0500	[thread overview]
Message-ID: <20260922215008.2554402-1-tdave@nvidia.com> (raw)

This series adds an 'acs-ctrl' property to PCIe root ports and downstream
ports, letting the hypervisor expose a specific PCIe ACS (Access Control
Services) configuration to the guest instead of QEMU always advertising
every ACS capability the port structurally supports.

This matters for P2P (peer-to-peer) topologies such as GPUDirect RDMA,
where the actual ACS configuration in effect must match what the host
side is doing -- otherwise the guest sees a topology/configuration that
doesn't reflect reality, which is undefined behavior and can fail either
in software or in hardware.

Patch 1 adds the missing ACS capability to xio3130 downstream ports
(previously only root ports exposed one), gated behind a new
'x-pcie-acs' property so older machine types can disable it via
hw_compat and preserve migration compatibility.

Patch 2 introduces the 'acs-ctrl' property itself on both root and
downstream ports, so the configured value -- not just the maximal
capability set -- is what gets exposed to the guest.

Patch 3 makes the ACS Control register read-only to the guest once
'acs-ctrl' has been explicitly configured, so a guest OS doing normal
PCIe programming can't silently override the host-configured ACS
state. An explicitly configured value of 0 is treated the same as any
other configured value (locked), distinct from the property never
being set at all (which stays guest-writable, unchanged from current
behavior).

Tushar Dave (2):
  xio3130_downstream: Add ACS support for downstream PCIe ports
  hw/pci: Make ACS Control read-only to guests

Yishai Hadas (1):
  hw/pci: Expose ACS ctrl on Guest as configured by the HYP

 hw/core/machine.c                  |  1 +
 hw/pci-bridge/pcie_root_port.c     | 11 +++++-
 hw/pci-bridge/xio3130_downstream.c | 14 +++++++
 hw/pci/pci.c                       |  2 +
 hw/pci/pcie.c                      | 61 ++++++++++++++++++++++++++++--
 include/hw/pci/pci.h               |  3 ++
 include/hw/pci/pcie.h              |  9 +++--
 include/hw/pci/pcie_port.h         |  2 +
 8 files changed, 94 insertions(+), 9 deletions(-)

-- 
2.34.1



             reply	other threads:[~2026-09-22 21:55 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 21:50 Tushar Dave [this message]
2026-09-22 21:50 ` [PATCH 1/3] xio3130_downstream: Add ACS support for downstream PCIe ports Tushar Dave
2026-10-02 10:38   ` Shameer Kolothum Thodi
2026-10-02 16:35     ` Tushar Dave
2026-09-22 21:50 ` [PATCH 2/3] hw/pci: Expose ACS ctrl on Guest as configured by the HYP Tushar Dave
2026-10-02 11:08   ` Shameer Kolothum Thodi
2026-09-22 21:50 ` [PATCH 3/3] hw/pci: Make ACS Control read-only to guests Tushar Dave
2026-10-02 11:39   ` Shameer Kolothum Thodi

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