[PATCH 1/3] xio3130_downstream: Add ACS support for downstream PCIe ports

[Tushar Dave <tdave@nvidia.com>]

When a PASID-capable device is added behind the PCIe downstream port,
for example, an Nvidia GPU, the PCIe downstream ports must expose ACS
capability otherwise PASID won't get enabled.

In addition, the other use case is GPUDirect RDMA using Data Direct
that must require special ACS controls at the PCIe downstream ports
for P2P communication.

Gate it behind a new x-pcie-acs property (default on), following the
x-pcie-* compat-bit convention (x-pcie-ext-tag/x-pcie-err-unc-mask/
x-pcie-ari-nextfn-1), so older machine types can disable it via
hw_compat to preserve migration compatibility.

Signed-off-by: Tushar Dave <tdave@nvidia.com>
---
 hw/core/machine.c                  | 1 +
 hw/pci-bridge/xio3130_downstream.c | 7 +++++++
 hw/pci/pci.c                       | 2 ++
 include/hw/pci/pci.h               | 3 +++
 4 files changed, 13 insertions(+)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index 92f7be52a1..4fd48f594f 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -43,6 +43,7 @@
 GlobalProperty hw_compat_11_1[] = {
     { "sysbus-ehci-usb", "x-migrate-fetch-addr-64bit", "off" },
     { "pci-ehci-usb", "x-migrate-fetch-addr-64bit", "off" },
+    { TYPE_PCI_DEVICE, "x-pcie-acs", "off" }, /* Added in 11.2 */
 };
 const size_t hw_compat_11_1_len = G_N_ELEMENTS(hw_compat_11_1);
 
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 0c3fed3053..87ba30eb36 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -40,6 +40,8 @@
 #define XIO3130_SSVID_SSID              0
 #define XIO3130_EXP_OFFSET              0x90
 #define XIO3130_AER_OFFSET              0x100
+#define XIO3130_ACS_OFFSET \
+    (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
 
 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
                                          uint32_t val, int len)
@@ -60,6 +62,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)
     pcie_cap_deverr_reset(d);
     pcie_cap_slot_reset(d);
     pcie_cap_arifwd_reset(d);
+    pcie_acs_reset(d);
     pci_bridge_reset(qdev);
 }
 
@@ -111,6 +114,10 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
         goto err;
     }
 
+    if (d->cap_present & QEMU_PCIE_CAP_ACS) {
+        pcie_acs_init(d, XIO3130_ACS_OFFSET);
+    }
+
     return;
 
 err:
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 0efb4eb4bb..807729ca75 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -105,6 +105,8 @@ static const Property pci_props[] = {
     DEFINE_PROP_STRING("sriov-pf", PCIDevice, sriov_pf),
     DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present,
                     QEMU_PCIE_EXT_TAG_BITNR, true),
+    DEFINE_PROP_BIT("x-pcie-acs", PCIDevice, cap_present,
+                    QEMU_PCIE_ACS_BITNR, true),
     { .name = "busnr", .info = &prop_pci_busnr },
 };
 
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index f2448e941a..dd52b9639e 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -231,6 +231,9 @@ enum {
     QEMU_PCI_CAP_PM = (1 << QEMU_PCI_CAP_PM_BITNR),
 #define QEMU_PCI_SKIP_RESET_ON_CPR_BITNR 15
     QEMU_PCI_SKIP_RESET_ON_CPR = (1 << QEMU_PCI_SKIP_RESET_ON_CPR_BITNR),
+    /* PCIe ACS (Access Control Services) extended capability present */
+#define QEMU_PCIE_ACS_BITNR 16
+    QEMU_PCIE_CAP_ACS = (1 << QEMU_PCIE_ACS_BITNR),
 };
 
 typedef struct PCIINTxRoute {
-- 
2.34.1