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From: sashiko-bot@kernel.org
To: tze.yee.ng@altera.com
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
Date: Wed, 23 Sep 2026 08:30:16 +0000	[thread overview]
Message-ID: <20260923083017.565C91F00893@smtp.kernel.org> (raw)
In-Reply-To: <096868737ae11bd457ec791099dcfbec775d23ad.1790151203.git.tze.yee.ng@altera.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt: mmc: cdns,ddr50-* properties undocumented and unused
--

commit 980c0e02eef0135ea601c44b02d3683b9aeff804
Author: Tze Yee Ng <tze.yee.ng@altera.com>

arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc

Add the Cadence SD6HC DDR50 read-path tuning properties to the shared
Agilex5 sdmmc node.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 5f22e6d7ab858..dc25b7382a29f 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -322,6 +322,8 @@ sdmmc: mmc@10808000 {
>  			resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>,
>  				 <&rst SDMMC_OCP_RESET>;
>  			reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
> +			cdns,ddr50-use-lpbk-dqs = <0>;
> +			cdns,ddr50-read-dqs-delay = <96>;

[Severity: Medium]
Are these cdns,ddr50-* properties documented in the device tree bindings or
supported by the driver?

Adding undocumented properties to the device tree without accompanying binding
documentation and driver support creates dead code and causes dtbs_check schema
validation errors, since the corresponding binding (cdns,sd6hc.yaml) enforces
unevaluatedProperties: false.

>  
>  			status = "disabled";
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1790151203.git.tze.yee.ng@altera.com?part=1

  reply	other threads:[~2026-09-23  8:30 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-23  8:22 [PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK tze.yee.ng
2026-09-23  8:22 ` [PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc tze.yee.ng
2026-09-23  8:30   ` sashiko-bot [this message]
2026-10-05 13:58   ` Dinh Nguyen
2026-09-23  8:22 ` [PATCH 2/6] arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK tze.yee.ng
2026-09-23  8:22 ` [PATCH 3/6] arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC tze.yee.ng
2026-09-23  8:22 ` [PATCH 4/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular tze.yee.ng
2026-09-23  8:30   ` sashiko-bot
2026-09-23  8:22 ` [PATCH 5/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B tze.yee.ng
2026-09-23  8:22 ` [PATCH 6/6] arm64: dts: socfpga: agilex3: enable SD card on SoCDK tze.yee.ng
2026-10-05 14:20 ` [PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK Dinh Nguyen

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