From: sashiko-bot@kernel.org
To: tze.yee.ng@altera.com
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 4/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
Date: Wed, 23 Sep 2026 08:30:52 +0000 [thread overview]
Message-ID: <20260923083053.27A861F000FF@smtp.kernel.org> (raw)
In-Reply-To: <8a7cb87c7afbe8e1d6d0801658bfa6615c030c66.1790151203.git.tze.yee.ng@altera.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dtbs_check failure: unparsed cdns,ddr50-phony-dqs-timing property
--
commit 856f28d1f721f596d93f5b3cac3f410afa5e6dc8
Author: Tze Yee Ng <tze.yee.ng@altera.com>
arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
This commit enables the micro-SD slot on the Agilex5 SoCDK modular board
by adding regulators, the PCA9535 expander, and configuring the sdmmc node.
> - Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I
> support, wire up the vmmc/vqmmc supplies, and set the board's
> DDR50 phony DQS timing.
Is the claim about setting the DDR50 phony DQS timing accurate?
The added devicetree property doesn't appear to be parsed by the host driver,
meaning this might not actually set the board's timing as intended.
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
> index a2b707ae6e9e4..7b44c24412c24 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
[ ... ]
> @@ -61,6 +79,32 @@ emac2_phy0: ethernet-phy@0 {
[ ... ]
> +&sdmmc {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + disable-wp;
> + max-frequency = <200000000>;
> + no-mmc;
> + sd-uhs-ddr50;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vmmc_reg>;
> + vqmmc-supply = <&vqmmc_io_reg>;
> + cdns,ddr50-phony-dqs-timing = <0>;
[Severity: Low]
Does this property actually configure the hardware?
It appears cdns,ddr50-phony-dqs-timing does not exist in any Cadence SDHCI
bindings and is completely unparsed by the driver in
drivers/mmc/host/sdhci-cadence-phy-v6.c.
Since Cadence devicetree schemas strictly prohibit unevaluated properties, will
this trigger dtbs_check validation errors when building the devicetree? It
looks like the driver manages phony DQS logic internally, making this property
dead code with no functional runtime impact.
> +
> + status = "okay";
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1790151203.git.tze.yee.ng@altera.com?part=4
next prev parent reply other threads:[~2026-09-23 8:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 8:22 [PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK tze.yee.ng
2026-09-23 8:22 ` [PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc tze.yee.ng
2026-09-23 8:30 ` sashiko-bot
2026-10-05 13:58 ` Dinh Nguyen
2026-09-23 8:22 ` [PATCH 2/6] arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK tze.yee.ng
2026-09-23 8:22 ` [PATCH 3/6] arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC tze.yee.ng
2026-09-23 8:22 ` [PATCH 4/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular tze.yee.ng
2026-09-23 8:30 ` sashiko-bot [this message]
2026-09-23 8:22 ` [PATCH 5/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B tze.yee.ng
2026-09-23 8:22 ` [PATCH 6/6] arm64: dts: socfpga: agilex3: enable SD card on SoCDK tze.yee.ng
2026-10-05 14:20 ` [PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK Dinh Nguyen
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