[linux-next:master 5416/9480] drivers/memory/tegra/tegra264.c:964:7-28: opportunity for str_write_read(value & fault -> rw_bit)

[linux-next:master 5416/9480] drivers/memory/tegra/tegra264.c:964:7-28: opportunity for str_write_read(value & fault -> rw_bit)

[kernel test robot]

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
TO: Ketan Patil <ketanp@nvidia.com>
CC: Krzysztof Kozlowski <krzk@kernel.org>

Hi Ketan,

FYI, the error/warning was bisected to this commit, please ignore it if it's irrelevant.

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   3d7783543c2646af69ad65825e810060494bea21
commit: f4e16143420f4021431cc652ebd71e176267ecbc [5416/9480] memory: tegra: Refactor Tegra264 mc-err code
:::::: branch date: 7 hours ago
:::::: commit date: 9 days ago
config: arm64-randconfig-r2107-20260924 (https://download.01.org/0day-ci/archive/20260924/202609240937.ZhKteWVi-lkp@intel.com/config)
compiler: clang version 24.0.0git (https://github.com/llvm/llvm-project 7e4b8ae111298941e0c31052a7124ab36f5365b5)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Julia Lawall <julia.lawall@inria.fr>
| Closes: https://lore.kernel.org/r/202609240937.ZhKteWVi-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/memory/tegra/tegra264.c:964:7-28: opportunity for str_write_read(value & fault -> rw_bit)

vim +964 drivers/memory/tegra/tegra264.c

82169065ffb075 Ketan Patil 2026-02-26  924  
f4e16143420f40 Ketan Patil 2026-09-03  925  static void tegra264_mc_report_fault(struct tegra_mc *mc, u32 channel,
f4e16143420f40 Ketan Patil 2026-09-03  926  				     unsigned int interrupt,
f4e16143420f40 Ketan Patil 2026-09-03  927  				     const struct tegra264_mc_fault *fault)
f4e16143420f40 Ketan Patil 2026-09-03  928  {
f4e16143420f40 Ketan Patil 2026-09-03  929  	const char *client = "unknown", *desc = "NA";
f4e16143420f40 Ketan Patil 2026-09-03  930  	u32 value, client_id, status1 = 0;
f4e16143420f40 Ketan Patil 2026-09-03  931  	phys_addr_t addr = 0;
f4e16143420f40 Ketan Patil 2026-09-03  932  	unsigned int i;
f4e16143420f40 Ketan Patil 2026-09-03  933  	u8 type;
82169065ffb075 Ketan Patil 2026-02-26  934  
f4e16143420f40 Ketan Patil 2026-09-03  935  	value = mc_ch_readl(mc, channel, fault->status_reg);
82169065ffb075 Ketan Patil 2026-02-26  936  
f4e16143420f40 Ketan Patil 2026-09-03  937  	if (fault->addr_hi_reg) {
f4e16143420f40 Ketan Patil 2026-09-03  938  		addr = mc_ch_readl(mc, channel, fault->addr_hi_reg);
f4e16143420f40 Ketan Patil 2026-09-03  939  	} else if (fault->status1_reg) {
f4e16143420f40 Ketan Patil 2026-09-03  940  		status1 = mc_ch_readl(mc, channel, fault->status1_reg);
f4e16143420f40 Ketan Patil 2026-09-03  941  		addr = (status1 >> fault->addr_hi_shift) & fault->addr_hi_mask;
82169065ffb075 Ketan Patil 2026-02-26  942  	} else {
f4e16143420f40 Ketan Patil 2026-09-03  943  		addr = (value >> fault->addr_hi_shift) & fault->addr_hi_mask;
82169065ffb075 Ketan Patil 2026-02-26  944  	}
82169065ffb075 Ketan Patil 2026-02-26  945  
82169065ffb075 Ketan Patil 2026-02-26  946  	addr <<= 32;
f4e16143420f40 Ketan Patil 2026-09-03  947  	addr |= mc_ch_readl(mc, channel, fault->addr_reg);
82169065ffb075 Ketan Patil 2026-02-26  948  
82169065ffb075 Ketan Patil 2026-02-26  949  	client_id = value & mc->soc->client_id_mask;
82169065ffb075 Ketan Patil 2026-02-26  950  	for (i = 0; i < mc->soc->num_clients; i++) {
82169065ffb075 Ketan Patil 2026-02-26  951  		if (mc->soc->clients[i].id == client_id) {
82169065ffb075 Ketan Patil 2026-02-26  952  			client = mc->soc->clients[i].name;
82169065ffb075 Ketan Patil 2026-02-26  953  			break;
82169065ffb075 Ketan Patil 2026-02-26  954  		}
82169065ffb075 Ketan Patil 2026-02-26  955  	}
82169065ffb075 Ketan Patil 2026-02-26  956  
f4e16143420f40 Ketan Patil 2026-09-03  957  	if (fault->type_names) {
f4e16143420f40 Ketan Patil 2026-09-03  958  		type = (value & fault->type_mask) >> fault->type_shift;
f4e16143420f40 Ketan Patil 2026-09-03  959  		desc = fault->type_names[type];
82169065ffb075 Ketan Patil 2026-02-26  960  	}
82169065ffb075 Ketan Patil 2026-02-26  961  
82169065ffb075 Ketan Patil 2026-02-26  962  	dev_err_ratelimited(mc->dev, "%s: %s %s @%pa: %s (%s)\n",
f4e16143420f40 Ketan Patil 2026-09-03  963  			    client, value & fault->sec_bit ? "secure" : "non-secure",
f4e16143420f40 Ketan Patil 2026-09-03 @964  			    value & fault->rw_bit ? "write" : "read", &addr,
f4e16143420f40 Ketan Patil 2026-09-03  965  			    tegra_mc_status_names[interrupt] ?: "unknown", desc);
f4e16143420f40 Ketan Patil 2026-09-03  966  
f4e16143420f40 Ketan Patil 2026-09-03  967  	if (fault->status1_reg)
82169065ffb075 Ketan Patil 2026-02-26  968  		dev_err_ratelimited(mc->dev, "gsc_apr_id=%u gsc_co_apr_id=%u\n",
f4e16143420f40 Ketan Patil 2026-09-03  969  				    (status1 >> ERR_GENERALIZED_APERTURE_ID_SHIFT) &
f4e16143420f40 Ketan Patil 2026-09-03  970  				    ERR_GENERALIZED_APERTURE_ID_MASK,
f4e16143420f40 Ketan Patil 2026-09-03  971  				    (status1 >> ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT) &
f4e16143420f40 Ketan Patil 2026-09-03  972  				    ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK);
f4e16143420f40 Ketan Patil 2026-09-03  973  }
f4e16143420f40 Ketan Patil 2026-09-03  974  

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