[PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Aniket Limaye]

Add new compatible and update driver to support Synopsys Advanced I2C
Controller (DWC_i2c [0]) present on TI TDA54 SoC. This is needed since
this controller differs from the existing designware i2c (DW_apb_i2c
[1]) in its register offsets and some register definitions.

The new compatible updates driver logic due to changes in register
definitions:

- The new register offsets are handled by first refactoring the driver
  to use a map of register IDs to their offsets.
- Similarly, also update the driver to use an updated CON-register
  bitfield definition.
- Interrupts are acknowledged by writing a bitmask to a single CLR_INTR
  register instead of reading N dedicated CLR_* registers;
  i2c_dw_ack_intr() picks the right method based on dev->flags.
- One HCNT/LCNT register pair is shared between standard and fast speed
  instead of having one pair each; i2c_dw_write_timings() writes
  whichever value set matches the configured speed.
- No COMP_PARAM_1 register, so FIFO depth and high-speed-mode support
  can't be autodetected: FIFO depth now comes from the required
  snps,tx-fifo-depth/snps,rx-fifo-depth DT properties, and the
  high-speed capability check is skipped.
- No defined CON.RESTART_EN bit; treat it as always set.
- TDA54 SoC does not support SMBus, so skip accesses to those registers.

[0]: DWC_i2c_reference.pdf
[1]: DW_apb_i2c_databook.pdf

Signed-off-by: Aniket Limaye <a-limaye@ti.com>
---
Changes in v3:
- [PATCH 2/3] Revert to special handling for the max_register in regmap
  for MODEL_AMD_NAVI_GPU instead of unconditionally including
  AMD_UCSI_INTR_REG in the legal regmap range. (sashiko)
- Link to v2: https://lore.kernel.org/r/20260925-tda54-upstream-i2c-v2-0-261785e58493@ti.com

Changes in v2:
- Rename compatible/flag: snps,dwc-i2c -> ti,tda54-i2c,
  MODEL_DWC_I2C -> MODEL_TI_TDA54.
- Move the Reg ID -> Offset mapping inside the regmap functions such
  that existing calls to reg_read/write are unaltered. This does change
  the reg_read()/reg_write() functions to take reg IDs as input rather
  than their physical offsets, which also requires updates to the
  xe_i2c.c driver to handle the same mapping.
- Remove i2c_dwc_has_smbus(); just skip the SMBUS_INTR_MASK write under
  MODEL_TI_TDA54.
- Link to v1: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-0-b0b9f77be18b@ti.com

---
Aniket Limaye (3):
      dt-bindings: i2c: dw: Add ti,tda54-i2c compatible
      i2c: designware: Support per-variant reg/bit offsets and intr handling
      i2c: designware: Add ti,tda54-i2c support

 .../bindings/i2c/snps,designware-i2c.yaml          |  33 ++++
 drivers/gpu/drm/xe/regs/xe_i2c_regs.h              |   3 +-
 drivers/i2c/busses/i2c-designware-amdisp.c         |   1 +
 drivers/i2c/busses/i2c-designware-common.c         | 193 ++++++++++++++++++---
 drivers/i2c/busses/i2c-designware-core.h           |  70 +++++++-
 drivers/i2c/busses/i2c-designware-master.c         |  78 +++++----
 drivers/i2c/busses/i2c-designware-pcidrv.c         |   2 +
 drivers/i2c/busses/i2c-designware-platdrv.c        |   3 +
 drivers/i2c/busses/i2c-designware-slave.c          |  26 +--
 include/linux/designware_i2c.h                     | 137 ++++++++++-----
 10 files changed, 432 insertions(+), 114 deletions(-)
---
base-commit: 587858367581b9c55c3690f4e63382ad622719d4
change-id: 20260919-tda54-upstream-i2c-d0c67f16b4fc

Best regards,
-- 
Aniket Limaye <a-limaye@ti.com>

[PATCH v3 1/3] dt-bindings: i2c: dw: Add ti,tda54-i2c compatible

[Aniket Limaye]

Add the "ti,tda54-i2c" compatible for Synopsys Advanced I2C Controller
(DWC_i2c) present on TDA54 SoC. Compared to the existing
"snps,designware-i2c" (DW_apb_i2c), it broadly differs in its register
offsets and some bit fields, requiring changes to interrupt handling,
timing handling, etc.

Unlike DW_apb_i2c, this IP has no COMP_PARAM_1 register to autodetect
the FIFO depth from, so add snps,tx-fifo-depth and
snps,rx-fifo-depth as required properties.

Signed-off-by: Aniket Limaye <a-limaye@ti.com>

---

Changes in v2:
- Rename snps,dwc-i2c to ti,tda54-i2c
- Link to v1: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-1-b0b9f77be18b@ti.com/
---
 .../bindings/i2c/snps,designware-i2c.yaml          | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 467bdcbb8538..80a9376d6de7 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -21,12 +21,23 @@ allOf:
       properties:
         reg:
           maxItems: 1
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,tda54-i2c
+    then:
+      required:
+        - snps,tx-fifo-depth
+        - snps,rx-fifo-depth
 
 properties:
   compatible:
     oneOf:
       - description: Generic Synopsys DesignWare I2C controller
         const: snps,designware-i2c
+      - description: TI TDA54 SoC I2C controller (Synopsys DWC_i2c IP)
+        const: ti,tda54-i2c
       - description: Renesas RZ/N1D I2C controller
         items:
           - const: renesas,r9a06g032-i2c  # RZ/N1D
@@ -121,6 +132,18 @@ properties:
       low period of SCL line.
     type: boolean
 
+  snps,tx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The depth of the hardware TX FIFO. Required on the ti,tda54-i2c
+      variant, where fifo depth cannot be autodetected.
+
+  snps,rx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The depth of the hardware RX FIFO. Required on the ti,tda54-i2c
+      variant, where fifo depth cannot be autodetected.
+
 unevaluatedProperties: false
 
 required:
@@ -172,4 +195,14 @@ examples:
       interrupts = <8>;
       clocks = <&ahb_clk>;
     };
+  - |
+    i2c@53b00000 {
+      compatible = "ti,tda54-i2c";
+      reg = <0x53b00000 0x1000>;
+      interrupts = <166>;
+      clocks = <&sysclk>;
+      clock-frequency = <100000>;
+      snps,tx-fifo-depth = <32>;
+      snps,rx-fifo-depth = <32>;
+    };
 ...

-- 
2.53.0

Re: [PATCH v3 1/3] dt-bindings: i2c: dw: Add ti,tda54-i2c compatible

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3127 bytes --]

On Fri, Sep 25, 2026 at 12:26:28PM +0530, Aniket Limaye wrote:
> Add the "ti,tda54-i2c" compatible for Synopsys Advanced I2C Controller
> (DWC_i2c) present on TDA54 SoC. Compared to the existing
> "snps,designware-i2c" (DW_apb_i2c), it broadly differs in its register
> offsets and some bit fields, requiring changes to interrupt handling,
> timing handling, etc.
> 
> Unlike DW_apb_i2c, this IP has no COMP_PARAM_1 register to autodetect
> the FIFO depth from, so add snps,tx-fifo-depth and
> snps,rx-fifo-depth as required properties.
> 
> Signed-off-by: Aniket Limaye <a-limaye@ti.com>
> 
> ---
> 
> Changes in v2:
> - Rename snps,dwc-i2c to ti,tda54-i2c
> - Link to v1: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-1-b0b9f77be18b@ti.com/
> ---
>  .../bindings/i2c/snps,designware-i2c.yaml          | 33 ++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
> index 467bdcbb8538..80a9376d6de7 100644
> --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
> @@ -21,12 +21,23 @@ allOf:
>        properties:
>          reg:
>            maxItems: 1
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: ti,tda54-i2c
> +    then:
> +      required:
> +        - snps,tx-fifo-depth
> +        - snps,rx-fifo-depth
>  
>  properties:
>    compatible:
>      oneOf:
>        - description: Generic Synopsys DesignWare I2C controller
>          const: snps,designware-i2c
> +      - description: TI TDA54 SoC I2C controller (Synopsys DWC_i2c IP)
> +        const: ti,tda54-i2c
>        - description: Renesas RZ/N1D I2C controller
>          items:
>            - const: renesas,r9a06g032-i2c  # RZ/N1D
> @@ -121,6 +132,18 @@ properties:
>        low period of SCL line.
>      type: boolean
>  
> +  snps,tx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      The depth of the hardware TX FIFO. Required on the ti,tda54-i2c
> +      variant, where fifo depth cannot be autodetected.

Why is the compatible not sufficient to get this information from?
Does it vary across controllers on the same device?

> +
> +  snps,rx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      The depth of the hardware RX FIFO. Required on the ti,tda54-i2c
> +      variant, where fifo depth cannot be autodetected.
> +
>  unevaluatedProperties: false
>  
>  required:
> @@ -172,4 +195,14 @@ examples:
>        interrupts = <8>;
>        clocks = <&ahb_clk>;
>      };
> +  - |
> +    i2c@53b00000 {
> +      compatible = "ti,tda54-i2c";
> +      reg = <0x53b00000 0x1000>;
> +      interrupts = <166>;
> +      clocks = <&sysclk>;
> +      clock-frequency = <100000>;
> +      snps,tx-fifo-depth = <32>;
> +      snps,rx-fifo-depth = <32>;
> +    };
>  ...
> 
> -- 
> 2.53.0
> 

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[PATCH v3 2/3] i2c: designware: Support per-variant reg/bit offsets and intr handling

[Aniket Limaye]

Every DW_IC_* register offset and CON-register bit position is currently
baked in as a compile-time constant, which only works while there is a
single register layout.

- Make DW_IC_* a logical enum (enum dw_ic_reg_id) and the regmap
  internally translates to physical offsets.
- Add a struct to hold the CON-register bitfield positions.
- Fold the read-to-clear interrupt-acknowledgment pattern into a new
  i2c_dw_ack_intr() helper, driven by a per-variant dev->intr_clr[].

All of these are selected at probe time via the new
i2c_dw_select_variant().

Only one variant exists at this point (DW_apb_i2c), so this is a
mechanical, behavior-preserving change. It lays the groundwork for
adding a second register layout without duplicating the whole driver.

Signed-off-by: Aniket Limaye <a-limaye@ti.com>

---

Changes in v3:
- Revert to special handling for the max_register in regmap for
  MODEL_AMD_NAVI_GPU instead of unconditionally including
  AMD_UCSI_INTR_REG in the legal regmap range.
- Link to v2: https://lore.kernel.org/all/20260925-tda54-upstream-i2c-v2-2-261785e58493@ti.com/

Changes in v2:
- Move the Reg ID -> Offset mapping inside the regmap functions such
  that existing calls to reg_read/write are unaltered. This does change
  the reg_read()/reg_write() functions to take reg IDs as input rather
  than their physical offsets, which also requires updates to the
  xe_i2c.c driver to handle the same mapping.
- Link to v1: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-2-b0b9f77be18b@ti.com/
---
 drivers/gpu/drm/xe/regs/xe_i2c_regs.h       |   3 +-
 drivers/i2c/busses/i2c-designware-amdisp.c  |   1 +
 drivers/i2c/busses/i2c-designware-common.c  |  71 +++++++++++---
 drivers/i2c/busses/i2c-designware-core.h    |  52 ++++++++++-
 drivers/i2c/busses/i2c-designware-master.c  |  54 +++++------
 drivers/i2c/busses/i2c-designware-pcidrv.c  |   2 +
 drivers/i2c/busses/i2c-designware-platdrv.c |   2 +
 drivers/i2c/busses/i2c-designware-slave.c   |  26 +++---
 include/linux/designware_i2c.h              | 137 +++++++++++++++++++---------
 9 files changed, 252 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
index 37550e4a20f8..86449efb4a98 100644
--- a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h
@@ -2,6 +2,7 @@
 #ifndef _XE_I2C_REGS_H_
 #define _XE_I2C_REGS_H_
 
+#include <linux/designware_i2c.h>
 #include <linux/pci_regs.h>
 
 #include "xe_reg_defs.h"
@@ -20,6 +21,6 @@
 #define I2C_CONFIG_CMD			XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND)
 #define I2C_CONFIG_PMCSR		XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84)
 
-#define I2C_REG(reg)			XE_REG((reg) + I2C_MEM_SPACE_OFFSET)
+#define I2C_REG(reg)			XE_REG(dw_i2c_reg_offsets[reg] + I2C_MEM_SPACE_OFFSET)
 
 #endif /* _XE_I2C_REGS_H_ */
diff --git a/drivers/i2c/busses/i2c-designware-amdisp.c b/drivers/i2c/busses/i2c-designware-amdisp.c
index 9f0ec0fae6f2..f7aa075c9977 100644
--- a/drivers/i2c/busses/i2c-designware-amdisp.c
+++ b/drivers/i2c/busses/i2c-designware-amdisp.c
@@ -46,6 +46,7 @@ static int amd_isp_dw_i2c_plat_probe(struct platform_device *pdev)
 	isp_i2c_dev->flags |= ACCESS_POLLING;
 	platform_set_drvdata(pdev, isp_i2c_dev);
 
+	i2c_dw_select_variant(isp_i2c_dev);
 	isp_i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(isp_i2c_dev->base))
 		return dev_err_probe(&pdev->dev, PTR_ERR(isp_i2c_dev->base),
diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index a1eca6cd4b75..bd25b9c582c1 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -72,11 +72,55 @@ static const char *const abort_sources[] = {
 		"incorrect slave-transmitter mode configuration",
 };
 
+static const struct dw_i2c_con_bits dw_i2c_con_bits = {
+	.master			= DW_IC_CON_MASTER,
+	.speed_std		= DW_IC_CON_SPEED_STD,
+	.speed_fast		= DW_IC_CON_SPEED_FAST,
+	.speed_high		= DW_IC_CON_SPEED_HIGH,
+	.speed_mask		= DW_IC_CON_SPEED_MASK,
+	.bit10_slave		= DW_IC_CON_10BITADDR_SLAVE,
+	.bit10_master		= DW_IC_CON_10BITADDR_MASTER,
+	.restart_en		= DW_IC_CON_RESTART_EN,
+	.slave_disable		= DW_IC_CON_SLAVE_DISABLE,
+	.stop_det_ifaddressed	= DW_IC_CON_STOP_DET_IFADDRESSED,
+	.tx_empty_ctrl		= DW_IC_CON_TX_EMPTY_CTRL,
+	.rx_fifo_full_hld_ctrl	= DW_IC_CON_RX_FIFO_FULL_HLD_CTRL,
+	.bus_clear_ctrl		= DW_IC_CON_BUS_CLEAR_CTRL,
+};
+
+/* "snps,designware-i2c": dedicated read-to-clear register ID per logical interrupt */
+static const u32 dw_i2c_intr_clr[DW_INTR_IDX_MAX] = {
+	[DW_INTR_IDX_INTR]      = DW_IC_CLR_INTR,
+	[DW_INTR_IDX_RX_UNDER]  = DW_IC_CLR_RX_UNDER,
+	[DW_INTR_IDX_RX_OVER]   = DW_IC_CLR_RX_OVER,
+	[DW_INTR_IDX_TX_OVER]   = DW_IC_CLR_TX_OVER,
+	[DW_INTR_IDX_RD_REQ]    = DW_IC_CLR_RD_REQ,
+	[DW_INTR_IDX_TX_ABRT]   = DW_IC_CLR_TX_ABRT,
+	[DW_INTR_IDX_RX_DONE]   = DW_IC_CLR_RX_DONE,
+	[DW_INTR_IDX_ACTIVITY]  = DW_IC_CLR_ACTIVITY,
+	[DW_INTR_IDX_STOP_DET]  = DW_IC_CLR_STOP_DET,
+	[DW_INTR_IDX_START_DET] = DW_IC_CLR_START_DET,
+	[DW_INTR_IDX_GEN_CALL]  = DW_IC_CLR_GEN_CALL,
+};
+
+/**
+ * i2c_dw_select_variant() - Pick the register offset table, CON-register bit
+ * layout and interrupt-ack mapping matching this device's IP variant
+ * @dev: device private data
+ */
+void i2c_dw_select_variant(struct dw_i2c_dev *dev)
+{
+	dev->regs = dw_i2c_reg_offsets;
+	dev->con_bits = &dw_i2c_con_bits;
+	dev->intr_clr = dw_i2c_intr_clr;
+}
+EXPORT_SYMBOL_GPL(i2c_dw_select_variant);
+
 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
 {
 	struct dw_i2c_dev *dev = context;
 
-	*val = readl(dev->base + reg);
+	*val = readl(dev->base + dev->regs[reg]);
 
 	return 0;
 }
@@ -85,7 +129,7 @@ static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
 {
 	struct dw_i2c_dev *dev = context;
 
-	writel(val, dev->base + reg);
+	writel(val, dev->base + dev->regs[reg]);
 
 	return 0;
 }
@@ -94,7 +138,7 @@ static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
 {
 	struct dw_i2c_dev *dev = context;
 
-	*val = swab32(readl(dev->base + reg));
+	*val = swab32(readl(dev->base + dev->regs[reg]));
 
 	return 0;
 }
@@ -103,7 +147,7 @@ static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
 {
 	struct dw_i2c_dev *dev = context;
 
-	writel(swab32(val), dev->base + reg);
+	writel(swab32(val), dev->base + dev->regs[reg]);
 
 	return 0;
 }
@@ -111,9 +155,10 @@ static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
 {
 	struct dw_i2c_dev *dev = context;
+	unsigned int offset = dev->regs[reg];
 
-	*val = readw(dev->base + reg) |
-		(readw(dev->base + reg + DW_IC_REG_STEP_BYTES) << DW_IC_REG_WORD_SHIFT);
+	*val = readw(dev->base + offset) |
+		(readw(dev->base + offset + DW_IC_REG_STEP_BYTES) << DW_IC_REG_WORD_SHIFT);
 
 	return 0;
 }
@@ -121,9 +166,10 @@ static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
 {
 	struct dw_i2c_dev *dev = context;
+	unsigned int offset = dev->regs[reg];
 
-	writew(val, dev->base + reg);
-	writew(val >> DW_IC_REG_WORD_SHIFT, dev->base + reg + DW_IC_REG_STEP_BYTES);
+	writew(val, dev->base + offset);
+	writew(val >> DW_IC_REG_WORD_SHIFT, dev->base + offset + DW_IC_REG_STEP_BYTES);
 
 	return 0;
 }
@@ -143,7 +189,7 @@ static int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
 	struct regmap_config map_cfg = {
 		.reg_bits = 32,
 		.val_bits = 32,
-		.reg_stride = 4,
+		.reg_stride = 1,
 		.disable_locking = true,
 		.reg_read = dw_reg_read,
 		.reg_write = dw_reg_write,
@@ -163,7 +209,7 @@ static int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
 	if (ret)
 		return ret;
 
-	reg = readl(dev->base + DW_IC_COMP_TYPE);
+	reg = readl(dev->base + dev->regs[DW_IC_COMP_TYPE]);
 	i2c_dw_release_lock(dev);
 
 	if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
@@ -845,7 +891,6 @@ u32 i2c_dw_func(struct i2c_adapter *adap)
 
 void i2c_dw_disable(struct dw_i2c_dev *dev)
 {
-	unsigned int dummy;
 	int ret;
 
 	ret = i2c_dw_acquire_lock(dev);
@@ -857,7 +902,7 @@ void i2c_dw_disable(struct dw_i2c_dev *dev)
 
 	/* Disable all interrupts */
 	__i2c_dw_write_intr_mask(dev, 0);
-	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
+	i2c_dw_ack_intr(dev, DW_INTR_IDX_INTR);
 
 	i2c_dw_release_lock(dev);
 }
@@ -1055,7 +1100,7 @@ void i2c_dw_shutdown(struct dw_i2c_dev *dev)
 	 * disable bit while the controller is still enabled.
 	 */
 	regmap_read(dev->map, DW_IC_CON, &con);
-	con |= DW_IC_CON_SLAVE_DISABLE;
+	con |= dev->con_bits->slave_disable;
 	regmap_write(dev->map, DW_IC_CON, con);
 
 	i2c_dw_disable(dev);
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 2c929a6e8da2..4c782594ab4e 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -43,6 +43,42 @@
 #define DW_IC_SDA_HOLD_MIN_VERS			0x3131312A /* "111*" == v1.11* */
 #define DW_IC_COMP_TYPE_VALUE			0x44570140 /* "DW" + 0x0140 */
 
+/*
+ * Bit positions within the CON register that could differ between IP
+ * variants.
+ */
+struct dw_i2c_con_bits {
+	u32 master;
+	u32 speed_std;
+	u32 speed_fast;
+	u32 speed_high;
+	u32 speed_mask;
+	u32 bit10_slave;
+	u32 bit10_master;
+	u32 restart_en;
+	u32 slave_disable;
+	u32 stop_det_ifaddressed;
+	u32 tx_empty_ctrl;
+	u32 rx_fifo_full_hld_ctrl;
+	u32 bus_clear_ctrl;
+};
+
+/* Logical interrupt IDs for i2c_dw_ack_intr() */
+enum dw_i2c_intr_idx {
+	DW_INTR_IDX_INTR,
+	DW_INTR_IDX_RX_UNDER,
+	DW_INTR_IDX_RX_OVER,
+	DW_INTR_IDX_TX_OVER,
+	DW_INTR_IDX_RD_REQ,
+	DW_INTR_IDX_TX_ABRT,
+	DW_INTR_IDX_RX_DONE,
+	DW_INTR_IDX_ACTIVITY,
+	DW_INTR_IDX_STOP_DET,
+	DW_INTR_IDX_START_DET,
+	DW_INTR_IDX_GEN_CALL,
+	DW_INTR_IDX_MAX,
+};
+
 #define DW_IC_INTR_DEFAULT_MASK			(DW_IC_INTR_RX_FULL | \
 						 DW_IC_INTR_TX_ABRT | \
 						 DW_IC_INTR_STOP_DET)
@@ -126,6 +162,9 @@ struct reset_control;
  * struct dw_i2c_dev - private i2c-designware data
  * @dev: driver model device node
  * @map: IO registers map
+ * @regs: logical-to-physical register offset table for the active IP variant
+ * @con_bits: CON register bit-layout for the active IP variant
+ * @intr_clr: logical intr number to reg table for the active IP variant
  * @sysmap: System controller registers map
  * @base: IO registers pointer
  * @ext: Extended IO registers pointer
@@ -189,6 +228,9 @@ struct reset_control;
 struct dw_i2c_dev {
 	struct device		*dev;
 	struct regmap		*map;
+	const u32		*regs;
+	const struct dw_i2c_con_bits *con_bits;
+	const u32		*intr_clr;
 	struct regmap		*sysmap;
 	void __iomem		*base;
 	void __iomem		*ext;
@@ -255,7 +297,6 @@ struct dw_i2c_dev {
  * Enable UCSI interrupt by writing 0xd at register
  * offset 0x474 specified in hardware specification.
  */
-#define AMD_UCSI_INTR_REG			0x474
 #define AMD_UCSI_INTR_EN			0xd
 
 #define TXGBE_TX_FIFO_DEPTH			4
@@ -265,6 +306,7 @@ struct i2c_dw_semaphore_callbacks {
 	int	(*probe)(struct dw_i2c_dev *dev);
 };
 
+void i2c_dw_select_variant(struct dw_i2c_dev *dev);
 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
 		    u32 tSYMBOL, u32 tf, int offset);
 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
@@ -310,6 +352,14 @@ static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev,
 		*intr_mask = dev->sw_mask;
 }
 
+/* Acknowledge a logical interrupt via dev->intr_clr[]: reg ID */
+static inline void i2c_dw_ack_intr(struct dw_i2c_dev *dev, enum dw_i2c_intr_idx intr)
+{
+	unsigned int dummy;
+
+	regmap_read(dev->map, dev->intr_clr[intr], &dummy);
+}
+
 void __i2c_dw_disable(struct dw_i2c_dev *dev);
 void i2c_dw_disable(struct dw_i2c_dev *dev);
 
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index a1bcc3797e4f..329f958ded3e 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -133,14 +133,14 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
 		fp_str, dev->fs_hcnt, dev->fs_lcnt);
 
 	/* Check is high speed possible and fall back to fast mode if not */
-	if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
-		DW_IC_CON_SPEED_HIGH) {
+	if ((dev->master_cfg & dev->con_bits->speed_mask) ==
+		dev->con_bits->speed_high) {
 		if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 			!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 			dev_err(dev->dev, "High Speed not supported!\n");
 			t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
-			dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
-			dev->master_cfg |= DW_IC_CON_SPEED_FAST;
+			dev->master_cfg &= ~dev->con_bits->speed_mask;
+			dev->master_cfg |= dev->con_bits->speed_fast;
 			dev->hs_hcnt = 0;
 			dev->hs_lcnt = 0;
 		} else if (!dev->hs_hcnt || !dev->hs_lcnt) {
@@ -200,7 +200,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 
 	/* If the slave address is ten bit address, enable 10BITADDR */
 	if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
-		ic_con = DW_IC_CON_10BITADDR_MASTER;
+		ic_con = dev->con_bits->bit10_master;
 		/*
 		 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 		 * mode has to be enabled via bit 12 of IC_TAR register.
@@ -210,7 +210,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 		ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 	}
 
-	regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
+	regmap_update_bits(dev->map, DW_IC_CON, dev->con_bits->bit10_master,
 			   ic_con);
 
 	/*
@@ -230,7 +230,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 	regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
 
 	/* Clear and enable interrupts */
-	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
+	i2c_dw_ack_intr(dev, DW_INTR_IDX_INTR);
 	__i2c_dw_write_intr_mask(dev, DW_IC_INTR_MASTER_MASK);
 }
 
@@ -399,8 +399,8 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 			 * IC_RESTART_EN are set, we must manually
 			 * set restart bit between messages.
 			 */
-			if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
-					(dev->msg_write_idx > 0))
+			if (dev->master_cfg & dev->con_bits->restart_en &&
+			    dev->msg_write_idx > 0)
 				need_restart = true;
 		}
 
@@ -574,7 +574,7 @@ i2c_dw_read(struct dw_i2c_dev *dev)
 
 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 {
-	unsigned int stat, dummy;
+	unsigned int stat;
 
 	/*
 	 * The IC_INTR_STAT register just indicates "enabled" interrupts.
@@ -603,32 +603,32 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 	 * Instead, use the separately-prepared IC_CLR_* registers.
 	 */
 	if (stat & DW_IC_INTR_RX_UNDER)
-		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RX_UNDER);
 	if (stat & DW_IC_INTR_RX_OVER)
-		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RX_OVER);
 	if (stat & DW_IC_INTR_TX_OVER)
-		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_TX_OVER);
 	if (stat & DW_IC_INTR_RD_REQ)
-		regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RD_REQ);
 	if (stat & DW_IC_INTR_TX_ABRT) {
 		/*
 		 * The IC_TX_ABRT_SOURCE register is cleared whenever
 		 * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 		 */
 		regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
-		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_TX_ABRT);
 	}
 	if (stat & DW_IC_INTR_RX_DONE)
-		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RX_DONE);
 	if (stat & DW_IC_INTR_ACTIVITY)
-		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_ACTIVITY);
 	if ((stat & DW_IC_INTR_STOP_DET) &&
 	    ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL)))
-		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_STOP_DET);
 	if (stat & DW_IC_INTR_START_DET)
-		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_START_DET);
 	if (stat & DW_IC_INTR_GEN_CALL)
-		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_GEN_CALL);
 
 	return stat;
 }
@@ -940,20 +940,20 @@ void i2c_dw_configure_master(struct dw_i2c_dev *dev)
 	if ((dev->flags & MODEL_MASK) != MODEL_AMD_NAVI_GPU)
 		dev->functionality |= I2C_FUNC_PROTOCOL_MANGLING;
 
-	dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
-			  DW_IC_CON_RESTART_EN;
+	dev->master_cfg = dev->con_bits->master | dev->con_bits->slave_disable |
+			  dev->con_bits->restart_en;
 
 	dev->mode = DW_IC_MASTER;
 
 	switch (t->bus_freq_hz) {
 	case I2C_MAX_STANDARD_MODE_FREQ:
-		dev->master_cfg |= DW_IC_CON_SPEED_STD;
+		dev->master_cfg |= dev->con_bits->speed_std;
 		break;
 	case I2C_MAX_HIGH_SPEED_MODE_FREQ:
-		dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
+		dev->master_cfg |= dev->con_bits->speed_high;
 		break;
 	default:
-		dev->master_cfg |= DW_IC_CON_SPEED_FAST;
+		dev->master_cfg |= dev->con_bits->speed_fast;
 	}
 }
 EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
@@ -1042,8 +1042,8 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev)
 	if (ret)
 		return ret;
 
-	if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL)
-		dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL;
+	if (ic_con & dev->con_bits->bus_clear_ctrl)
+		dev->master_cfg |= dev->con_bits->bus_clear_ctrl;
 
 	return i2c_dw_init_recovery_info(dev);
 }
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 468287922363..fc73106fb0f9 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -246,6 +246,8 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
 
 	pci_set_drvdata(pdev, dev);
 
+	i2c_dw_select_variant(dev);
+
 	if (controller->setup) {
 		r = controller->setup(pdev, controller);
 		if (r)
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 447af5523c2e..42b34c678146 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -156,6 +156,8 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
 	dev->flags = flags;
 	platform_set_drvdata(pdev, dev);
 
+	i2c_dw_select_variant(dev);
+
 	ret = dw_i2c_plat_request_regs(dev);
 	if (ret)
 		return ret;
diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c
index 0abcc7757b23..0985e907c9c3 100644
--- a/drivers/i2c/busses/i2c-designware-slave.c
+++ b/drivers/i2c/busses/i2c-designware-slave.c
@@ -65,7 +65,7 @@ int i2c_dw_unreg_slave(struct i2c_client *slave)
 
 static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
 {
-	unsigned int stat, dummy;
+	unsigned int stat;
 
 	/*
 	 * The IC_INTR_STAT register just indicates "enabled" interrupts.
@@ -89,23 +89,23 @@ static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
 	 * Instead, use the separately-prepared IC_CLR_* registers.
 	 */
 	if (stat & DW_IC_INTR_TX_ABRT)
-		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_TX_ABRT);
 	if (stat & DW_IC_INTR_RX_UNDER)
-		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RX_UNDER);
 	if (stat & DW_IC_INTR_RX_OVER)
-		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RX_OVER);
 	if (stat & DW_IC_INTR_TX_OVER)
-		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_TX_OVER);
 	if (stat & DW_IC_INTR_RX_DONE)
-		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_RX_DONE);
 	if (stat & DW_IC_INTR_ACTIVITY)
-		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_ACTIVITY);
 	if (stat & DW_IC_INTR_STOP_DET)
-		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_STOP_DET);
 	if (stat & DW_IC_INTR_START_DET)
-		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_START_DET);
 	if (stat & DW_IC_INTR_GEN_CALL)
-		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
+		i2c_dw_ack_intr(dev, DW_INTR_IDX_GEN_CALL);
 
 	return stat;
 }
@@ -155,7 +155,7 @@ irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev)
 
 	if (stat & DW_IC_INTR_RD_REQ) {
 		if (slave_activity) {
-			regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
+			i2c_dw_ack_intr(dev, DW_INTR_IDX_RD_REQ);
 
 			if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 				i2c_slave_event(dev->slave,
@@ -185,8 +185,8 @@ void i2c_dw_configure_slave(struct dw_i2c_dev *dev)
 
 	dev->functionality |= I2C_FUNC_SLAVE;
 
-	dev->slave_cfg = DW_IC_CON_RX_FIFO_FULL_HLD_CTRL |
-			 DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED;
+	dev->slave_cfg = dev->con_bits->rx_fifo_full_hld_ctrl |
+			 dev->con_bits->restart_en | dev->con_bits->stop_det_ifaddressed;
 }
 EXPORT_SYMBOL_GPL(i2c_dw_configure_slave);
 
diff --git a/include/linux/designware_i2c.h b/include/linux/designware_i2c.h
index 53f37f18a722..994e0e5ea623 100644
--- a/include/linux/designware_i2c.h
+++ b/include/linux/designware_i2c.h
@@ -11,48 +11,103 @@
 #include <linux/bits.h>
 
 /*
- * Registers offset
+ * Logical register IDs. Each ID is resolved to a physical offset via a
+ * per-variant table (see dw_i2c_reg_offsets[] below); regmap backends
+ * (dw_reg_read()/dw_reg_write() and the Xe I2C_REG() macro) perform that
+ * lookup so callers never need to know the real offset.
  */
-#define DW_IC_CON				0x00
-#define DW_IC_TAR				0x04
-#define DW_IC_SAR				0x08
-#define DW_IC_DATA_CMD				0x10
-#define DW_IC_SS_SCL_HCNT			0x14
-#define DW_IC_SS_SCL_LCNT			0x18
-#define DW_IC_FS_SCL_HCNT			0x1c
-#define DW_IC_FS_SCL_LCNT			0x20
-#define DW_IC_HS_SCL_HCNT			0x24
-#define DW_IC_HS_SCL_LCNT			0x28
-#define DW_IC_INTR_STAT				0x2c
-#define DW_IC_INTR_MASK				0x30
-#define DW_IC_RAW_INTR_STAT			0x34
-#define DW_IC_RX_TL				0x38
-#define DW_IC_TX_TL				0x3c
-#define DW_IC_CLR_INTR				0x40
-#define DW_IC_CLR_RX_UNDER			0x44
-#define DW_IC_CLR_RX_OVER			0x48
-#define DW_IC_CLR_TX_OVER			0x4c
-#define DW_IC_CLR_RD_REQ			0x50
-#define DW_IC_CLR_TX_ABRT			0x54
-#define DW_IC_CLR_RX_DONE			0x58
-#define DW_IC_CLR_ACTIVITY			0x5c
-#define DW_IC_CLR_STOP_DET			0x60
-#define DW_IC_CLR_START_DET			0x64
-#define DW_IC_CLR_GEN_CALL			0x68
-#define DW_IC_ENABLE				0x6c
-#define DW_IC_STATUS				0x70
-#define DW_IC_TXFLR				0x74
-#define DW_IC_RXFLR				0x78
-#define DW_IC_SDA_HOLD				0x7c
-#define DW_IC_TX_ABRT_SOURCE			0x80
-#define DW_IC_ENABLE_STATUS			0x9c
-#define DW_IC_CLR_RESTART_DET			0xa8
-#define DW_IC_SMBUS_INTR_STAT			0xc8
-#define DW_IC_SMBUS_INTR_MASK			0xcc
-#define DW_IC_CLR_SMBUS_INTR			0xd4
-#define DW_IC_COMP_PARAM_1			0xf4
-#define DW_IC_COMP_VERSION			0xf8
-#define DW_IC_COMP_TYPE				0xfc
+enum dw_ic_reg_id {
+	DW_IC_CON,
+	DW_IC_TAR,
+	DW_IC_SAR,
+	DW_IC_DATA_CMD,
+	DW_IC_SS_SCL_HCNT,
+	DW_IC_SS_SCL_LCNT,
+	DW_IC_FS_SCL_HCNT,
+	DW_IC_FS_SCL_LCNT,
+	DW_IC_HS_SCL_HCNT,
+	DW_IC_HS_SCL_LCNT,
+	DW_IC_INTR_STAT,
+	DW_IC_INTR_MASK,
+	DW_IC_RAW_INTR_STAT,
+	DW_IC_RX_TL,
+	DW_IC_TX_TL,
+	DW_IC_CLR_INTR,
+	DW_IC_CLR_RX_UNDER,
+	DW_IC_CLR_RX_OVER,
+	DW_IC_CLR_TX_OVER,
+	DW_IC_CLR_RD_REQ,
+	DW_IC_CLR_TX_ABRT,
+	DW_IC_CLR_RX_DONE,
+	DW_IC_CLR_ACTIVITY,
+	DW_IC_CLR_STOP_DET,
+	DW_IC_CLR_START_DET,
+	DW_IC_CLR_GEN_CALL,
+	DW_IC_ENABLE,
+	DW_IC_STATUS,
+	DW_IC_TXFLR,
+	DW_IC_RXFLR,
+	DW_IC_SDA_HOLD,
+	DW_IC_TX_ABRT_SOURCE,
+	DW_IC_ENABLE_STATUS,
+	DW_IC_CLR_RESTART_DET,
+	DW_IC_SMBUS_INTR_STAT,
+	DW_IC_SMBUS_INTR_MASK,
+	DW_IC_CLR_SMBUS_INTR,
+	DW_IC_COMP_PARAM_1,
+	DW_IC_COMP_VERSION,
+	DW_IC_COMP_TYPE,
+	AMD_UCSI_INTR_REG,
+	DW_IC_REG_MAX
+};
+
+/*
+ * Default "snps,designware-i2c" register offsets, indexed by
+ * enum dw_ic_reg_id.
+ */
+static const __maybe_unused u32 dw_i2c_reg_offsets[DW_IC_REG_MAX] = {
+	[DW_IC_CON]			= 0x00,
+	[DW_IC_TAR]			= 0x04,
+	[DW_IC_SAR]			= 0x08,
+	[DW_IC_DATA_CMD]		= 0x10,
+	[DW_IC_SS_SCL_HCNT]		= 0x14,
+	[DW_IC_SS_SCL_LCNT]		= 0x18,
+	[DW_IC_FS_SCL_HCNT]		= 0x1c,
+	[DW_IC_FS_SCL_LCNT]		= 0x20,
+	[DW_IC_HS_SCL_HCNT]		= 0x24,
+	[DW_IC_HS_SCL_LCNT]		= 0x28,
+	[DW_IC_INTR_STAT]		= 0x2c,
+	[DW_IC_INTR_MASK]		= 0x30,
+	[DW_IC_RAW_INTR_STAT]		= 0x34,
+	[DW_IC_RX_TL]			= 0x38,
+	[DW_IC_TX_TL]			= 0x3c,
+	[DW_IC_CLR_INTR]		= 0x40,
+	[DW_IC_CLR_RX_UNDER]		= 0x44,
+	[DW_IC_CLR_RX_OVER]		= 0x48,
+	[DW_IC_CLR_TX_OVER]		= 0x4c,
+	[DW_IC_CLR_RD_REQ]		= 0x50,
+	[DW_IC_CLR_TX_ABRT]		= 0x54,
+	[DW_IC_CLR_RX_DONE]		= 0x58,
+	[DW_IC_CLR_ACTIVITY]		= 0x5c,
+	[DW_IC_CLR_STOP_DET]		= 0x60,
+	[DW_IC_CLR_START_DET]		= 0x64,
+	[DW_IC_CLR_GEN_CALL]		= 0x68,
+	[DW_IC_ENABLE]			= 0x6c,
+	[DW_IC_STATUS]			= 0x70,
+	[DW_IC_TXFLR]			= 0x74,
+	[DW_IC_RXFLR]			= 0x78,
+	[DW_IC_SDA_HOLD]		= 0x7c,
+	[DW_IC_TX_ABRT_SOURCE]		= 0x80,
+	[DW_IC_ENABLE_STATUS]		= 0x9c,
+	[DW_IC_CLR_RESTART_DET]		= 0xa8,
+	[DW_IC_SMBUS_INTR_STAT]		= 0xc8,
+	[DW_IC_SMBUS_INTR_MASK]		= 0xcc,
+	[DW_IC_CLR_SMBUS_INTR]		= 0xd4,
+	[DW_IC_COMP_PARAM_1]		= 0xf4,
+	[DW_IC_COMP_VERSION]		= 0xf8,
+	[DW_IC_COMP_TYPE]		= 0xfc,
+	[AMD_UCSI_INTR_REG]		= 0x474,
+};
 
 /* DW_IC_CON bits */
 #define DW_IC_CON_MASTER			BIT(0)

-- 
2.53.0

Re: [PATCH v3 2/3] i2c: designware: Support per-variant reg/bit offsets and intr handling

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] i2c: designware: wangxun hardware register access broken
- [Low] i2c: designware: dw_i2c_reg_offsets array bloat in header
--

commit 5382481b0ab458e2922590488d443f56e4cc2c8b
Author: Aniket Limaye <a-limaye@ti.com>

    i2c: designware: Support per-variant reg/bit offsets and intr handling

This commit introduces support for per-variant register and bit offsets,
and interrupt handling in the DesignWare I2C driver. It changes register
offsets from compile-time constants to a logical enum, resolving physical
offsets via a regmap-based mapping table to prepare for different register
layouts.

Link: https://lore.kernel.org/all/20260925-tda54-upstream-i2c-v2-2-261785e58493@ti.com/
Link: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-2-b0b9f77be18b@ti.com/

> diff --git a/include/linux/designware_i2c.h b/include/linux/designware_i2c.h
> index 53f37f18a7229..994e0e5ea623f 100644
> --- a/include/linux/designware_i2c.h
> +++ b/include/linux/designware_i2c.h
> @@ -11,48 +11,103 @@
>  #include <linux/bits.h>
>  
>  /*
> - * Registers offset
> + * Logical register IDs. Each ID is resolved to a physical offset via a
> + * per-variant table (see dw_i2c_reg_offsets[] below); regmap backends
> + * (dw_reg_read()/dw_reg_write() and the Xe I2C_REG() macro) perform that
> + * lookup so callers never need to know the real offset.
>   */
> -#define DW_IC_CON				0x00
> -#define DW_IC_TAR				0x04
[ ... ]
> -#define DW_IC_COMP_TYPE				0xfc
> +enum dw_ic_reg_id {
> +	DW_IC_CON,
> +	DW_IC_TAR,

[Severity: High]
Does changing these constants to logical enum IDs break Wangxun hardware
register access?

When the Wangxun driver's parent (txgbe) provisions an external parent regmap,
the I2C core skips its built-in regmap initialization:

drivers/i2c/busses/i2c-designware-common.c:i2c_dw_init_regmap() {
    ...
    /*
     * Skip detecting the registers map configuration if the regmap has
     * already been provided by a higher code.
     */
    if (dev->map)
        return 0;
    ...
}

Because the parent regmap hasn't been updated to expect logical register IDs,
it will pass these new enum values directly to the hardware. For example, it
would pass 26 for DW_IC_ENABLE instead of the physical offset 0x6c.

Will this cause the driver to read and write to incorrect register offsets on
Wangxun platforms?

[ ... ]
> +	DW_IC_COMP_TYPE,
> +	AMD_UCSI_INTR_REG,
> +	DW_IC_REG_MAX
> +};
> +
> +/*
> + * Default "snps,designware-i2c" register offsets, indexed by
> + * enum dw_ic_reg_id.
> + */
> +static const __maybe_unused u32 dw_i2c_reg_offsets[DW_IC_REG_MAX] = {
> +	[DW_IC_CON]			= 0x00,

[Severity: Low]
Does defining this static const array in a header file cause binary bloat?

Including linux/designware_i2c.h will embed a private copy of this 164-byte
array into every translation unit that includes the header.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260925-tda54-upstream-i2c-v3-0-544d74e992ff@ti.com?part=2

Re: [PATCH v3 2/3] i2c: designware: Support per-variant reg/bit offsets and intr handling

[Aniket Limaye]

On 25/09/26 12:39, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] i2c: designware: wangxun hardware register access broken
> - [Low] i2c: designware: dw_i2c_reg_offsets array bloat in header
> --
>
> commit 5382481b0ab458e2922590488d443f56e4cc2c8b
> Author: Aniket Limaye <a-limaye@ti.com>
>
>      i2c: designware: Support per-variant reg/bit offsets and intr handling
>
> This commit introduces support for per-variant register and bit offsets,
> and interrupt handling in the DesignWare I2C driver. It changes register
> offsets from compile-time constants to a logical enum, resolving physical
> offsets via a regmap-based mapping table to prepare for different register
> layouts.
>
> Link: https://lore.kernel.org/all/20260925-tda54-upstream-i2c-v2-2-261785e58493@ti.com/
> Link: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-2-b0b9f77be18b@ti.com/
>
>> diff --git a/include/linux/designware_i2c.h b/include/linux/designware_i2c.h
>> index 53f37f18a7229..994e0e5ea623f 100644
>> --- a/include/linux/designware_i2c.h
>> +++ b/include/linux/designware_i2c.h
>> @@ -11,48 +11,103 @@
>>   #include <linux/bits.h>
>>   
>>   /*
>> - * Registers offset
>> + * Logical register IDs. Each ID is resolved to a physical offset via a
>> + * per-variant table (see dw_i2c_reg_offsets[] below); regmap backends
>> + * (dw_reg_read()/dw_reg_write() and the Xe I2C_REG() macro) perform that
>> + * lookup so callers never need to know the real offset.
>>    */
>> -#define DW_IC_CON				0x00
>> -#define DW_IC_TAR				0x04
> [ ... ]
>> -#define DW_IC_COMP_TYPE				0xfc
>> +enum dw_ic_reg_id {
>> +	DW_IC_CON,
>> +	DW_IC_TAR,
> [Severity: High]
> Does changing these constants to logical enum IDs break Wangxun hardware
> register access?
>
> When the Wangxun driver's parent (txgbe) provisions an external parent regmap,
> the I2C core skips its built-in regmap initialization:
>
> drivers/i2c/busses/i2c-designware-common.c:i2c_dw_init_regmap() {
>      ...
>      /*
>       * Skip detecting the registers map configuration if the regmap has
>       * already been provided by a higher code.
>       */
>      if (dev->map)
>          return 0;
>      ...
> }
>
> Because the parent regmap hasn't been updated to expect logical register IDs,
> it will pass these new enum values directly to the hardware. For example, it
> would pass 26 for DW_IC_ENABLE instead of the physical offset 0x6c.
>
> Will this cause the driver to read and write to incorrect register offsets on
> Wangxun platforms?

This is a legitimate miss in current version, and will be handled in v4
similar to how xe_i2c.c is handled currently.

Will wait for a bit to see if there are more reviews on the approach,
before sending v4.

>
> [ ... ]
>> +	DW_IC_COMP_TYPE,
>> +	AMD_UCSI_INTR_REG,
>> +	DW_IC_REG_MAX
>> +};
>> +
>> +/*
>> + * Default "snps,designware-i2c" register offsets, indexed by
>> + * enum dw_ic_reg_id.
>> + */
>> +static const __maybe_unused u32 dw_i2c_reg_offsets[DW_IC_REG_MAX] = {
>> +	[DW_IC_CON]			= 0x00,
> [Severity: Low]
> Does defining this static const array in a header file cause binary bloat?
>
> Including linux/designware_i2c.h will embed a private copy of this 164-byte
> array into every translation unit that includes the header.
>

[PATCH v3 3/3] i2c: designware: Add ti,tda54-i2c support

[Aniket Limaye]

Compared to the existing DW_apb_i2c layout [1], DWC_i2c present in TDA54
SoC [0] differs enough to need MODEL_TI_TDA54-gated special-casing in a
few places:

- Add new register offsets table for TI TDA54 SoC.
- The DW_IC_CON register bitfields are also updated.
- Interrupts are acknowledged by writing a bitmask to a single CLR_INTR
  register instead of reading N dedicated CLR_* registers;
  i2c_dw_ack_intr() picks the right method based on dev->flags.
- One HCNT/LCNT register pair is shared between standard and fast speed
  instead of having one pair each; i2c_dw_write_timings() writes
  whichever value set matches the configured speed.
- No COMP_PARAM_1 register, so FIFO depth and high-speed-mode support
  can't be autodetected: FIFO depth now comes from the required
  snps,tx-fifo-depth/snps,rx-fifo-depth DT properties, and the
  high-speed capability check is skipped.
- No defined CON.RESTART_EN bit; treated as always set.
- TDA54 SoC does not have SMBus block, skip accesses to those registers.

[0]: DWC_i2c_reference.pdf
[1]: DW_apb_i2c_databook.pdf

Signed-off-by: Aniket Limaye <a-limaye@ti.com>

---

Changes in v2:
- Rename compatible/flag: snps,dwc-i2c -> ti,tda54-i2c,
  MODEL_DWC_I2C -> MODEL_TI_TDA54.
- Remove i2c_dwc_has_smbus(); just skip the SMBUS_INTR_MASK write under
  MODEL_TI_TDA54.
- Link to v1: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-3-b0b9f77be18b@ti.com/
---
 drivers/i2c/busses/i2c-designware-common.c  | 128 +++++++++++++++++++++++++---
 drivers/i2c/busses/i2c-designware-core.h    |  22 ++++-
 drivers/i2c/busses/i2c-designware-master.c  |  26 +++---
 drivers/i2c/busses/i2c-designware-platdrv.c |   1 +
 4 files changed, 153 insertions(+), 24 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index bd25b9c582c1..8cb162a6aed8 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -72,6 +72,40 @@ static const char *const abort_sources[] = {
 		"incorrect slave-transmitter mode configuration",
 };
 
+/* "ti,tda54-i2c" block-based register layout */
+#define DWC_ADV_OPERATION_BLK_OFFSET		0x00
+#define DWC_ADV_I2C_BLK_OFFSET			0x28
+#define DWC_ADV_FIFO_INTR_BLK_OFFSET		0xbc
+#define DWC_ADV_DEBUG_BLK_OFFSET		0xf8
+
+static const u32 tda54_i2c_reg_offsets[DW_IC_REG_MAX] = {
+	[DW_IC_ENABLE]			= DWC_ADV_OPERATION_BLK_OFFSET + 0x04,
+	[DW_IC_CON]			= DWC_ADV_I2C_BLK_OFFSET + 0x04,
+	[DW_IC_TAR]			= DWC_ADV_I2C_BLK_OFFSET + 0x08,
+	[DW_IC_SAR]			= DWC_ADV_I2C_BLK_OFFSET + 0x0c,
+	[DW_IC_DATA_CMD]		= DWC_ADV_I2C_BLK_OFFSET + 0x58,
+	[DW_IC_SS_SCL_HCNT]		= DWC_ADV_I2C_BLK_OFFSET + 0x24, /* shared SS/FS pair */
+	[DW_IC_SS_SCL_LCNT]		= DWC_ADV_I2C_BLK_OFFSET + 0x28,
+	[DW_IC_FS_SCL_HCNT]		= DWC_ADV_I2C_BLK_OFFSET + 0x24,
+	[DW_IC_FS_SCL_LCNT]		= DWC_ADV_I2C_BLK_OFFSET + 0x28,
+	[DW_IC_HS_SCL_HCNT]		= DWC_ADV_I2C_BLK_OFFSET + 0x2c,
+	[DW_IC_HS_SCL_LCNT]		= DWC_ADV_I2C_BLK_OFFSET + 0x30,
+	[DW_IC_SDA_HOLD]		= DWC_ADV_I2C_BLK_OFFSET + 0x34,
+	[DW_IC_RX_TL]			= DWC_ADV_I2C_BLK_OFFSET + 0x5c,
+	[DW_IC_TX_TL]			= DWC_ADV_I2C_BLK_OFFSET + 0x60,
+	[DW_IC_INTR_STAT]		= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x04,
+	[DW_IC_INTR_MASK]		= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x08,
+	[DW_IC_RAW_INTR_STAT]		= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x0c,
+	[DW_IC_CLR_INTR]		= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x10,
+	[DW_IC_STATUS]			= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x1c,
+	[DW_IC_TXFLR]			= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x20,
+	[DW_IC_RXFLR]			= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x24,
+	[DW_IC_TX_ABRT_SOURCE]		= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x18,
+	[DW_IC_ENABLE_STATUS]		= DWC_ADV_FIFO_INTR_BLK_OFFSET + 0x14,
+	[DW_IC_COMP_VERSION]		= DWC_ADV_DEBUG_BLK_OFFSET + 0x08,
+	[DW_IC_COMP_TYPE]		= DWC_ADV_DEBUG_BLK_OFFSET + 0x0c,
+};
+
 static const struct dw_i2c_con_bits dw_i2c_con_bits = {
 	.master			= DW_IC_CON_MASTER,
 	.speed_std		= DW_IC_CON_SPEED_STD,
@@ -88,6 +122,26 @@ static const struct dw_i2c_con_bits dw_i2c_con_bits = {
 	.bus_clear_ctrl		= DW_IC_CON_BUS_CLEAR_CTRL,
 };
 
+/*
+ * DWC_IC_CTRL bit layout for "ti,tda54-i2c".
+ * There is no defined bit for RESTART_EN or SLAVE_DISABLE on this IP.
+ */
+static const struct dw_i2c_con_bits dwc_adv_i2c_con_bits = {
+	.master			= BIT(0),
+	.speed_std		= (1 << 4),
+	.speed_fast		= (2 << 4),
+	.speed_high		= (3 << 4),
+	.speed_mask		= GENMASK(5, 4),
+	.bit10_slave		= BIT(8),
+	.bit10_master		= BIT(9),
+	.restart_en		= 0,
+	.slave_disable		= 0,
+	.stop_det_ifaddressed	= BIT(10),
+	.tx_empty_ctrl		= BIT(11),
+	.rx_fifo_full_hld_ctrl	= BIT(12),
+	.bus_clear_ctrl		= 0,
+};
+
 /* "snps,designware-i2c": dedicated read-to-clear register ID per logical interrupt */
 static const u32 dw_i2c_intr_clr[DW_INTR_IDX_MAX] = {
 	[DW_INTR_IDX_INTR]      = DW_IC_CLR_INTR,
@@ -103,6 +157,21 @@ static const u32 dw_i2c_intr_clr[DW_INTR_IDX_MAX] = {
 	[DW_INTR_IDX_GEN_CALL]  = DW_IC_CLR_GEN_CALL,
 };
 
+/* "ti,tda54-i2c" CLR_INTR bit to write per logical interrupt */
+static const u32 dwc_adv_i2c_intr_clr[DW_INTR_IDX_MAX] = {
+	[DW_INTR_IDX_INTR]      = DWC_ADV_IC_INTR_CLR_INTR,
+	[DW_INTR_IDX_RX_UNDER]  = DWC_ADV_IC_INTR_CLR_RX_UNDER,
+	[DW_INTR_IDX_RX_OVER]   = DWC_ADV_IC_INTR_CLR_RX_OVER,
+	[DW_INTR_IDX_TX_OVER]   = DWC_ADV_IC_INTR_CLR_TX_OVER,
+	[DW_INTR_IDX_RD_REQ]    = DWC_ADV_IC_INTR_CLR_RD_REQ,
+	[DW_INTR_IDX_TX_ABRT]   = DWC_ADV_IC_INTR_CLR_TX_ABRT,
+	[DW_INTR_IDX_RX_DONE]   = DWC_ADV_IC_INTR_CLR_RX_DONE,
+	[DW_INTR_IDX_ACTIVITY]  = DWC_ADV_IC_INTR_CLR_ACTIVITY,
+	[DW_INTR_IDX_STOP_DET]  = DWC_ADV_IC_INTR_CLR_STOP_DET,
+	[DW_INTR_IDX_START_DET] = DWC_ADV_IC_INTR_CLR_START_DET,
+	[DW_INTR_IDX_GEN_CALL]  = DWC_ADV_IC_INTR_CLR_GEN_CALL,
+};
+
 /**
  * i2c_dw_select_variant() - Pick the register offset table, CON-register bit
  * layout and interrupt-ack mapping matching this device's IP variant
@@ -110,9 +179,15 @@ static const u32 dw_i2c_intr_clr[DW_INTR_IDX_MAX] = {
  */
 void i2c_dw_select_variant(struct dw_i2c_dev *dev)
 {
-	dev->regs = dw_i2c_reg_offsets;
-	dev->con_bits = &dw_i2c_con_bits;
-	dev->intr_clr = dw_i2c_intr_clr;
+	if (dev->flags & MODEL_TI_TDA54) {
+		dev->regs = tda54_i2c_reg_offsets;
+		dev->con_bits = &dwc_adv_i2c_con_bits;
+		dev->intr_clr = dwc_adv_i2c_intr_clr;
+	} else {
+		dev->regs = dw_i2c_reg_offsets;
+		dev->con_bits = &dw_i2c_con_bits;
+		dev->intr_clr = dw_i2c_intr_clr;
+	}
 }
 EXPORT_SYMBOL_GPL(i2c_dw_select_variant);
 
@@ -432,13 +507,27 @@ static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode)
 
 static void i2c_dw_write_timings(struct dw_i2c_dev *dev)
 {
-	/* Write standard speed timing parameters */
-	regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
-	regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
-
-	/* Write fast mode/fast mode plus timing parameters */
-	regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
-	regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
+	if (dev->flags & MODEL_TI_TDA54) {
+		/*
+		 * Only one HCNT/LCNT register pair backs both speeds on
+		 * this IP -- write whichever value set matches master_cfg.
+		 */
+		if ((dev->master_cfg & dev->con_bits->speed_mask) == dev->con_bits->speed_std) {
+			regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
+			regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
+		} else {
+			regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
+			regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
+		}
+	} else {
+		/* Write standard speed timing parameters */
+		regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
+		regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
+
+		/* Write fast mode/fast mode plus timing parameters */
+		regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
+		regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
+	}
 
 	/* Write high speed timing parameters */
 	regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
@@ -493,8 +582,10 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
 	 * Mask SMBus interrupts to block storms from broken
 	 * firmware that leaves IC_SMBUS=1; the handler never
 	 * services them.
+	 * TDA54 SoC has no SMBus block, so skip it.
 	 */
-	regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);
+	if (!(dev->flags & MODEL_TI_TDA54))
+		regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);
 
 	i2c_dw_write_timings(dev);
 
@@ -538,6 +629,14 @@ int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev)
 	if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus_capacitance_pF))
 		dev->bus_capacitance_pF = DW_IC_DEFAULT_BUS_CAPACITANCE_pF;
 
+	if (dev->flags & MODEL_TI_TDA54) {
+		device_property_read_u32(device, "snps,tx-fifo-depth", &dev->tx_fifo_depth);
+		device_property_read_u32(device, "snps,rx-fifo-depth", &dev->rx_fifo_depth);
+
+		if (!dev->tx_fifo_depth || !dev->rx_fifo_depth)
+			return -EINVAL;
+	}
+
 	dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized");
 
 	/* Mobileye controllers do not hold the clock on empty FIFO */
@@ -854,6 +953,13 @@ static int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
 		return 0;
 	}
 
+	/*
+	 * DW_IC_COMP_PARAM_1 not implemented on this IP;
+	 * fifo depth set in i2c_dw_fw_parse_and_configure().
+	 */
+	if (dev->flags & MODEL_TI_TDA54)
+		return 0;
+
 	/*
 	 * Try to detect the FIFO depth if not set by interface driver,
 	 * the depth could be from 2 to 256 from HW spec.
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 4c782594ab4e..bd96abf63c39 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -79,6 +79,18 @@ enum dw_i2c_intr_idx {
 	DW_INTR_IDX_MAX,
 };
 
+#define DWC_ADV_IC_INTR_CLR_INTR		BIT(0)
+#define DWC_ADV_IC_INTR_CLR_RX_UNDER		BIT(1)
+#define DWC_ADV_IC_INTR_CLR_RX_OVER		BIT(2)
+#define DWC_ADV_IC_INTR_CLR_TX_OVER		BIT(3)
+#define DWC_ADV_IC_INTR_CLR_RD_REQ		BIT(4)
+#define DWC_ADV_IC_INTR_CLR_TX_ABRT		BIT(5)
+#define DWC_ADV_IC_INTR_CLR_RX_DONE		BIT(6)
+#define DWC_ADV_IC_INTR_CLR_ACTIVITY		BIT(7)
+#define DWC_ADV_IC_INTR_CLR_STOP_DET		BIT(8)
+#define DWC_ADV_IC_INTR_CLR_START_DET		BIT(9)
+#define DWC_ADV_IC_INTR_CLR_GEN_CALL		BIT(10)
+
 #define DW_IC_INTR_DEFAULT_MASK			(DW_IC_INTR_RX_FULL | \
 						 DW_IC_INTR_TX_ABRT | \
 						 DW_IC_INTR_STOP_DET)
@@ -291,7 +303,8 @@ struct dw_i2c_dev {
 
 #define MODEL_AMD_NAVI_GPU			BIT(10)
 #define MODEL_WANGXUN_SP			BIT(11)
-#define MODEL_MASK				GENMASK(11, 8)
+#define MODEL_TI_TDA54				BIT(12)
+#define MODEL_MASK				GENMASK(12, 8)
 
 /*
  * Enable UCSI interrupt by writing 0xd at register
@@ -352,12 +365,15 @@ static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev,
 		*intr_mask = dev->sw_mask;
 }
 
-/* Acknowledge a logical interrupt via dev->intr_clr[]: reg ID */
+/* Acknowledge a logical interrupt via dev->intr_clr[]: reg ID or bit value */
 static inline void i2c_dw_ack_intr(struct dw_i2c_dev *dev, enum dw_i2c_intr_idx intr)
 {
 	unsigned int dummy;
 
-	regmap_read(dev->map, dev->intr_clr[intr], &dummy);
+	if (dev->flags & MODEL_TI_TDA54)
+		regmap_write(dev->map, DW_IC_CLR_INTR, dev->intr_clr[intr]);
+	else
+		regmap_read(dev->map, dev->intr_clr[intr], &dummy);
 }
 
 void __i2c_dw_disable(struct dw_i2c_dev *dev);
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index 329f958ded3e..94594f6349d4 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -42,14 +42,16 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
 	u32 ic_clk;
 	int ret;
 
-	ret = i2c_dw_acquire_lock(dev);
-	if (ret)
-		return ret;
-
-	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
-	i2c_dw_release_lock(dev);
-	if (ret)
-		return ret;
+	if (!(dev->flags & MODEL_TI_TDA54)) {
+		ret = i2c_dw_acquire_lock(dev);
+		if (ret)
+			return ret;
+
+		ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
+		i2c_dw_release_lock(dev);
+		if (ret)
+			return ret;
+	}
 
 	/* Set standard and fast speed dividers for high/low periods */
 	sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
@@ -135,7 +137,8 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
 	/* Check is high speed possible and fall back to fast mode if not */
 	if ((dev->master_cfg & dev->con_bits->speed_mask) ==
 		dev->con_bits->speed_high) {
-		if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
+		if (!(dev->flags & MODEL_TI_TDA54) &&
+		    (comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 			!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 			dev_err(dev->dev, "High Speed not supported!\n");
 			t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
@@ -398,8 +401,11 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 			 * If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 			 * IC_RESTART_EN are set, we must manually
 			 * set restart bit between messages.
+			 * ti,tda54-i2c does not define a CON.RESTART_EN
+			 * bit, and behaves like it is set to 1.
 			 */
-			if (dev->master_cfg & dev->con_bits->restart_en &&
+			if (((dev->master_cfg & dev->con_bits->restart_en) ||
+			     (dev->flags & MODEL_TI_TDA54)) &&
 			    dev->msg_write_idx > 0)
 				need_restart = true;
 		}
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 42b34c678146..069c3dc0da10 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -257,6 +257,7 @@ static const struct of_device_id dw_i2c_of_match[] = {
 	{ .compatible = "mobileye,eyeq6lplus-i2c" },
 	{ .compatible = "mscc,ocelot-i2c" },
 	{ .compatible = "snps,designware-i2c" },
+	{ .compatible = "ti,tda54-i2c", .data = (void *)MODEL_TI_TDA54 },
 	{}
 };
 MODULE_DEVICE_TABLE(of, dw_i2c_of_match);

-- 
2.53.0

Re: [PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Andy Shevchenko]

On Fri, Sep 25, 2026 at 12:26:27PM +0530, Aniket Limaye wrote:
> Add new compatible and update driver to support Synopsys Advanced I2C
> Controller (DWC_i2c [0]) present on TI TDA54 SoC. This is needed since
> this controller differs from the existing designware i2c (DW_apb_i2c
> [1]) in its register offsets and some register definitions.
> 
> The new compatible updates driver logic due to changes in register
> definitions:
> 
> - The new register offsets are handled by first refactoring the driver
>   to use a map of register IDs to their offsets.
> - Similarly, also update the driver to use an updated CON-register
>   bitfield definition.
> - Interrupts are acknowledged by writing a bitmask to a single CLR_INTR
>   register instead of reading N dedicated CLR_* registers;
>   i2c_dw_ack_intr() picks the right method based on dev->flags.
> - One HCNT/LCNT register pair is shared between standard and fast speed
>   instead of having one pair each; i2c_dw_write_timings() writes
>   whichever value set matches the configured speed.
> - No COMP_PARAM_1 register, so FIFO depth and high-speed-mode support
>   can't be autodetected: FIFO depth now comes from the required
>   snps,tx-fifo-depth/snps,rx-fifo-depth DT properties, and the
>   high-speed capability check is skipped.
> - No defined CON.RESTART_EN bit; treat it as always set.
> - TDA54 SoC does not support SMBus, so skip accesses to those registers.
> 
> [0]: DWC_i2c_reference.pdf
> [1]: DW_apb_i2c_databook.pdf

Still doesn't look good. The current register layout may be left as is. What
you need is translate it in the respective regmap callbacks in case we are
enumerated on the different IP. Also possible to have a different regmap
config for the different HW where you translate them only in one place.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Aniket Limaye]

[-- Attachment #1: Type: text/plain, Size: 2211 bytes --]


On 25/09/26 15:11, Andy Shevchenko wrote:
> On Fri, Sep 25, 2026 at 12:26:27PM +0530, Aniket Limaye wrote:
>> Add new compatible and update driver to support Synopsys Advanced I2C
>> Controller (DWC_i2c [0]) present on TI TDA54 SoC. This is needed since
>> this controller differs from the existing designware i2c (DW_apb_i2c
>> [1]) in its register offsets and some register definitions.
>>
>> The new compatible updates driver logic due to changes in register
>> definitions:
>>
>> - The new register offsets are handled by first refactoring the driver
>>    to use a map of register IDs to their offsets.
>> - Similarly, also update the driver to use an updated CON-register
>>    bitfield definition.
>> - Interrupts are acknowledged by writing a bitmask to a single CLR_INTR
>>    register instead of reading N dedicated CLR_* registers;
>>    i2c_dw_ack_intr() picks the right method based on dev->flags.
>> - One HCNT/LCNT register pair is shared between standard and fast speed
>>    instead of having one pair each; i2c_dw_write_timings() writes
>>    whichever value set matches the configured speed.
>> - No COMP_PARAM_1 register, so FIFO depth and high-speed-mode support
>>    can't be autodetected: FIFO depth now comes from the required
>>    snps,tx-fifo-depth/snps,rx-fifo-depth DT properties, and the
>>    high-speed capability check is skipped.
>> - No defined CON.RESTART_EN bit; treat it as always set.
>> - TDA54 SoC does not support SMBus, so skip accesses to those registers.
>>
>> [0]: DWC_i2c_reference.pdf
>> [1]: DW_apb_i2c_databook.pdf
> Still doesn't look good. The current register layout may be left as is. What
> you need is translate it in the respective regmap callbacks in case we are
> enumerated on the different IP. Also possible to have a different regmap
> config for the different HW where you translate them only in one place.

Is it confusing to keep using existing offsets in regmap_read/write() 
call sites for TDA54, and let the regmap silently handle the translation?

Given that we do *not* have any new registers in use on the tda54 
version that were not there in the original one, I guess it works... 
will send a v4 as per your suggestion.

Thanks,
Aniket

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Re: [PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Andy Shevchenko]

On Fri, Sep 25, 2026 at 03:29:27PM +0530, Aniket Limaye wrote:
> On 25/09/26 15:11, Andy Shevchenko wrote:
> > On Fri, Sep 25, 2026 at 12:26:27PM +0530, Aniket Limaye wrote:

...

> > Still doesn't look good. The current register layout may be left as is. What
> > you need is translate it in the respective regmap callbacks in case we are
> > enumerated on the different IP. Also possible to have a different regmap
> > config for the different HW where you translate them only in one place.
> 
> Is it confusing to keep using existing offsets in regmap_read/write() call
> sites for TDA54, and let the regmap silently handle the translation?
> 
> Given that we do *not* have any new registers in use on the tda54 version
> that were not there in the original one, I guess it works... will send a v4
> as per your suggestion.

Depends on the mapping. Your series also forgot to provide the differences
Check this as an example: e539f435cb9c ("spi: dw: Add support for DesignWare DWC_ssi").

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Aniket Limaye]

On 25/09/26 15:40, Andy Shevchenko wrote:
> On Fri, Sep 25, 2026 at 03:29:27PM +0530, Aniket Limaye wrote:
>> On 25/09/26 15:11, Andy Shevchenko wrote:
>>> On Fri, Sep 25, 2026 at 12:26:27PM +0530, Aniket Limaye wrote:
> ...
>
>>> Still doesn't look good. The current register layout may be left as is. What
>>> you need is translate it in the respective regmap callbacks in case we are
>>> enumerated on the different IP. Also possible to have a different regmap
>>> config for the different HW where you translate them only in one place.
>> Is it confusing to keep using existing offsets in regmap_read/write() call
>> sites for TDA54, and let the regmap silently handle the translation?
>>
>> Given that we do *not* have any new registers in use on the tda54 version
>> that were not there in the original one, I guess it works... will send a v4
>> as per your suggestion.
> Depends on the mapping. Your series also forgot to provide the differences
> Check this as an example: e539f435cb9c ("spi: dw: Add support for DesignWare DWC_ssi").
>
Ahh sorry about that, will remember to add a clean mapping in cover 
letter of next version.

For now here are the structural differences:

1.  Reg offsets  Existing        New TDA54

     [DW_IC_CON]                     0x00           0x2c
     [DW_IC_TAR]                     0x04            0x30
     [DW_IC_SAR]                     0x08            0x34
     [DW_IC_DATA_CMD]                0x10            0x80
     [DW_IC_SS_SCL_HCNT]             0x14            0x4c
     [DW_IC_SS_SCL_LCNT]             0x18            0x50
     [DW_IC_FS_SCL_HCNT]             0x1c            0x4c  /* same as SS */
     [DW_IC_FS_SCL_LCNT]             0x20            0x50  /* same as SS */
     [DW_IC_HS_SCL_HCNT]             0x24         0x54
     [DW_IC_HS_SCL_LCNT]             0x28            0x58
     [DW_IC_INTR_STAT]               0x2c            0xc0
     [DW_IC_INTR_MASK]               0x30            0xc4
     [DW_IC_RAW_INTR_STAT]           0x34            0xc8
     [DW_IC_RX_TL]                   0x38            0x84
     [DW_IC_TX_TL]                   0x3c            0x88
     [DW_IC_CLR_INTR]                0x40            0xcc
     [DW_IC_CLR_RX_UNDER]            0x44            NA
     [DW_IC_CLR_RX_OVER]             0x48            NA
     [DW_IC_CLR_TX_OVER]             0x4c            NA
     [DW_IC_CLR_RD_REQ]              0x50            NA
     [DW_IC_CLR_TX_ABRT]             0x54            NA
     [DW_IC_CLR_RX_DONE]             0x58            NA
     [DW_IC_CLR_ACTIVITY]            0x5c            NA
     [DW_IC_CLR_STOP_DET]            0x60            NA
     [DW_IC_CLR_START_DET]           0x64            NA
     [DW_IC_CLR_GEN_CALL]            0x68            NA
     [DW_IC_ENABLE]                  0x6c            0x04
     [DW_IC_STATUS]                  0x70            0xd8
     [DW_IC_TXFLR]                   0x74            0xdc
     [DW_IC_RXFLR]                   0x78            0xe0
     [DW_IC_SDA_HOLD]                0x7c            0x5c
     [DW_IC_TX_ABRT_SOURCE]          0x80            0xd4
     [DW_IC_ENABLE_STATUS]           0x9c            0xd0
     [DW_IC_CLR_RESTART_DET]         0xa8            NA
     [DW_IC_SMBUS_INTR_STAT]         0xc8            NA
     [DW_IC_SMBUS_INTR_MASK]         0xcc            NA
     [DW_IC_CLR_SMBUS_INTR]          0xd4            NA
     [DW_IC_COMP_PARAM_1]            0xf4            NA
     [DW_IC_COMP_VERSION]            0xf8            0x100
     [DW_IC_COMP_TYPE]               0xfc            0x104

2. DW_IC_CON bitfields:

     DW_IC_CON_MASTER BIT(0)                  BIT(0)
     DW_IC_CON_SPEED_STD                 (1 << 1)       (1 << 4)
     DW_IC_CON_SPEED_FAST                (2 << 1)       (2 << 4)
     DW_IC_CON_SPEED_HIGH                (3 << 1)       (3 << 4)
     DW_IC_CON_SPEED_MASK                GENMASK(2, 1)  GENMASK(5, 4)
     DW_IC_CON_10BITADDR_SLAVE           BIT(3) BIT(8)
     DW_IC_CON_10BITADDR_MASTER          BIT(4) BIT(9)
     DW_IC_CON_RESTART_EN                BIT(5) NA
     DW_IC_CON_SLAVE_DISABLE             BIT(6) NA
     DW_IC_CON_STOP_DET_IFADDRESSED      BIT(7) BIT(10)
     DW_IC_CON_TX_EMPTY_CTRL             BIT(8) BIT(11)
     DW_IC_CON_RX_FIFO_FULL_HLD_CTRL     BIT(9) BIT(12)
     DW_IC_CON_BUS_CLEAR_CTRL            BIT(11)  BIT(14)

3. To clear INTR,  Read DW_IC_CLR_* reg    Write bit to DW_IC_CLR_INTR

As you can see, it's an entirely different mapping, which is why I had 2 
independent enum -> reg offset maps instead of offset -> offset 
translation.
Similarly, selecting a CON register bitfield layout too.

Let me know what you would prefer based on this...

Thanks,
Aniket

Re: [PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Andy Shevchenko]

On Fri, Sep 25, 2026 at 04:46:39PM +0530, Aniket Limaye wrote:
> On 25/09/26 15:40, Andy Shevchenko wrote:
> > On Fri, Sep 25, 2026 at 03:29:27PM +0530, Aniket Limaye wrote:
> > > On 25/09/26 15:11, Andy Shevchenko wrote:
> > > > On Fri, Sep 25, 2026 at 12:26:27PM +0530, Aniket Limaye wrote:

...

> > > > Still doesn't look good. The current register layout may be left as is. What
> > > > you need is translate it in the respective regmap callbacks in case we are
> > > > enumerated on the different IP. Also possible to have a different regmap
> > > > config for the different HW where you translate them only in one place.
> > > Is it confusing to keep using existing offsets in regmap_read/write() call
> > > sites for TDA54, and let the regmap silently handle the translation?
> > > 
> > > Given that we do *not* have any new registers in use on the tda54 version
> > > that were not there in the original one, I guess it works... will send a v4
> > > as per your suggestion.
> > Depends on the mapping. Your series also forgot to provide the differences
> > Check this as an example: e539f435cb9c ("spi: dw: Add support for DesignWare DWC_ssi").
> > 
> Ahh sorry about that, will remember to add a clean mapping in cover letter
> of next version.
> 
> For now here are the structural differences:
> 
> 1.  Reg offsets  Existing        New TDA54
> 
>     [DW_IC_CON]                     0x00           0x2c
>     [DW_IC_TAR]                     0x04            0x30
>     [DW_IC_SAR]                     0x08            0x34
>     [DW_IC_DATA_CMD]                0x10            0x80
>     [DW_IC_SS_SCL_HCNT]             0x14            0x4c
>     [DW_IC_SS_SCL_LCNT]             0x18            0x50
>     [DW_IC_FS_SCL_HCNT]             0x1c            0x4c  /* same as SS */
>     [DW_IC_FS_SCL_LCNT]             0x20            0x50  /* same as SS */
>     [DW_IC_HS_SCL_HCNT]             0x24         0x54
>     [DW_IC_HS_SCL_LCNT]             0x28            0x58
>     [DW_IC_INTR_STAT]               0x2c            0xc0
>     [DW_IC_INTR_MASK]               0x30            0xc4
>     [DW_IC_RAW_INTR_STAT]           0x34            0xc8
>     [DW_IC_RX_TL]                   0x38            0x84
>     [DW_IC_TX_TL]                   0x3c            0x88
>     [DW_IC_CLR_INTR]                0x40            0xcc
>     [DW_IC_CLR_RX_UNDER]            0x44            NA
>     [DW_IC_CLR_RX_OVER]             0x48            NA
>     [DW_IC_CLR_TX_OVER]             0x4c            NA
>     [DW_IC_CLR_RD_REQ]              0x50            NA
>     [DW_IC_CLR_TX_ABRT]             0x54            NA
>     [DW_IC_CLR_RX_DONE]             0x58            NA
>     [DW_IC_CLR_ACTIVITY]            0x5c            NA
>     [DW_IC_CLR_STOP_DET]            0x60            NA
>     [DW_IC_CLR_START_DET]           0x64            NA
>     [DW_IC_CLR_GEN_CALL]            0x68            NA
>     [DW_IC_ENABLE]                  0x6c            0x04
>     [DW_IC_STATUS]                  0x70            0xd8
>     [DW_IC_TXFLR]                   0x74            0xdc
>     [DW_IC_RXFLR]                   0x78            0xe0
>     [DW_IC_SDA_HOLD]                0x7c            0x5c
>     [DW_IC_TX_ABRT_SOURCE]          0x80            0xd4
>     [DW_IC_ENABLE_STATUS]           0x9c            0xd0
>     [DW_IC_CLR_RESTART_DET]         0xa8            NA
>     [DW_IC_SMBUS_INTR_STAT]         0xc8            NA
>     [DW_IC_SMBUS_INTR_MASK]         0xcc            NA
>     [DW_IC_CLR_SMBUS_INTR]          0xd4            NA
>     [DW_IC_COMP_PARAM_1]            0xf4            NA
>     [DW_IC_COMP_VERSION]            0xf8            0x100
>     [DW_IC_COMP_TYPE]               0xfc            0x104
> 
> 2. DW_IC_CON bitfields:
> 
>     DW_IC_CON_MASTER BIT(0)                  BIT(0)
>     DW_IC_CON_SPEED_STD                 (1 << 1)       (1 << 4)
>     DW_IC_CON_SPEED_FAST                (2 << 1)       (2 << 4)
>     DW_IC_CON_SPEED_HIGH                (3 << 1)       (3 << 4)
>     DW_IC_CON_SPEED_MASK                GENMASK(2, 1)  GENMASK(5, 4)
>     DW_IC_CON_10BITADDR_SLAVE           BIT(3) BIT(8)
>     DW_IC_CON_10BITADDR_MASTER          BIT(4) BIT(9)
>     DW_IC_CON_RESTART_EN                BIT(5) NA
>     DW_IC_CON_SLAVE_DISABLE             BIT(6) NA
>     DW_IC_CON_STOP_DET_IFADDRESSED      BIT(7) BIT(10)
>     DW_IC_CON_TX_EMPTY_CTRL             BIT(8) BIT(11)
>     DW_IC_CON_RX_FIFO_FULL_HLD_CTRL     BIT(9) BIT(12)
>     DW_IC_CON_BUS_CLEAR_CTRL            BIT(11)  BIT(14)

Thanks for providing this mapping!

> 3. To clear INTR,  Read DW_IC_CLR_* reg    Write bit to DW_IC_CLR_INTR
> 
> As you can see, it's an entirely different mapping, which is why I had 2
> independent enum -> reg offset maps instead of offset -> offset translation.
> Similarly, selecting a CON register bitfield layout too.
> 
> Let me know what you would prefer based on this...

This clears a bit the whole picture and what I would like to say is that better
to have the separate driver for it. On top of completely reworked RTL I believe
you won't need tons of hacks and workarounds that are applied during all these
years against the old IP.

TL;DR: Make a new clean and simple driver, which is hack-less and done properly
(using the all modern APIs and frameworks in the kernel).

-- 
With Best Regards,
Andy Shevchenko

✓ CI.KUnit: success for i2c: designware: Add TI TDA54 I2C support (rev2)

[Patchwork]

== Series Details ==

Series: i2c: designware: Add TI TDA54 I2C support (rev2)
URL   : https://patchwork.freedesktop.org/series/175011/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[20:20:55] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:21:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:21:20] Starting KUnit Kernel (1/1)...
[20:21:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:21:20] ============= refcount_interrupt (4 subtests) ==============
[20:21:20] [PASSED] test_single_irq_change
[20:21:20] [PASSED] test_nested_irq_change
[20:21:20] [PASSED] test_multiple_irq_change
[20:21:20] [PASSED] test_irq_save
[20:21:20] =============== [PASSED] refcount_interrupt ================
[20:21:20] ================= gpu_buddy (14 subtests) ==================
[20:21:20] [PASSED] gpu_test_buddy_alloc_limit
[20:21:20] [PASSED] gpu_test_buddy_alloc_optimistic
[20:21:20] [PASSED] gpu_test_buddy_alloc_pessimistic
[20:21:20] [PASSED] gpu_test_buddy_alloc_pathological
[20:21:20] [PASSED] gpu_test_buddy_alloc_contiguous
[20:21:20] [PASSED] gpu_test_buddy_alloc_clear
[20:21:20] [PASSED] gpu_test_buddy_alloc_range
[20:21:20] [PASSED] gpu_test_buddy_alloc_range_bias
[20:21:21] [PASSED] gpu_test_buddy_fragmentation_performance
[20:21:22] [PASSED] gpu_test_buddy_dirty_tracker_performance
[20:21:22] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[20:21:22] [PASSED] gpu_test_buddy_offset_aligned_allocation
[20:21:22] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[20:21:22] [PASSED] gpu_test_buddy_addr_to_block
[20:21:22] ==================== [PASSED] gpu_buddy ====================
[20:21:22] ============================================================
[20:21:22] Testing complete. Ran 18 tests: passed: 18
[20:21:22] Elapsed time: 26.606s total, 4.410s configuring, 20.328s building, 1.820s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:21:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:21:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:21:57] Starting KUnit Kernel (1/1)...
[20:21:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:21:58] ============= refcount_interrupt (4 subtests) ==============
[20:21:58] [PASSED] test_single_irq_change
[20:21:58] [PASSED] test_nested_irq_change
[20:21:58] [PASSED] test_multiple_irq_change
[20:21:58] [PASSED] test_irq_save
[20:21:58] =============== [PASSED] refcount_interrupt ================
[20:21:58] ================== guc_buf (11 subtests) ===================
[20:21:58] [PASSED] test_smallest
[20:21:58] [PASSED] test_largest
[20:21:58] [PASSED] test_granular
[20:21:58] [PASSED] test_unique
[20:21:58] [PASSED] test_overlap
[20:21:58] [PASSED] test_reusable
[20:21:58] [PASSED] test_too_big
[20:21:58] [PASSED] test_flush
[20:21:58] [PASSED] test_lookup
[20:21:58] [PASSED] test_data
[20:21:58] [PASSED] test_class
[20:21:58] ===================== [PASSED] guc_buf =====================
[20:21:58] =================== guc_dbm (7 subtests) ===================
[20:21:58] [PASSED] test_empty
[20:21:58] [PASSED] test_default
[20:21:58] ======================== test_size  ========================
[20:21:58] [PASSED] 4
[20:21:58] [PASSED] 8
[20:21:58] [PASSED] 32
[20:21:58] [PASSED] 256
[20:21:58] ==================== [PASSED] test_size ====================
[20:21:58] ======================= test_reuse  ========================
[20:21:58] [PASSED] 4
[20:21:58] [PASSED] 8
[20:21:58] [PASSED] 32
[20:21:58] [PASSED] 256
[20:21:58] =================== [PASSED] test_reuse ====================
[20:21:58] =================== test_range_overlap  ====================
[20:21:58] [PASSED] 4
[20:21:58] [PASSED] 8
[20:21:58] [PASSED] 32
[20:21:58] [PASSED] 256
[20:21:58] =============== [PASSED] test_range_overlap ================
[20:21:58] =================== test_range_compact  ====================
[20:21:58] [PASSED] 4
[20:21:58] [PASSED] 8
[20:21:58] [PASSED] 32
[20:21:58] [PASSED] 256
[20:21:58] =============== [PASSED] test_range_compact ================
[20:21:58] ==================== test_range_spare  =====================
[20:21:58] [PASSED] 4
[20:21:58] [PASSED] 8
[20:21:58] [PASSED] 32
[20:21:58] [PASSED] 256
[20:21:58] ================ [PASSED] test_range_spare =================
[20:21:58] ===================== [PASSED] guc_dbm =====================
[20:21:58] =================== guc_idm (6 subtests) ===================
[20:21:58] [PASSED] bad_init
[20:21:58] [PASSED] no_init
[20:21:58] [PASSED] init_fini
[20:21:58] [PASSED] check_used
[20:21:58] [PASSED] check_quota
[20:21:58] [PASSED] check_all
[20:21:58] ===================== [PASSED] guc_idm =====================
[20:21:58] ============== guc_klv_helpers (13 subtests) ===============
[20:21:58] [PASSED] test_count
[20:21:58] [PASSED] test_encode_u32
[20:21:58] [PASSED] test_encode_u64
[20:21:58] [PASSED] test_encode_string
[20:21:58] [PASSED] test_encode_object_raw
[20:21:58] [PASSED] test_encode_object_klv
[20:21:58] [PASSED] test_encode_object_nested
[20:21:58] [PASSED] test_encode_object_basic
[20:21:58] ===================== test_decode_u16  =====================
[20:21:58] [PASSED] empty
[20:21:58] [PASSED] valid
[20:21:58] [PASSED] max
[20:21:58] [PASSED] big
[20:21:58] [PASSED] long
[20:21:58] ================= [PASSED] test_decode_u16 =================
[20:21:58] ===================== test_decode_u32  =====================
[20:21:58] [PASSED] empty
[20:21:58] [PASSED] valid
[20:21:58] [PASSED] max
[20:21:58] [PASSED] long
[20:21:58] ================= [PASSED] test_decode_u32 =================
[20:21:58] ===================== test_decode_u64  =====================
[20:21:58] [PASSED] empty
[20:21:58] [PASSED] short
[20:21:58] [PASSED] valid
[20:21:58] [PASSED] max
[20:21:58] [PASSED] long
[20:21:58] ================= [PASSED] test_decode_u64 =================
[20:21:58] ===================== test_decode_str  =====================
[20:21:58] [PASSED] empty
[20:21:58] [PASSED] one
[20:21:58] [PASSED] one_trash
[20:21:58] [PASSED] two
[20:21:58] [PASSED] two_trash
[20:21:58] [PASSED] three
[20:21:58] [PASSED] dword
[20:21:58] [PASSED] four
[20:21:58] [PASSED] five
[20:21:58] [PASSED] six
[20:21:58] [PASSED] seven
[20:21:58] [PASSED] qword
[20:21:58] ================= [PASSED] test_decode_str =================
[20:21:58] [PASSED] test_print
[20:21:58] ================= [PASSED] guc_klv_helpers =================
[20:21:58] =================== xe_log (4 subtests) ====================
[20:21:58] [PASSED] demo_cper
[20:21:58] [PASSED] demo_dmesg
[20:21:58] ======================= test_dmesg  ========================
[20:21:58] [PASSED] test_fatal
[20:21:58] [PASSED] test_fatal_tile
[20:21:58] [PASSED] test_fatal_gt
[20:21:58] [PASSED] test_fatal_comp
[20:21:58] [PASSED] test_fatal_comp_tile
[20:21:58] [PASSED] test_fatal_comp_gt
[20:21:58] [PASSED] test_fatal_all
[20:21:58] [PASSED] test_recoverable
[20:21:58] [PASSED] test_recoverable_tile
[20:21:58] [PASSED] test_recoverable_gt
[20:21:58] [PASSED] test_recoverable_comp
[20:21:58] [PASSED] test_recoverable_comp_tile
[20:21:58] [PASSED] test_recoverable_comp_gt
[20:21:58] [PASSED] test_recoverable_all
[20:21:58] [PASSED] test_info
[20:21:58] [PASSED] test_info_tile
[20:21:58] [PASSED] test_info_gt
[20:21:58] [PASSED] test_info_err
[20:21:58] [PASSED] test_info_comp
[20:21:58] [PASSED] test_info_comp_tile
[20:21:58] [PASSED] test_info_comp_gt
[20:21:58] [PASSED] test_info_all
[20:21:58] [PASSED] test_hw_fatal
[20:21:58] [PASSED] test_hw_recoverable
[20:21:58] [PASSED] test_hw_corrected
[20:21:58] [PASSED] test_hw_informational
[20:21:58] =================== [PASSED] test_dmesg ====================
[20:21:58] ====================== test_invalid  =======================
[20:21:58] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[20:21:58] ================== [SKIPPED] test_invalid ==================
[20:21:58] ===================== [PASSED] xe_log ======================
[20:21:58] ================== no_relay (3 subtests) ===================
[20:21:58] [PASSED] xe_drops_guc2pf_if_not_ready
[20:21:58] [PASSED] xe_drops_guc2vf_if_not_ready
[20:21:58] [PASSED] xe_rejects_send_if_not_ready
[20:21:58] ==================== [PASSED] no_relay =====================
[20:21:58] ================== pf_relay (14 subtests) ==================
[20:21:58] [PASSED] pf_rejects_guc2pf_too_short
[20:21:58] [PASSED] pf_rejects_guc2pf_too_long
[20:21:58] [PASSED] pf_rejects_guc2pf_no_payload
[20:21:58] [PASSED] pf_fails_no_payload
[20:21:58] [PASSED] pf_fails_bad_origin
[20:21:58] [PASSED] pf_fails_bad_type
[20:21:58] [PASSED] pf_txn_reports_error
[20:21:58] [PASSED] pf_txn_sends_pf2guc
[20:21:58] [PASSED] pf_sends_pf2guc
[20:21:58] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:21:58] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:21:58] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:21:58] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:21:58] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:21:58] ==================== [PASSED] pf_relay =====================
[20:21:58] ================== vf_relay (3 subtests) ===================
[20:21:58] [PASSED] vf_rejects_guc2vf_too_short
[20:21:58] [PASSED] vf_rejects_guc2vf_too_long
[20:21:58] [PASSED] vf_rejects_guc2vf_no_payload
[20:21:58] ==================== [PASSED] vf_relay =====================
[20:21:58] ================ pf_gt_config (9 subtests) =================
[20:21:58] [PASSED] fair_contexts_1vf
[20:21:58] [PASSED] fair_doorbells_1vf
[20:21:58] [PASSED] fair_ggtt_1vf
[20:21:58] ====================== fair_vram_1vf  ======================
[20:21:58] [PASSED] 3.50 GiB
[20:21:58] [PASSED] 11.5 GiB
[20:21:58] [PASSED] 15.5 GiB
[20:21:58] [PASSED] 31.5 GiB
[20:21:58] [PASSED] 63.5 GiB
[20:21:58] [PASSED] 1.91 GiB
[20:21:58] ================== [PASSED] fair_vram_1vf ==================
[20:21:58] ================ fair_vram_1vf_admin_only  =================
[20:21:58] [PASSED] 3.50 GiB
[20:21:58] [PASSED] 11.5 GiB
[20:21:58] [PASSED] 15.5 GiB
[20:21:58] [PASSED] 31.5 GiB
[20:21:58] [PASSED] 63.5 GiB
[20:21:58] [PASSED] 1.91 GiB
[20:21:58] ============ [PASSED] fair_vram_1vf_admin_only =============
[20:21:58] ====================== fair_contexts  ======================
[20:21:58] [PASSED] 1 VF
[20:21:58] [PASSED] 2 VFs
[20:21:58] [PASSED] 3 VFs
[20:21:58] [PASSED] 4 VFs
[20:21:58] [PASSED] 5 VFs
[20:21:58] [PASSED] 6 VFs
[20:21:58] [PASSED] 7 VFs
[20:21:58] [PASSED] 8 VFs
[20:21:58] [PASSED] 9 VFs
[20:21:58] [PASSED] 10 VFs
[20:21:58] [PASSED] 11 VFs
[20:21:58] [PASSED] 12 VFs
[20:21:58] [PASSED] 13 VFs
[20:21:58] [PASSED] 14 VFs
[20:21:58] [PASSED] 15 VFs
[20:21:58] [PASSED] 16 VFs
[20:21:58] [PASSED] 17 VFs
[20:21:58] [PASSED] 18 VFs
[20:21:58] [PASSED] 19 VFs
[20:21:58] [PASSED] 20 VFs
[20:21:58] [PASSED] 21 VFs
[20:21:58] [PASSED] 22 VFs
[20:21:58] [PASSED] 23 VFs
[20:21:58] [PASSED] 24 VFs
[20:21:58] [PASSED] 25 VFs
[20:21:58] [PASSED] 26 VFs
[20:21:58] [PASSED] 27 VFs
[20:21:58] [PASSED] 28 VFs
[20:21:58] [PASSED] 29 VFs
[20:21:58] [PASSED] 30 VFs
[20:21:58] [PASSED] 31 VFs
[20:21:58] [PASSED] 32 VFs
[20:21:58] [PASSED] 33 VFs
[20:21:58] [PASSED] 34 VFs
[20:21:58] [PASSED] 35 VFs
[20:21:58] [PASSED] 36 VFs
[20:21:58] [PASSED] 37 VFs
[20:21:58] [PASSED] 38 VFs
[20:21:58] [PASSED] 39 VFs
[20:21:58] [PASSED] 40 VFs
[20:21:58] [PASSED] 41 VFs
[20:21:58] [PASSED] 42 VFs
[20:21:58] [PASSED] 43 VFs
[20:21:58] [PASSED] 44 VFs
[20:21:58] [PASSED] 45 VFs
[20:21:58] [PASSED] 46 VFs
[20:21:58] [PASSED] 47 VFs
[20:21:58] [PASSED] 48 VFs
[20:21:58] [PASSED] 49 VFs
[20:21:58] [PASSED] 50 VFs
[20:21:58] [PASSED] 51 VFs
[20:21:58] [PASSED] 52 VFs
[20:21:58] [PASSED] 53 VFs
[20:21:58] [PASSED] 54 VFs
[20:21:58] [PASSED] 55 VFs
[20:21:58] [PASSED] 56 VFs
[20:21:58] [PASSED] 57 VFs
[20:21:58] [PASSED] 58 VFs
[20:21:58] [PASSED] 59 VFs
[20:21:58] [PASSED] 60 VFs
[20:21:58] [PASSED] 61 VFs
[20:21:58] [PASSED] 62 VFs
[20:21:58] [PASSED] 63 VFs
[20:21:58] ================== [PASSED] fair_contexts ==================
[20:21:58] ===================== fair_doorbells  ======================
[20:21:58] [PASSED] 1 VF
[20:21:58] [PASSED] 2 VFs
[20:21:58] [PASSED] 3 VFs
[20:21:58] [PASSED] 4 VFs
[20:21:58] [PASSED] 5 VFs
[20:21:58] [PASSED] 6 VFs
[20:21:58] [PASSED] 7 VFs
[20:21:58] [PASSED] 8 VFs
[20:21:58] [PASSED] 9 VFs
[20:21:58] [PASSED] 10 VFs
[20:21:58] [PASSED] 11 VFs
[20:21:58] [PASSED] 12 VFs
[20:21:58] [PASSED] 13 VFs
[20:21:58] [PASSED] 14 VFs
[20:21:58] [PASSED] 15 VFs
[20:21:58] [PASSED] 16 VFs
[20:21:58] [PASSED] 17 VFs
[20:21:58] [PASSED] 18 VFs
[20:21:58] [PASSED] 19 VFs
[20:21:58] [PASSED] 20 VFs
[20:21:58] [PASSED] 21 VFs
[20:21:58] [PASSED] 22 VFs
[20:21:58] [PASSED] 23 VFs
[20:21:58] [PASSED] 24 VFs
[20:21:58] [PASSED] 25 VFs
[20:21:58] [PASSED] 26 VFs
[20:21:58] [PASSED] 27 VFs
[20:21:58] [PASSED] 28 VFs
[20:21:58] [PASSED] 29 VFs
[20:21:58] [PASSED] 30 VFs
[20:21:58] [PASSED] 31 VFs
[20:21:58] [PASSED] 32 VFs
[20:21:58] [PASSED] 33 VFs
[20:21:58] [PASSED] 34 VFs
[20:21:58] [PASSED] 35 VFs
[20:21:58] [PASSED] 36 VFs
[20:21:58] [PASSED] 37 VFs
[20:21:58] [PASSED] 38 VFs
[20:21:58] [PASSED] 39 VFs
[20:21:58] [PASSED] 40 VFs
[20:21:58] [PASSED] 41 VFs
[20:21:58] [PASSED] 42 VFs
[20:21:58] [PASSED] 43 VFs
[20:21:58] [PASSED] 44 VFs
[20:21:58] [PASSED] 45 VFs
[20:21:58] [PASSED] 46 VFs
[20:21:58] [PASSED] 47 VFs
[20:21:58] [PASSED] 48 VFs
[20:21:58] [PASSED] 49 VFs
[20:21:58] [PASSED] 50 VFs
[20:21:58] [PASSED] 51 VFs
[20:21:58] [PASSED] 52 VFs
[20:21:58] [PASSED] 53 VFs
[20:21:58] [PASSED] 54 VFs
[20:21:58] [PASSED] 55 VFs
[20:21:58] [PASSED] 56 VFs
[20:21:58] [PASSED] 57 VFs
[20:21:58] [PASSED] 58 VFs
[20:21:58] [PASSED] 59 VFs
[20:21:58] [PASSED] 60 VFs
[20:21:58] [PASSED] 61 VFs
[20:21:58] [PASSED] 62 VFs
[20:21:58] [PASSED] 63 VFs
[20:21:58] ================= [PASSED] fair_doorbells ==================
[20:21:58] ======================== fair_ggtt  ========================
[20:21:58] [PASSED] 1 VF
[20:21:58] [PASSED] 2 VFs
[20:21:58] [PASSED] 3 VFs
[20:21:58] [PASSED] 4 VFs
[20:21:58] [PASSED] 5 VFs
[20:21:58] [PASSED] 6 VFs
[20:21:58] [PASSED] 7 VFs
[20:21:58] [PASSED] 8 VFs
[20:21:58] [PASSED] 9 VFs
[20:21:58] [PASSED] 10 VFs
[20:21:58] [PASSED] 11 VFs
[20:21:58] [PASSED] 12 VFs
[20:21:58] [PASSED] 13 VFs
[20:21:58] [PASSED] 14 VFs
[20:21:58] [PASSED] 15 VFs
[20:21:58] [PASSED] 16 VFs
[20:21:58] [PASSED] 17 VFs
[20:21:58] [PASSED] 18 VFs
[20:21:58] [PASSED] 19 VFs
[20:21:58] [PASSED] 20 VFs
[20:21:58] [PASSED] 21 VFs
[20:21:58] [PASSED] 22 VFs
[20:21:58] [PASSED] 23 VFs
[20:21:58] [PASSED] 24 VFs
[20:21:58] [PASSED] 25 VFs
[20:21:58] [PASSED] 26 VFs
[20:21:58] [PASSED] 27 VFs
[20:21:58] [PASSED] 28 VFs
[20:21:58] [PASSED] 29 VFs
[20:21:58] [PASSED] 30 VFs
[20:21:58] [PASSED] 31 VFs
[20:21:58] [PASSED] 32 VFs
[20:21:58] [PASSED] 33 VFs
[20:21:58] [PASSED] 34 VFs
[20:21:58] [PASSED] 35 VFs
[20:21:58] [PASSED] 36 VFs
[20:21:58] [PASSED] 37 VFs
[20:21:58] [PASSED] 38 VFs
[20:21:58] [PASSED] 39 VFs
[20:21:58] [PASSED] 40 VFs
[20:21:58] [PASSED] 41 VFs
[20:21:58] [PASSED] 42 VFs
[20:21:58] [PASSED] 43 VFs
[20:21:58] [PASSED] 44 VFs
[20:21:58] [PASSED] 45 VFs
[20:21:58] [PASSED] 46 VFs
[20:21:58] [PASSED] 47 VFs
[20:21:58] [PASSED] 48 VFs
[20:21:58] [PASSED] 49 VFs
[20:21:58] [PASSED] 50 VFs
[20:21:58] [PASSED] 51 VFs
[20:21:58] [PASSED] 52 VFs
[20:21:58] [PASSED] 53 VFs
[20:21:58] [PASSED] 54 VFs
[20:21:58] [PASSED] 55 VFs
[20:21:58] [PASSED] 56 VFs
[20:21:58] [PASSED] 57 VFs
[20:21:58] [PASSED] 58 VFs
[20:21:58] [PASSED] 59 VFs
[20:21:58] [PASSED] 60 VFs
[20:21:58] [PASSED] 61 VFs
[20:21:58] [PASSED] 62 VFs
[20:21:58] [PASSED] 63 VFs
[20:21:58] ==================== [PASSED] fair_ggtt ====================
[20:21:58] ======================== fair_vram  ========================
[20:21:58] [PASSED] 1 VF
[20:21:58] [PASSED] 2 VFs
[20:21:58] [PASSED] 3 VFs
[20:21:58] [PASSED] 4 VFs
[20:21:58] [PASSED] 5 VFs
[20:21:58] [PASSED] 6 VFs
[20:21:58] [PASSED] 7 VFs
[20:21:58] [PASSED] 8 VFs
[20:21:58] [PASSED] 9 VFs
[20:21:58] [PASSED] 10 VFs
[20:21:58] [PASSED] 11 VFs
[20:21:58] [PASSED] 12 VFs
[20:21:58] [PASSED] 13 VFs
[20:21:58] [PASSED] 14 VFs
[20:21:58] [PASSED] 15 VFs
[20:21:58] [PASSED] 16 VFs
[20:21:58] [PASSED] 17 VFs
[20:21:58] [PASSED] 18 VFs
[20:21:58] [PASSED] 19 VFs
[20:21:58] [PASSED] 20 VFs
[20:21:58] [PASSED] 21 VFs
[20:21:58] [PASSED] 22 VFs
[20:21:58] [PASSED] 23 VFs
[20:21:58] [PASSED] 24 VFs
[20:21:58] [PASSED] 25 VFs
[20:21:58] [PASSED] 26 VFs
[20:21:58] [PASSED] 27 VFs
[20:21:58] [PASSED] 28 VFs
[20:21:58] [PASSED] 29 VFs
[20:21:58] [PASSED] 30 VFs
[20:21:58] [PASSED] 31 VFs
[20:21:58] [PASSED] 32 VFs
[20:21:58] [PASSED] 33 VFs
[20:21:58] [PASSED] 34 VFs
[20:21:58] [PASSED] 35 VFs
[20:21:58] [PASSED] 36 VFs
[20:21:58] [PASSED] 37 VFs
[20:21:58] [PASSED] 38 VFs
[20:21:58] [PASSED] 39 VFs
[20:21:58] [PASSED] 40 VFs
[20:21:58] [PASSED] 41 VFs
[20:21:58] [PASSED] 42 VFs
[20:21:58] [PASSED] 43 VFs
[20:21:58] [PASSED] 44 VFs
[20:21:58] [PASSED] 45 VFs
[20:21:58] [PASSED] 46 VFs
[20:21:58] [PASSED] 47 VFs
[20:21:58] [PASSED] 48 VFs
[20:21:58] [PASSED] 49 VFs
[20:21:58] [PASSED] 50 VFs
[20:21:58] [PASSED] 51 VFs
[20:21:58] [PASSED] 52 VFs
[20:21:58] [PASSED] 53 VFs
[20:21:58] [PASSED] 54 VFs
[20:21:58] [PASSED] 55 VFs
[20:21:58] [PASSED] 56 VFs
[20:21:58] [PASSED] 57 VFs
[20:21:58] [PASSED] 58 VFs
[20:21:58] [PASSED] 59 VFs
[20:21:58] [PASSED] 60 VFs
[20:21:58] [PASSED] 61 VFs
[20:21:58] [PASSED] 62 VFs
[20:21:58] [PASSED] 63 VFs
[20:21:58] ==================== [PASSED] fair_vram ====================
[20:21:58] ================== [PASSED] pf_gt_config ===================
[20:21:58] ===================== lmtt (1 subtest) =====================
[20:21:58] ======================== test_ops  =========================
[20:21:58] [PASSED] 2-level
[20:21:58] [PASSED] multi-level
[20:21:58] ==================== [PASSED] test_ops =====================
[20:21:58] ====================== [PASSED] lmtt =======================
[20:21:58] ================= sriov_packet (1 subtest) =================
[20:21:58] [PASSED] test_descriptor_init
[20:21:58] ================== [PASSED] sriov_packet ===================
[20:21:58] ================= pf_service (11 subtests) =================
[20:21:58] [PASSED] pf_negotiate_any
[20:21:58] [PASSED] pf_negotiate_base_match
[20:21:58] [PASSED] pf_negotiate_base_newer
[20:21:58] [PASSED] pf_negotiate_base_next
[20:21:58] [SKIPPED] pf_negotiate_base_older (no older minor)
[20:21:58] [PASSED] pf_negotiate_base_prev
[20:21:58] [PASSED] pf_negotiate_latest_match
[20:21:58] [PASSED] pf_negotiate_latest_newer
[20:21:58] [PASSED] pf_negotiate_latest_next
[20:21:58] [SKIPPED] pf_negotiate_latest_older (no older minor)
[20:21:58] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[20:21:58] =================== [PASSED] pf_service ====================
[20:21:58] ================= xe_guc_g2g (2 subtests) ==================
[20:21:58] ============== xe_live_guc_g2g_kunit_default  ==============
[20:21:58] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:21:58] ============== xe_live_guc_g2g_kunit_allmem  ===============
[20:21:58] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:21:58] =================== [SKIPPED] xe_guc_g2g ===================
[20:21:58] =================== xe_mocs (2 subtests) ===================
[20:21:58] ================ xe_live_mocs_kernel_kunit  ================
[20:21:58] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:21:58] ================ xe_live_mocs_reset_kunit  =================
[20:21:58] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:21:58] ==================== [SKIPPED] xe_mocs =====================
[20:21:58] ================= xe_migrate (2 subtests) ==================
[20:21:58] ================= xe_migrate_sanity_kunit  =================
[20:21:58] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:21:58] ================== xe_validate_ccs_kunit  ==================
[20:21:58] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:21:58] =================== [SKIPPED] xe_migrate ===================
[20:21:58] ================== xe_dma_buf (1 subtest) ==================
[20:21:58] ==================== xe_dma_buf_kunit  =====================
[20:21:58] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:21:58] =================== [SKIPPED] xe_dma_buf ===================
[20:21:58] ================= xe_bo_shrink (1 subtest) =================
[20:21:58] =================== xe_bo_shrink_kunit  ====================
[20:21:58] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:21:58] ================== [SKIPPED] xe_bo_shrink ==================
[20:21:58] ==================== xe_bo (2 subtests) ====================
[20:21:58] ================== xe_ccs_migrate_kunit  ===================
[20:21:58] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:21:58] ==================== xe_bo_evict_kunit  ====================
[20:21:58] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:21:58] ===================== [SKIPPED] xe_bo ======================
[20:21:58] =================== xe_any (9 subtests) ====================
[20:21:58] [PASSED] test_to_xe
[20:21:58] [PASSED] test_to_dev
[20:21:58] [PASSED] test_to_pdev
[20:21:58] [PASSED] test_to_drm
[20:21:58] [PASSED] test_if_pdev
[20:21:58] [PASSED] test_if_xe
[20:21:58] [PASSED] test_if_tile
[20:21:58] [PASSED] test_if_gt
[20:21:58] [PASSED] test_to_id
[20:21:58] ===================== [PASSED] xe_any ======================
[20:21:58] ==================== args (13 subtests) ====================
[20:21:58] [PASSED] count_args_test
[20:21:58] [PASSED] call_args_example
[20:21:58] [PASSED] call_args_test
[20:21:58] [PASSED] drop_first_arg_example
[20:21:58] [PASSED] drop_first_arg_test
[20:21:58] [PASSED] first_arg_example
[20:21:58] [PASSED] first_arg_test
[20:21:58] [PASSED] last_arg_example
[20:21:58] [PASSED] last_arg_test
[20:21:58] [PASSED] pick_arg_example
[20:21:58] [PASSED] if_args_example
[20:21:58] [PASSED] if_args_test
[20:21:58] [PASSED] sep_comma_example
[20:21:58] ====================== [PASSED] args =======================
[20:21:58] =================== xe_pci (3 subtests) ====================
[20:21:58] ==================== check_graphics_ip  ====================
[20:21:58] [PASSED] 12.00 Xe_LP
[20:21:58] [PASSED] 12.10 Xe_LP+
[20:21:58] [PASSED] 12.55 Xe_HPG
[20:21:58] [PASSED] 12.60 Xe_HPC
[20:21:58] [PASSED] 12.70 Xe_LPG
[20:21:58] [PASSED] 12.71 Xe_LPG
[20:21:58] [PASSED] 12.74 Xe_LPG+
[20:21:58] [PASSED] 20.01 Xe2_HPG
[20:21:58] [PASSED] 20.02 Xe2_HPG
[20:21:58] [PASSED] 20.04 Xe2_LPG
[20:21:58] [PASSED] 30.00 Xe3_LPG
[20:21:58] [PASSED] 30.01 Xe3_LPG
[20:21:58] [PASSED] 30.03 Xe3_LPG
[20:21:58] [PASSED] 30.04 Xe3_LPG
[20:21:58] [PASSED] 30.05 Xe3_LPG
[20:21:58] [PASSED] 35.10 Xe3p_LPG
[20:21:58] [PASSED] 35.11 Xe3p_XPC
[20:21:58] ================ [PASSED] check_graphics_ip ================
[20:21:58] ===================== check_media_ip  ======================
[20:21:58] [PASSED] 12.00 Xe_M
[20:21:58] [PASSED] 12.55 Xe_HPM
[20:21:58] [PASSED] 13.00 Xe_LPM+
[20:21:58] [PASSED] 13.01 Xe2_HPM
[20:21:58] [PASSED] 20.00 Xe2_LPM
[20:21:58] [PASSED] 30.00 Xe3_LPM
[20:21:58] [PASSED] 30.02 Xe3_LPM
[20:21:58] [PASSED] 35.00 Xe3p_LPM
[20:21:58] [PASSED] 35.03 Xe3p_HPM
[20:21:58] ================= [PASSED] check_media_ip ==================
[20:21:58] =================== check_platform_desc  ===================
[20:21:58] [PASSED] 0x9A60 (TIGERLAKE)
[20:21:58] [PASSED] 0x9A68 (TIGERLAKE)
[20:21:58] [PASSED] 0x9A70 (TIGERLAKE)
[20:21:58] [PASSED] 0x9A40 (TIGERLAKE)
[20:21:58] [PASSED] 0x9A49 (TIGERLAKE)
[20:21:58] [PASSED] 0x9A59 (TIGERLAKE)
[20:21:58] [PASSED] 0x9A78 (TIGERLAKE)
[20:21:58] [PASSED] 0x9AC0 (TIGERLAKE)
[20:21:58] [PASSED] 0x9AC9 (TIGERLAKE)
[20:21:58] [PASSED] 0x9AD9 (TIGERLAKE)
[20:21:58] [PASSED] 0x9AF8 (TIGERLAKE)
[20:21:58] [PASSED] 0x4C80 (ROCKETLAKE)
[20:21:58] [PASSED] 0x4C8A (ROCKETLAKE)
[20:21:58] [PASSED] 0x4C8B (ROCKETLAKE)
[20:21:58] [PASSED] 0x4C8C (ROCKETLAKE)
[20:21:58] [PASSED] 0x4C90 (ROCKETLAKE)
[20:21:58] [PASSED] 0x4C9A (ROCKETLAKE)
[20:21:58] [PASSED] 0x4680 (ALDERLAKE_S)
[20:21:58] [PASSED] 0x4682 (ALDERLAKE_S)
[20:21:58] [PASSED] 0x4688 (ALDERLAKE_S)
[20:21:58] [PASSED] 0x468A (ALDERLAKE_S)
[20:21:58] [PASSED] 0x468B (ALDERLAKE_S)
[20:21:58] [PASSED] 0x4690 (ALDERLAKE_S)
[20:21:58] [PASSED] 0x4692 (ALDERLAKE_S)
[20:21:58] [PASSED] 0x4693 (ALDERLAKE_S)
[20:21:58] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46AA (ALDERLAKE_P)
[20:21:58] [PASSED] 0x462A (ALDERLAKE_P)
[20:21:58] [PASSED] 0x4626 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x4628 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:21:58] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:21:58] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:21:58] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:21:58] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:21:58] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:21:58] [PASSED] 0xA721 (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA720 (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:21:58] [PASSED] 0xA780 (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA781 (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA782 (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA783 (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA788 (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA789 (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA78A (ALDERLAKE_S)
[20:21:58] [PASSED] 0xA78B (ALDERLAKE_S)
[20:21:58] [PASSED] 0x4905 (DG1)
[20:21:58] [PASSED] 0x4906 (DG1)
[20:21:58] [PASSED] 0x4907 (DG1)
[20:21:58] [PASSED] 0x4908 (DG1)
[20:21:58] [PASSED] 0x4909 (DG1)
[20:21:58] [PASSED] 0x56C0 (DG2)
[20:21:58] [PASSED] 0x56C2 (DG2)
[20:21:58] [PASSED] 0x56C1 (DG2)
[20:21:58] [PASSED] 0x7D51 (METEORLAKE)
[20:21:58] [PASSED] 0x7DD1 (METEORLAKE)
[20:21:58] [PASSED] 0x7D41 (METEORLAKE)
[20:21:58] [PASSED] 0x7D67 (METEORLAKE)
[20:21:58] [PASSED] 0xB640 (METEORLAKE)
[20:21:58] [PASSED] 0x56A0 (DG2)
[20:21:58] [PASSED] 0x56A1 (DG2)
[20:21:58] [PASSED] 0x56A2 (DG2)
[20:21:58] [PASSED] 0x56BE (DG2)
[20:21:58] [PASSED] 0x56BF (DG2)
[20:21:58] [PASSED] 0x5690 (DG2)
[20:21:58] [PASSED] 0x5691 (DG2)
[20:21:58] [PASSED] 0x5692 (DG2)
[20:21:58] [PASSED] 0x56A5 (DG2)
[20:21:58] [PASSED] 0x56A6 (DG2)
[20:21:58] [PASSED] 0x56B0 (DG2)
[20:21:58] [PASSED] 0x56B1 (DG2)
[20:21:58] [PASSED] 0x56BA (DG2)
[20:21:58] [PASSED] 0x56BB (DG2)
[20:21:58] [PASSED] 0x56BC (DG2)
[20:21:58] [PASSED] 0x56BD (DG2)
[20:21:58] [PASSED] 0x5693 (DG2)
[20:21:58] [PASSED] 0x5694 (DG2)
[20:21:58] [PASSED] 0x5695 (DG2)
[20:21:58] [PASSED] 0x56A3 (DG2)
[20:21:58] [PASSED] 0x56A4 (DG2)
[20:21:58] [PASSED] 0x56B2 (DG2)
[20:21:58] [PASSED] 0x56B3 (DG2)
[20:21:58] [PASSED] 0x5696 (DG2)
[20:21:58] [PASSED] 0x5697 (DG2)
[20:21:58] [PASSED] 0xB69 (PVC)
[20:21:58] [PASSED] 0xB6E (PVC)
[20:21:58] [PASSED] 0xBD4 (PVC)
[20:21:58] [PASSED] 0xBD5 (PVC)
[20:21:58] [PASSED] 0xBD6 (PVC)
[20:21:58] [PASSED] 0xBD7 (PVC)
[20:21:58] [PASSED] 0xBD8 (PVC)
[20:21:58] [PASSED] 0xBD9 (PVC)
[20:21:58] [PASSED] 0xBDA (PVC)
[20:21:58] [PASSED] 0xBDB (PVC)
[20:21:58] [PASSED] 0xBE0 (PVC)
[20:21:58] [PASSED] 0xBE1 (PVC)
[20:21:58] [PASSED] 0xBE5 (PVC)
[20:21:58] [PASSED] 0x7D40 (METEORLAKE)
[20:21:58] [PASSED] 0x7D45 (METEORLAKE)
[20:21:58] [PASSED] 0x7D55 (METEORLAKE)
[20:21:58] [PASSED] 0x7D60 (METEORLAKE)
[20:21:58] [PASSED] 0x7DD5 (METEORLAKE)
[20:21:58] [PASSED] 0x6420 (LUNARLAKE)
[20:21:58] [PASSED] 0x64A0 (LUNARLAKE)
[20:21:58] [PASSED] 0x64B0 (LUNARLAKE)
[20:21:58] [PASSED] 0xE202 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE209 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE20B (BATTLEMAGE)
[20:21:58] [PASSED] 0xE20C (BATTLEMAGE)
[20:21:58] [PASSED] 0xE20D (BATTLEMAGE)
[20:21:58] [PASSED] 0xE210 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE211 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE212 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE216 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE220 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE221 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE222 (BATTLEMAGE)
[20:21:58] [PASSED] 0xE223 (BATTLEMAGE)
[20:21:58] [PASSED] 0xB080 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB081 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB082 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB083 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB084 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB085 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB086 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB087 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB08F (PANTHERLAKE)
[20:21:58] [PASSED] 0xB090 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:21:58] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:21:58] [PASSED] 0xFD80 (PANTHERLAKE)
[20:21:58] [PASSED] 0xFD81 (PANTHERLAKE)
[20:21:58] [PASSED] 0xD740 (NOVALAKE_S)
[20:21:58] [PASSED] 0xD741 (NOVALAKE_S)
[20:21:58] [PASSED] 0xD742 (NOVALAKE_S)
[20:21:58] [PASSED] 0xD743 (NOVALAKE_S)
[20:21:58] [PASSED] 0xD745 (NOVALAKE_S)
[20:21:58] [PASSED] 0xD74A (NOVALAKE_S)
[20:21:58] [PASSED] 0xD74B (NOVALAKE_S)
[20:21:58] [PASSED] 0x674C (CRESCENTISLAND)
[20:21:58] [PASSED] 0x674D (CRESCENTISLAND)
[20:21:58] [PASSED] 0x674E (CRESCENTISLAND)
[20:21:58] [PASSED] 0x674F (CRESCENTISLAND)
[20:21:58] [PASSED] 0x6750 (CRESCENTISLAND)
[20:21:58] [PASSED] 0xD750 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD751 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD752 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD753 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD754 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD755 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD756 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD757 (NOVALAKE_P)
[20:21:58] [PASSED] 0xD75F (NOVALAKE_P)
[20:21:58] =============== [PASSED] check_platform_desc ===============
[20:21:58] ===================== [PASSED] xe_pci ======================
[20:21:58] ============= xe_rtp_tables_test (5 subtests) ==============
[20:21:58] ================== xe_rtp_table_gt_test  ===================
[20:21:58] [PASSED] gt_was/14011060649
[20:21:58] [PASSED] gt_was/14011059788
[20:21:58] [PASSED] gt_was/14015795083
[20:21:58] [PASSED] gt_was/16021867713
[20:21:58] [PASSED] gt_was/14019449301
[20:21:58] [PASSED] gt_was/16028005424
[20:21:58] [PASSED] gt_was/14026578760
[20:21:58] [PASSED] gt_was/1409420604
[20:21:58] [PASSED] gt_was/1408615072
[20:21:58] [PASSED] gt_was/22010523718
[20:21:58] [PASSED] gt_was/14011006942
[20:21:58] [PASSED] gt_was/14014830051
[20:21:58] [PASSED] gt_was/18018781329
[20:21:58] [PASSED] gt_was/1509235366
[20:21:58] [PASSED] gt_was/18018781329
[20:21:58] [PASSED] gt_was/16016694945
[20:21:58] [PASSED] gt_was/14018575942
[20:21:58] [PASSED] gt_was/22016670082
[20:21:58] [PASSED] gt_was/22016670082
[20:21:58] [PASSED] gt_was/14017421178
[20:21:58] [PASSED] gt_was/16025250150
[20:21:58] [PASSED] gt_was/14021871409
[20:21:58] [PASSED] gt_was/16021865536
[20:21:58] [PASSED] gt_was/14021486841
[20:21:58] [PASSED] gt_was/14025160223
[20:21:58] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[20:21:58] [PASSED] gt_was/14025635424
[20:21:58] [PASSED] gt_was/16028005424
[20:21:58] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:21:58] ================== xe_rtp_table_gt_test  ===================
[20:21:58] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[20:21:58] [PASSED] gt_tunings/Tuning: 32B Access Enable
[20:21:58] [PASSED] gt_tunings/Tuning: L3 cache
[20:21:58] [PASSED] gt_tunings/Tuning: L3 cache - media
[20:21:58] [PASSED] gt_tunings/Tuning: Compression Overfetch
[20:21:58] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[20:21:58] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[20:21:58] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[20:21:58] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[20:21:58] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[20:21:58] [PASSED] gt_tunings/Tuning: Stateless compression control
[20:21:58] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[20:21:58] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[20:21:58] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[20:21:58] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[20:21:58] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:21:58] ================== xe_rtp_table_oob_test  ==================
[20:21:58] [PASSED] oob_was/1607983814
[20:21:58] [PASSED] oob_was/16010904313
[20:21:58] [PASSED] oob_was/18022495364
[20:21:58] [PASSED] oob_was/22012773006
[20:21:58] [PASSED] oob_was/14014475959
[20:21:58] [PASSED] oob_was/22011391025
[20:21:58] [PASSED] oob_was/22012727170
[20:21:58] [PASSED] oob_was/22012727685
[20:21:58] [PASSED] oob_was/22016596838
[20:21:58] [PASSED] oob_was/18020744125
[20:21:58] [PASSED] oob_was/1409600907
[20:21:58] [PASSED] oob_was/22014953428
[20:21:58] [PASSED] oob_was/16017236439
[20:21:58] [PASSED] oob_was/14019821291
[20:21:58] [PASSED] oob_was/14015076503
[20:21:58] [PASSED] oob_was/22016122933
[20:21:58] [PASSED] oob_was/14018913170
[20:21:58] [PASSED] oob_was/14018094691
[20:21:58] [PASSED] oob_was/18024947630
[20:21:58] [PASSED] oob_was/16022287689
[20:21:58] [PASSED] oob_was/13011645652
[20:21:58] [PASSED] oob_was/14022293748
[20:21:58] [PASSED] oob_was/22019794406
[20:21:58] [PASSED] oob_was/22019338487
[20:21:58] [PASSED] oob_was/16023588340
[20:21:58] [PASSED] oob_was/14019789679
[20:21:58] [PASSED] oob_was/14022866841
[20:21:58] [PASSED] oob_was/16021333562
[20:21:58] [PASSED] oob_was/14016712196
[20:21:58] [PASSED] oob_was/14015568240
[20:21:58] [PASSED] oob_was/18013179988
[20:21:58] [PASSED] oob_was/1508761755
[20:21:58] [PASSED] oob_was/16023105232
[20:21:58] [PASSED] oob_was/16026508708
[20:21:58] [PASSED] oob_was/14020001231
[20:21:58] [PASSED] oob_was/16023683509
[20:21:58] [PASSED] oob_was/14025515070
[20:21:58] [PASSED] oob_was/15015404425_disable
[20:21:58] [PASSED] oob_was/16026007364
[20:21:58] [PASSED] oob_was/14020316580
[20:21:58] [PASSED] oob_was/14025883347
[20:21:58] [PASSED] oob_was/16029380221
[20:21:58] [PASSED] oob_was/22022079272
[20:21:58] [PASSED] oob_was/16029897822
[20:21:58] [PASSED] oob_was/14027054324
[20:21:58] [PASSED] oob_was/14025941587
[20:21:58] ============== [PASSED] xe_rtp_table_oob_test ==============
[20:21:58] ================ xe_rtp_table_dev_oob_test  ================
[20:21:58] [PASSED] device_oob_was/22010954014
[20:21:58] [PASSED] device_oob_was/15015404425
[20:21:58] [PASSED] device_oob_was/22019338487_display
[20:21:58] [PASSED] device_oob_was/14022085890
[20:21:58] [PASSED] device_oob_was/14026539277
[20:21:58] [PASSED] device_oob_was/14026633728
[20:21:58] [PASSED] device_oob_was/14026746987
[20:21:58] [PASSED] device_oob_was/14026779378
[20:21:58] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[20:21:58] ========== xe_rtp_table_missing_upper_bound_test  ==========
[20:21:58] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[20:21:58] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[20:21:58] [PASSED] register_whitelist/1806527549
[20:21:58] [PASSED] register_whitelist/allow_read_ctx_timestamp
[20:21:58] [PASSED] register_whitelist/allow_read_queue_timestamp
[20:21:58] [PASSED] register_whitelist/16014440446
[20:21:58] [PASSED] register_whitelist/16017236439
[20:21:58] [PASSED] register_whitelist/16020183090
[20:21:58] [PASSED] register_whitelist/14024997852
[20:21:58] [PASSED] register_whitelist/14024997852
[20:21:58] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[20:21:58] =============== [PASSED] xe_rtp_tables_test ================
[20:21:58] =================== xe_rtp (3 subtests) ====================
[20:21:58] =================== xe_rtp_rules_tests  ====================
[20:21:58] [PASSED] no
[20:21:58] [PASSED] yes
[20:21:58] [PASSED] no-and-no
[20:21:58] [PASSED] no-and-yes
[20:21:58] [PASSED] yes-and-no
[20:21:58] [PASSED] yes-and-yes
[20:21:58] [PASSED] no-or-no
[20:21:58] [PASSED] no-or-yes
[20:21:58] [PASSED] yes-or-no
[20:21:58] [PASSED] yes-or-yes
[20:21:58] [PASSED] no-yes-or-yes-no
[20:21:58] [PASSED] no-yes-or-yes-yes
[20:21:58] [PASSED] yes-yes-or-no-yes
[20:21:58] [PASSED] yes-yes-or-yes-yes
[20:21:58] [PASSED] no-no-or-yes-or-no
[20:21:58] [PASSED] or
[20:21:58] [PASSED] or-yes
[20:21:58] [PASSED] or-no
[20:21:58] [PASSED] yes-or
[20:21:58] [PASSED] no-or
[20:21:58] [PASSED] no-or-or-yes
[20:21:58] [PASSED] yes-or-or-no
[20:21:58] [PASSED] no-or-or-no
[20:21:58] [PASSED] missing-context-engine-class
[20:21:58] [PASSED] missing-context-engine-class-or-yes
[20:21:58] [PASSED] missing-context-engine-class-or-or-yes
[20:21:58] =============== [PASSED] xe_rtp_rules_tests ================
[20:21:58] =============== xe_rtp_process_to_sr_tests  ================
[20:21:58] [PASSED] coalesce-same-reg
[20:21:58] [PASSED] coalesce-same-reg-literal-and-func
[20:21:58] [PASSED] no-match-no-add
[20:21:58] [PASSED] two-regs-two-entries
[20:21:58] [PASSED] clr-one-set-other
[20:21:58] [PASSED] set-field
[20:21:58] [PASSED] conflict-duplicate
[20:21:58] [PASSED] conflict-not-disjoint
[20:21:58] [PASSED] conflict-not-disjoint-literal-and-func
[20:21:58] [PASSED] conflict-reg-type
[20:21:58] [PASSED] bad-mcr-reg-forced-to-regular
[20:21:58] [PASSED] bad-regular-reg-forced-to-mcr
[20:21:58] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:21:58] ================== xe_rtp_process_tests  ===================
[20:21:58] [PASSED] active1
[20:21:58] [PASSED] active2
[20:21:58] [PASSED] active-inactive
[20:21:58] [PASSED] inactive-active
[20:21:58] [PASSED] inactive-active-inactive
[20:21:58] [PASSED] inactive-inactive-inactive
[20:21:58] ============== [PASSED] xe_rtp_process_tests ===============
[20:21:58] ===================== [PASSED] xe_rtp ======================
[20:21:58] ==================== xe_wa (1 subtest) =====================
[20:21:58] ======================== xe_wa_gt  =========================
[20:21:58] [PASSED] TIGERLAKE B0
[20:21:58] [PASSED] DG1 A0
[20:21:58] [PASSED] DG1 B0
[20:21:58] [PASSED] ALDERLAKE_S A0
[20:21:58] [PASSED] ALDERLAKE_S B0
[20:21:58] [PASSED] ALDERLAKE_S C0
[20:21:58] [PASSED] ALDERLAKE_S D0
[20:21:58] [PASSED] ALDERLAKE_P A0
[20:21:58] [PASSED] ALDERLAKE_P B0
[20:21:58] [PASSED] ALDERLAKE_P C0
[20:21:58] [PASSED] ALDERLAKE_S RPLS D0
[20:21:58] [PASSED] ALDERLAKE_P RPLU E0
[20:21:58] [PASSED] DG2 G10 C0
[20:21:58] [PASSED] DG2 G11 B1
[20:21:58] [PASSED] DG2 G12 A1
[20:21:58] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:21:58] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:21:58] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:21:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:21:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:21:58] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:21:58] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:21:58] ==================== [PASSED] xe_wa_gt =====================
[20:21:58] ====================== [PASSED] xe_wa ======================
[20:21:58] ============================================================
[20:21:58] Testing complete. Ran 821 tests: passed: 793, skipped: 28
[20:21:58] Elapsed time: 36.384s total, 1.838s configuring, 33.780s building, 0.715s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:21:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:22:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:22:25] Starting KUnit Kernel (1/1)...
[20:22:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:22:25] ============= refcount_interrupt (4 subtests) ==============
[20:22:25] [PASSED] test_single_irq_change
[20:22:25] [PASSED] test_nested_irq_change
[20:22:25] [PASSED] test_multiple_irq_change
[20:22:25] [PASSED] test_irq_save
[20:22:25] =============== [PASSED] refcount_interrupt ================
[20:22:25] ============ drm_test_pick_cmdline (2 subtests) ============
[20:22:25] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:22:25] =============== drm_test_pick_cmdline_named  ===============
[20:22:25] [PASSED] NTSC
[20:22:25] [PASSED] NTSC-J
[20:22:25] [PASSED] PAL
[20:22:25] [PASSED] PAL-M
[20:22:25] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:22:25] ============== [PASSED] drm_test_pick_cmdline ==============
[20:22:25] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:22:25] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:22:25] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:22:25] =========== drm_validate_clone_mode (2 subtests) ===========
[20:22:25] ============== drm_test_check_in_clone_mode  ===============
[20:22:25] [PASSED] in_clone_mode
[20:22:25] [PASSED] not_in_clone_mode
[20:22:25] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:22:25] =============== drm_test_check_valid_clones  ===============
[20:22:25] [PASSED] not_in_clone_mode
[20:22:25] [PASSED] valid_clone
[20:22:25] [PASSED] invalid_clone
[20:22:25] =========== [PASSED] drm_test_check_valid_clones ===========
[20:22:25] ============= [PASSED] drm_validate_clone_mode =============
[20:22:25] ============= drm_validate_modeset (1 subtest) =============
[20:22:25] [PASSED] drm_test_check_connector_changed_modeset
[20:22:25] ============== [PASSED] drm_validate_modeset ===============
[20:22:25] ====== drm_test_bridge_get_current_state (1 subtest) =======
[20:22:25] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:22:25] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:22:25] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:22:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:22:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:22:25] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[20:22:25] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:22:25] ============== drm_bridge_alloc (2 subtests) ===============
[20:22:25] [PASSED] drm_test_drm_bridge_alloc_basic
[20:22:25] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:22:25] ================ [PASSED] drm_bridge_alloc =================
[20:22:25] ============= drm_bridge_bus_fmt (5 subtests) ==============
[20:22:25] [PASSED] drm_test_bridge_rgb_yuv_rgb
[20:22:25] [PASSED] drm_test_bridge_must_convert_to_yuv444
[20:22:25] [PASSED] drm_test_bridge_hdmi_auto_rgb
[20:22:25] [PASSED] drm_test_bridge_auto_first
[20:22:25] [PASSED] drm_test_bridge_rgb_yuv_no_path
[20:22:25] =============== [PASSED] drm_bridge_bus_fmt ================
[20:22:25] ============= drm_cmdline_parser (40 subtests) =============
[20:22:25] [PASSED] drm_test_cmdline_force_d_only
[20:22:25] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:22:25] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:22:25] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:22:25] [PASSED] drm_test_cmdline_force_e_only
[20:22:25] [PASSED] drm_test_cmdline_res
[20:22:25] [PASSED] drm_test_cmdline_res_vesa
[20:22:25] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:22:25] [PASSED] drm_test_cmdline_res_rblank
[20:22:25] [PASSED] drm_test_cmdline_res_bpp
[20:22:25] [PASSED] drm_test_cmdline_res_refresh
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:22:25] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:22:25] [PASSED] drm_test_cmdline_res_margins_force_on
[20:22:25] [PASSED] drm_test_cmdline_res_vesa_margins
[20:22:25] [PASSED] drm_test_cmdline_name
[20:22:25] [PASSED] drm_test_cmdline_name_bpp
[20:22:25] [PASSED] drm_test_cmdline_name_option
[20:22:25] [PASSED] drm_test_cmdline_name_bpp_option
[20:22:25] [PASSED] drm_test_cmdline_rotate_0
[20:22:25] [PASSED] drm_test_cmdline_rotate_90
[20:22:25] [PASSED] drm_test_cmdline_rotate_180
[20:22:25] [PASSED] drm_test_cmdline_rotate_270
[20:22:25] [PASSED] drm_test_cmdline_hmirror
[20:22:25] [PASSED] drm_test_cmdline_vmirror
[20:22:25] [PASSED] drm_test_cmdline_margin_options
[20:22:25] [PASSED] drm_test_cmdline_multiple_options
[20:22:25] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:22:25] [PASSED] drm_test_cmdline_extra_and_option
[20:22:25] [PASSED] drm_test_cmdline_freestanding_options
[20:22:25] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:22:25] [PASSED] drm_test_cmdline_panel_orientation
[20:22:25] ================ drm_test_cmdline_invalid  =================
[20:22:25] [PASSED] margin_only
[20:22:25] [PASSED] interlace_only
[20:22:25] [PASSED] res_missing_x
[20:22:25] [PASSED] res_missing_y
[20:22:25] [PASSED] res_bad_y
[20:22:25] [PASSED] res_missing_y_bpp
[20:22:25] [PASSED] res_bad_bpp
[20:22:25] [PASSED] res_bad_refresh
[20:22:25] [PASSED] res_bpp_refresh_force_on_off
[20:22:25] [PASSED] res_invalid_mode
[20:22:25] [PASSED] res_bpp_wrong_place_mode
[20:22:25] [PASSED] name_bpp_refresh
[20:22:25] [PASSED] name_refresh
[20:22:25] [PASSED] name_refresh_wrong_mode
[20:22:25] [PASSED] name_refresh_invalid_mode
[20:22:25] [PASSED] rotate_multiple
[20:22:25] [PASSED] rotate_invalid_val
[20:22:25] [PASSED] rotate_truncated
[20:22:25] [PASSED] invalid_option
[20:22:25] [PASSED] invalid_tv_option
[20:22:25] [PASSED] truncated_tv_option
[20:22:25] ============ [PASSED] drm_test_cmdline_invalid =============
[20:22:25] =============== drm_test_cmdline_tv_options  ===============
[20:22:25] [PASSED] NTSC
[20:22:25] [PASSED] NTSC_443
[20:22:25] [PASSED] NTSC_J
[20:22:25] [PASSED] PAL
[20:22:25] [PASSED] PAL_M
[20:22:25] [PASSED] PAL_N
[20:22:25] [PASSED] SECAM
[20:22:25] [PASSED] MONO_525
[20:22:25] [PASSED] MONO_625
[20:22:25] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:22:25] =============== [PASSED] drm_cmdline_parser ================
[20:22:25] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:22:25] [PASSED] drm_test_connector_hdmi_init_valid
[20:22:25] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:22:25] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:22:25] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:22:25] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:22:25] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:22:25] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:22:25] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:22:25] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:22:25] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:22:25] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:22:25] [PASSED] supported_formats=0x5 yuv420_allowed=1
[20:22:25] [PASSED] supported_formats=0x5 yuv420_allowed=0
[20:22:25] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:22:25] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:22:25] [PASSED] drm_test_connector_hdmi_init_null_product
[20:22:25] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:22:25] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:22:25] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:22:25] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:22:25] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:22:25] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:22:25] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:22:25] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:22:25] [PASSED] HDMI-A
[20:22:25] [PASSED] HDMI-B
[20:22:25] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:22:25] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:22:25] [PASSED] Unknown
[20:22:25] [PASSED] VGA
[20:22:25] [PASSED] DVI-I
[20:22:25] [PASSED] DVI-D
[20:22:25] [PASSED] DVI-A
[20:22:25] [PASSED] Composite
[20:22:25] [PASSED] SVIDEO
[20:22:25] [PASSED] LVDS
[20:22:25] [PASSED] Component
[20:22:25] [PASSED] DIN
[20:22:25] [PASSED] DP
[20:22:25] [PASSED] TV
[20:22:25] [PASSED] eDP
[20:22:25] [PASSED] Virtual
[20:22:25] [PASSED] DSI
[20:22:25] [PASSED] DPI
[20:22:25] [PASSED] Writeback
[20:22:25] [PASSED] SPI
[20:22:25] [PASSED] USB
[20:22:25] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:22:25] ============ [PASSED] drmm_connector_hdmi_init =============
[20:22:25] ============= drmm_connector_init (3 subtests) =============
[20:22:25] [PASSED] drm_test_drmm_connector_init
[20:22:25] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:22:25] ========= drm_test_drmm_connector_init_type_valid  =========
[20:22:25] [PASSED] Unknown
[20:22:25] [PASSED] VGA
[20:22:25] [PASSED] DVI-I
[20:22:25] [PASSED] DVI-D
[20:22:25] [PASSED] DVI-A
[20:22:25] [PASSED] Composite
[20:22:25] [PASSED] SVIDEO
[20:22:25] [PASSED] LVDS
[20:22:25] [PASSED] Component
[20:22:25] [PASSED] DIN
[20:22:25] [PASSED] DP
[20:22:25] [PASSED] HDMI-A
[20:22:25] [PASSED] HDMI-B
[20:22:25] [PASSED] TV
[20:22:25] [PASSED] eDP
[20:22:25] [PASSED] Virtual
[20:22:25] [PASSED] DSI
[20:22:25] [PASSED] DPI
[20:22:25] [PASSED] Writeback
[20:22:25] [PASSED] SPI
[20:22:25] [PASSED] USB
[20:22:25] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:22:25] =============== [PASSED] drmm_connector_init ===============
[20:22:25] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_init
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:22:25] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:22:25] [PASSED] Unknown
[20:22:25] [PASSED] VGA
[20:22:25] [PASSED] DVI-I
[20:22:25] [PASSED] DVI-D
[20:22:25] [PASSED] DVI-A
[20:22:25] [PASSED] Composite
[20:22:25] [PASSED] SVIDEO
[20:22:25] [PASSED] LVDS
[20:22:25] [PASSED] Component
[20:22:25] [PASSED] DIN
[20:22:25] [PASSED] DP
[20:22:25] [PASSED] HDMI-A
[20:22:25] [PASSED] HDMI-B
[20:22:25] [PASSED] TV
[20:22:25] [PASSED] eDP
[20:22:25] [PASSED] Virtual
[20:22:25] [PASSED] DSI
[20:22:25] [PASSED] DPI
[20:22:25] [PASSED] Writeback
[20:22:25] [PASSED] SPI
[20:22:25] [PASSED] USB
[20:22:25] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:22:25] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:22:25] [PASSED] Unknown
[20:22:25] [PASSED] VGA
[20:22:25] [PASSED] DVI-I
[20:22:25] [PASSED] DVI-D
[20:22:25] [PASSED] DVI-A
[20:22:25] [PASSED] Composite
[20:22:25] [PASSED] SVIDEO
[20:22:25] [PASSED] LVDS
[20:22:25] [PASSED] Component
[20:22:25] [PASSED] DIN
[20:22:25] [PASSED] DP
[20:22:25] [PASSED] HDMI-A
[20:22:25] [PASSED] HDMI-B
[20:22:25] [PASSED] TV
[20:22:25] [PASSED] eDP
[20:22:25] [PASSED] Virtual
[20:22:25] [PASSED] DSI
[20:22:25] [PASSED] DPI
[20:22:25] [PASSED] Writeback
[20:22:25] [PASSED] SPI
[20:22:25] [PASSED] USB
[20:22:25] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:22:25] =========== [PASSED] drm_connector_dynamic_init ============
[20:22:25] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:22:25] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:22:25] ======= drm_connector_dynamic_register (7 subtests) ========
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:22:25] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:22:25] ========= [PASSED] drm_connector_dynamic_register ==========
[20:22:25] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:22:25] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:22:25] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:22:25] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:22:25] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:22:25] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:22:25] [PASSED] NTSC
[20:22:25] [PASSED] NTSC-443
[20:22:25] [PASSED] NTSC-J
[20:22:25] [PASSED] PAL
[20:22:25] [PASSED] PAL-M
[20:22:25] [PASSED] PAL-N
[20:22:25] [PASSED] SECAM
[20:22:25] [PASSED] Mono
[20:22:25] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:22:25] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:22:25] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:22:25] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:22:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:22:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:22:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:22:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:22:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:22:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:22:25] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:22:25] [PASSED] VIC 96
[20:22:25] [PASSED] VIC 97
[20:22:25] [PASSED] VIC 101
[20:22:25] [PASSED] VIC 102
[20:22:25] [PASSED] VIC 106
[20:22:25] [PASSED] VIC 107
[20:22:25] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:22:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:22:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:22:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:22:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:22:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:22:25] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:22:25] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:22:25] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:22:25] [PASSED] Automatic
[20:22:25] [PASSED] Full
[20:22:25] [PASSED] Limited 16:235
[20:22:25] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:22:25] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:22:25] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:22:25] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:22:25] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:22:25] [PASSED] RGB
[20:22:25] [PASSED] YUV 4:2:0
[20:22:25] [PASSED] YUV 4:2:2
[20:22:25] [PASSED] YUV 4:4:4
[20:22:25] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:22:25] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:22:25] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:22:25] ============= drm_damage_helper (21 subtests) ==============
[20:22:25] [PASSED] drm_test_damage_iter_no_damage
[20:22:25] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:22:25] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:22:25] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:22:25] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:22:25] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:22:25] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:22:25] [PASSED] drm_test_damage_iter_simple_damage
[20:22:25] [PASSED] drm_test_damage_iter_single_damage
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:22:25] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:22:25] [PASSED] drm_test_damage_iter_damage
[20:22:25] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:22:25] [PASSED] drm_test_damage_iter_damage_one_outside
[20:22:25] [PASSED] drm_test_damage_iter_damage_src_moved
[20:22:25] [PASSED] drm_test_damage_iter_damage_not_visible
[20:22:25] ================ [PASSED] drm_damage_helper ================
[20:22:25] ============== drm_dp_mst_helper (3 subtests) ==============
[20:22:25] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:22:25] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:22:25] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:22:25] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:22:25] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:22:25] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:22:25] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:22:25] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:22:25] [PASSED] Link rate 2000000 lane count 4
[20:22:25] [PASSED] Link rate 2000000 lane count 2
[20:22:25] [PASSED] Link rate 2000000 lane count 1
[20:22:25] [PASSED] Link rate 1350000 lane count 4
[20:22:25] [PASSED] Link rate 1350000 lane count 2
[20:22:25] [PASSED] Link rate 1350000 lane count 1
[20:22:25] [PASSED] Link rate 1000000 lane count 4
[20:22:25] [PASSED] Link rate 1000000 lane count 2
[20:22:25] [PASSED] Link rate 1000000 lane count 1
[20:22:25] [PASSED] Link rate 810000 lane count 4
[20:22:25] [PASSED] Link rate 810000 lane count 2
[20:22:25] [PASSED] Link rate 810000 lane count 1
[20:22:25] [PASSED] Link rate 540000 lane count 4
[20:22:25] [PASSED] Link rate 540000 lane count 2
[20:22:25] [PASSED] Link rate 540000 lane count 1
[20:22:25] [PASSED] Link rate 270000 lane count 4
[20:22:25] [PASSED] Link rate 270000 lane count 2
[20:22:25] [PASSED] Link rate 270000 lane count 1
[20:22:25] [PASSED] Link rate 162000 lane count 4
[20:22:25] [PASSED] Link rate 162000 lane count 2
[20:22:25] [PASSED] Link rate 162000 lane count 1
[20:22:25] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:22:25] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:22:25] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:22:25] [PASSED] DP_POWER_UP_PHY with port number
[20:22:25] [PASSED] DP_POWER_DOWN_PHY with port number
[20:22:25] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:22:25] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:22:25] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:22:25] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:22:25] [PASSED] DP_QUERY_PAYLOAD with port number
[20:22:25] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:22:25] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:22:25] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:22:25] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:22:25] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:22:25] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:22:25] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:22:25] [PASSED] DP_REMOTE_I2C_READ with port number
[20:22:25] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:22:25] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:22:25] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:22:25] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:22:25] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:22:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:22:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:22:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:22:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:22:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:22:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:22:25] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:22:25] ================ [PASSED] drm_dp_mst_helper ================
[20:22:25] ================== drm_exec (7 subtests) ===================
[20:22:25] [PASSED] sanitycheck
[20:22:25] [PASSED] test_lock
[20:22:25] [PASSED] test_lock_unlock
[20:22:25] [PASSED] test_duplicates
[20:22:25] [PASSED] test_prepare
[20:22:25] [PASSED] test_prepare_array
[20:22:25] [PASSED] test_multiple_loops
[20:22:25] ==================== [PASSED] drm_exec =====================
[20:22:25] =========== drm_format_helper_test (17 subtests) ===========
[20:22:25] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:22:25] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:22:25] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:22:25] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:22:25] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:22:25] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:22:25] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:22:25] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:22:25] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:22:25] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:22:25] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:22:25] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:22:25] ==================== drm_test_fb_swab  =====================
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ================ [PASSED] drm_test_fb_swab =================
[20:22:25] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:22:25] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:22:25] [PASSED] single_pixel_source_buffer
[20:22:25] [PASSED] single_pixel_clip_rectangle
[20:22:25] [PASSED] well_known_colors
[20:22:25] [PASSED] destination_pitch
[20:22:25] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:22:25] ================= drm_test_fb_clip_offset  =================
[20:22:25] [PASSED] pass through
[20:22:25] [PASSED] horizontal offset
[20:22:25] [PASSED] vertical offset
[20:22:25] [PASSED] horizontal and vertical offset
[20:22:25] [PASSED] horizontal offset (custom pitch)
[20:22:25] [PASSED] vertical offset (custom pitch)
[20:22:25] [PASSED] horizontal and vertical offset (custom pitch)
[20:22:25] ============= [PASSED] drm_test_fb_clip_offset =============
[20:22:25] =================== drm_test_fb_memcpy  ====================
[20:22:25] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:22:25] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:22:25] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:22:25] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:22:25] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:22:25] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:22:25] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:22:25] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:22:25] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:22:25] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:22:25] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:22:25] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:22:25] =============== [PASSED] drm_test_fb_memcpy ================
[20:22:25] ============= [PASSED] drm_format_helper_test ==============
[20:22:25] ================= drm_format (18 subtests) =================
[20:22:25] [PASSED] drm_test_format_block_width_invalid
[20:22:25] [PASSED] drm_test_format_block_width_one_plane
[20:22:25] [PASSED] drm_test_format_block_width_two_plane
[20:22:25] [PASSED] drm_test_format_block_width_three_plane
[20:22:25] [PASSED] drm_test_format_block_width_tiled
[20:22:25] [PASSED] drm_test_format_block_height_invalid
[20:22:25] [PASSED] drm_test_format_block_height_one_plane
[20:22:25] [PASSED] drm_test_format_block_height_two_plane
[20:22:25] [PASSED] drm_test_format_block_height_three_plane
[20:22:25] [PASSED] drm_test_format_block_height_tiled
[20:22:25] [PASSED] drm_test_format_min_pitch_invalid
[20:22:25] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:22:25] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:22:25] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:22:25] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:22:25] [PASSED] drm_test_format_min_pitch_two_plane
[20:22:25] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:22:25] [PASSED] drm_test_format_min_pitch_tiled
[20:22:25] =================== [PASSED] drm_format ====================
[20:22:25] ============== drm_framebuffer (10 subtests) ===============
[20:22:25] ========== drm_test_framebuffer_check_src_coords  ==========
[20:22:25] [PASSED] Success: source fits into fb
[20:22:25] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:22:25] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:22:25] [PASSED] Fail: overflowing fb with source width
[20:22:25] [PASSED] Fail: overflowing fb with source height
[20:22:25] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:22:25] [PASSED] drm_test_framebuffer_cleanup
[20:22:25] =============== drm_test_framebuffer_create  ===============
[20:22:25] [PASSED] ABGR8888 normal sizes
[20:22:25] [PASSED] ABGR8888 max sizes
[20:22:25] [PASSED] ABGR8888 pitch greater than min required
[20:22:25] [PASSED] ABGR8888 pitch less than min required
[20:22:25] [PASSED] ABGR8888 Invalid width
[20:22:25] [PASSED] ABGR8888 Invalid buffer handle
[20:22:25] [PASSED] No pixel format
[20:22:25] [PASSED] ABGR8888 Width 0
[20:22:25] [PASSED] ABGR8888 Height 0
[20:22:25] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:22:25] [PASSED] ABGR8888 Large buffer offset
[20:22:25] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:22:25] [PASSED] ABGR8888 Invalid flag
[20:22:25] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:22:25] [PASSED] ABGR8888 Valid buffer modifier
[20:22:25] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:22:25] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] NV12 Normal sizes
[20:22:25] [PASSED] NV12 Max sizes
[20:22:25] [PASSED] NV12 Invalid pitch
[20:22:25] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:22:25] [PASSED] NV12 different  modifier per-plane
[20:22:25] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:22:25] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] NV12 Modifier for inexistent plane
[20:22:25] [PASSED] NV12 Handle for inexistent plane
[20:22:25] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:22:25] [PASSED] YVU420 Normal sizes
[20:22:25] [PASSED] YVU420 Max sizes
[20:22:25] [PASSED] YVU420 Invalid pitch
[20:22:25] [PASSED] YVU420 Different pitches
[20:22:25] [PASSED] YVU420 Different buffer offsets/pitches
[20:22:25] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:22:25] [PASSED] YVU420 Valid modifier
[20:22:25] [PASSED] YVU420 Different modifiers per plane
[20:22:25] [PASSED] YVU420 Modifier for inexistent plane
[20:22:25] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:22:25] [PASSED] X0L2 Normal sizes
[20:22:25] [PASSED] X0L2 Max sizes
[20:22:25] [PASSED] X0L2 Invalid pitch
[20:22:25] [PASSED] X0L2 Pitch greater than minimum required
[20:22:25] [PASSED] X0L2 Handle for inexistent plane
[20:22:25] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:22:25] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:22:25] [PASSED] X0L2 Valid modifier
[20:22:25] [PASSED] X0L2 Modifier for inexistent plane
[20:22:25] =========== [PASSED] drm_test_framebuffer_create ===========
[20:22:25] [PASSED] drm_test_framebuffer_free
[20:22:25] [PASSED] drm_test_framebuffer_init
[20:22:25] [PASSED] drm_test_framebuffer_init_bad_format
[20:22:25] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:22:25] [PASSED] drm_test_framebuffer_lookup
[20:22:25] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:22:25] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:22:25] ================= [PASSED] drm_framebuffer =================
[20:22:25] ================ drm_gem_shmem (8 subtests) ================
[20:22:25] [PASSED] drm_gem_shmem_test_obj_create
[20:22:25] [PASSED] drm_gem_shmem_test_obj_create_private
[20:22:25] [PASSED] drm_gem_shmem_test_pin_pages
[20:22:25] [PASSED] drm_gem_shmem_test_vmap
[20:22:25] [PASSED] drm_gem_shmem_test_get_sg_table
[20:22:25] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:22:25] [PASSED] drm_gem_shmem_test_madvise
[20:22:25] [PASSED] drm_gem_shmem_test_purge
[20:22:25] ================== [PASSED] drm_gem_shmem ==================
[20:22:25] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:22:25] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:22:25] [PASSED] Automatic
[20:22:25] [PASSED] Full
[20:22:25] [PASSED] Limited 16:235
[20:22:25] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:22:25] [PASSED] drm_test_check_disable_connector
[20:22:25] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:22:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:22:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:22:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:22:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:22:25] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:22:25] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:22:25] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:22:25] [PASSED] drm_test_check_output_bpc_dvi
[20:22:25] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:22:25] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:22:25] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:22:25] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:22:25] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:22:25] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:22:25] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:22:25] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:22:25] ============ drm_test_check_hdmi_color_format  =============
[20:22:25] [PASSED] AUTO -> RGB
[20:22:25] [PASSED] YCBCR422 -> YUV422
[20:22:25] [PASSED] YCBCR420 -> YUV420
[20:22:25] [PASSED] YCBCR444 -> YUV444
[20:22:25] [PASSED] RGB -> RGB
[20:22:25] ======== [PASSED] drm_test_check_hdmi_color_format =========
[20:22:25] ======== drm_test_check_hdmi_color_format_420_only  ========
[20:22:25] [PASSED] RGB should fail
[20:22:25] [PASSED] YUV444 should fail
[20:22:25] [PASSED] YUV422 should fail
[20:22:25] [PASSED] YUV420 should work
[20:22:25] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[20:22:25] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:22:25] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:22:25] [PASSED] drm_test_check_broadcast_rgb_value
[20:22:25] [PASSED] drm_test_check_bpc_8_value
[20:22:25] [PASSED] drm_test_check_bpc_10_value
[20:22:25] [PASSED] drm_test_check_bpc_12_value
[20:22:25] [PASSED] drm_test_check_format_value
[20:22:25] [PASSED] drm_test_check_tmds_char_value
[20:22:25] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:22:25] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[20:22:25] [PASSED] drm_test_check_mode_valid
[20:22:25] [PASSED] drm_test_check_mode_valid_reject
[20:22:25] [PASSED] drm_test_check_mode_valid_reject_rate
[20:22:25] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:22:25] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[20:22:25] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[20:22:25] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[20:22:25] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:22:25] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:22:25] [PASSED] drm_test_check_infoframes
[20:22:25] [PASSED] drm_test_check_reject_avi_infoframe
[20:22:25] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:22:25] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:22:25] [PASSED] drm_test_check_reject_audio_infoframe
[20:22:25] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:22:25] ================= drm_managed (2 subtests) =================
[20:22:25] [PASSED] drm_test_managed_release_action
[20:22:25] [PASSED] drm_test_managed_run_action
[20:22:25] =================== [PASSED] drm_managed ===================
[20:22:25] =================== drm_mm (6 subtests) ====================
[20:22:25] [PASSED] drm_test_mm_init
[20:22:25] [PASSED] drm_test_mm_debug
[20:22:25] [PASSED] drm_test_mm_align32
[20:22:25] [PASSED] drm_test_mm_align64
[20:22:25] [PASSED] drm_test_mm_lowest
[20:22:25] [PASSED] drm_test_mm_highest
[20:22:25] ===================== [PASSED] drm_mm ======================
[20:22:25] ============= drm_modes_analog_tv (5 subtests) =============
[20:22:25] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:22:25] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:22:25] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:22:25] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:22:25] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:22:25] =============== [PASSED] drm_modes_analog_tv ===============
[20:22:25] ============== drm_panic_helper (3 subtests) ===============
[20:22:25] ============= drm_test_panic_screen_user_map  ==============
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[20:22:25] ========= [PASSED] drm_test_panic_screen_user_map ==========
[20:22:25] ============= drm_test_panic_screen_user_page  =============
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[20:22:25] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[20:22:25] ========= [PASSED] drm_test_panic_screen_user_page =========
[20:22:25] ========== drm_test_panic_screen_user_set_pixel  ===========
[20:22:25] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[20:22:25] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[20:22:26] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[20:22:26] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[20:22:26] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[20:22:26] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[20:22:26] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[20:22:26] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[20:22:26] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[20:22:26] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[20:22:26] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[20:22:26] ================ [PASSED] drm_panic_helper =================
[20:22:26] ============== drm_plane_helper (2 subtests) ===============
[20:22:26] =============== drm_test_check_plane_state  ================
[20:22:26] [PASSED] clipping_simple
[20:22:26] [PASSED] clipping_rotate_reflect
[20:22:26] [PASSED] positioning_simple
[20:22:26] [PASSED] upscaling
[20:22:26] [PASSED] downscaling
[20:22:26] [PASSED] rounding1
[20:22:26] [PASSED] rounding2
[20:22:26] [PASSED] rounding3
[20:22:26] [PASSED] rounding4
[20:22:26] =========== [PASSED] drm_test_check_plane_state ============
[20:22:26] =========== drm_test_check_invalid_plane_state  ============
[20:22:26] [PASSED] positioning_invalid
[20:22:26] [PASSED] upscaling_invalid
[20:22:26] [PASSED] downscaling_invalid
[20:22:26] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:22:26] ================ [PASSED] drm_plane_helper =================
[20:22:26] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:22:26] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:22:26] [PASSED] None
[20:22:26] [PASSED] PAL
[20:22:26] [PASSED] NTSC
[20:22:26] [PASSED] Both, NTSC Default
[20:22:26] [PASSED] Both, PAL Default
[20:22:26] [PASSED] Both, NTSC Default, with PAL on command-line
[20:22:26] [PASSED] Both, PAL Default, with NTSC on command-line
[20:22:26] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:22:26] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:22:26] ================== drm_rect (9 subtests) ===================
[20:22:26] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:22:26] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:22:26] [PASSED] drm_test_rect_clip_scaled_clipped
[20:22:26] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:22:26] ================= drm_test_rect_intersect  =================
[20:22:26] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:22:26] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:22:26] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:22:26] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:22:26] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:22:26] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:22:26] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:22:26] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:22:26] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:22:26] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:22:26] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:22:26] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:22:26] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:22:26] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:22:26] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:22:26] ============= [PASSED] drm_test_rect_intersect =============
[20:22:26] ================ drm_test_rect_calc_hscale  ================
[20:22:26] [PASSED] normal use
[20:22:26] [PASSED] out of max range
[20:22:26] [PASSED] out of min range
[20:22:26] [PASSED] zero dst
[20:22:26] [PASSED] negative src
[20:22:26] [PASSED] negative dst
[20:22:26] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:22:26] ================ drm_test_rect_calc_vscale  ================
[20:22:26] [PASSED] normal use
[20:22:26] [PASSED] out of max range
[20:22:26] [PASSED] out of min range
[20:22:26] [PASSED] zero dst
[20:22:26] [PASSED] negative src
[20:22:26] [PASSED] negative dst
[20:22:26] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:22:26] ================== drm_test_rect_rotate  ===================
[20:22:26] [PASSED] reflect-x
[20:22:26] [PASSED] reflect-y
[20:22:26] [PASSED] rotate-0
[20:22:26] [PASSED] rotate-90
[20:22:26] [PASSED] rotate-180
[20:22:26] [PASSED] rotate-270
[20:22:26] ============== [PASSED] drm_test_rect_rotate ===============
[20:22:26] ================ drm_test_rect_rotate_inv  =================
[20:22:26] [PASSED] reflect-x
[20:22:26] [PASSED] reflect-y
[20:22:26] [PASSED] rotate-0
[20:22:26] [PASSED] rotate-90
[20:22:26] [PASSED] rotate-180
[20:22:26] [PASSED] rotate-270
[20:22:26] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:22:26] ==================== [PASSED] drm_rect =====================
[20:22:26] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:22:26] ============ drm_test_sysfb_build_fourcc_list  =============
[20:22:26] [PASSED] no native formats
[20:22:26] [PASSED] XRGB8888 as native format
[20:22:26] [PASSED] remove duplicates
[20:22:26] [PASSED] convert alpha formats
[20:22:26] [PASSED] random formats
[20:22:26] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:22:26] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:22:26] ================== drm_fixp (2 subtests) ===================
[20:22:26] [PASSED] drm_test_int2fixp
[20:22:26] [PASSED] drm_test_sm2fixp
[20:22:26] ==================== [PASSED] drm_fixp =====================
[20:22:26] ============================================================
[20:22:26] Testing complete. Ran 671 tests: passed: 671
[20:22:26] Elapsed time: 27.242s total, 1.838s configuring, 24.935s building, 0.418s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:22:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:22:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:22:38] Starting KUnit Kernel (1/1)...
[20:22:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:22:38] ============= refcount_interrupt (4 subtests) ==============
[20:22:38] [PASSED] test_single_irq_change
[20:22:38] [PASSED] test_nested_irq_change
[20:22:38] [PASSED] test_multiple_irq_change
[20:22:38] [PASSED] test_irq_save
[20:22:38] =============== [PASSED] refcount_interrupt ================
[20:22:38] ================= ttm_device (5 subtests) ==================
[20:22:38] [PASSED] ttm_device_init_basic
[20:22:38] [PASSED] ttm_device_init_multiple
[20:22:38] [PASSED] ttm_device_fini_basic
[20:22:38] [PASSED] ttm_device_init_no_vma_man
[20:22:38] ================== ttm_device_init_pools  ==================
[20:22:38] [PASSED] No DMA allocations, no DMA32 required
[20:22:38] [PASSED] DMA allocations, DMA32 required
[20:22:38] [PASSED] No DMA allocations, DMA32 required
[20:22:38] [PASSED] DMA allocations, no DMA32 required
[20:22:38] ============== [PASSED] ttm_device_init_pools ==============
[20:22:38] =================== [PASSED] ttm_device ====================
[20:22:38] ================== ttm_pool (8 subtests) ===================
[20:22:38] ================== ttm_pool_alloc_basic  ===================
[20:22:38] [PASSED] One page
[20:22:38] [PASSED] More than one page
[20:22:38] [PASSED] Above the allocation limit
[20:22:38] [PASSED] One page, with coherent DMA mappings enabled
[20:22:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:22:38] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:22:38] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:22:38] [PASSED] One page
[20:22:38] [PASSED] More than one page
[20:22:38] [PASSED] Above the allocation limit
[20:22:38] [PASSED] One page, with coherent DMA mappings enabled
[20:22:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:22:38] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:22:38] [PASSED] ttm_pool_alloc_order_caching_match
[20:22:38] [PASSED] ttm_pool_alloc_caching_mismatch
[20:22:38] [PASSED] ttm_pool_alloc_order_mismatch
[20:22:38] [PASSED] ttm_pool_free_dma_alloc
[20:22:38] [PASSED] ttm_pool_free_no_dma_alloc
[20:22:38] [PASSED] ttm_pool_fini_basic
[20:22:38] ==================== [PASSED] ttm_pool =====================
[20:22:38] ================ ttm_resource (8 subtests) =================
[20:22:38] ================= ttm_resource_init_basic  =================
[20:22:38] [PASSED] Init resource in TTM_PL_SYSTEM
[20:22:38] [PASSED] Init resource in TTM_PL_VRAM
[20:22:38] [PASSED] Init resource in a private placement
[20:22:38] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:22:38] ============= [PASSED] ttm_resource_init_basic =============
[20:22:38] [PASSED] ttm_resource_init_pinned
[20:22:38] [PASSED] ttm_resource_fini_basic
[20:22:38] [PASSED] ttm_resource_manager_init_basic
[20:22:38] [PASSED] ttm_resource_manager_usage_basic
[20:22:38] [PASSED] ttm_resource_manager_set_used_basic
[20:22:38] [PASSED] ttm_sys_man_alloc_basic
[20:22:38] [PASSED] ttm_sys_man_free_basic
[20:22:38] ================== [PASSED] ttm_resource ===================
[20:22:38] =================== ttm_tt (15 subtests) ===================
[20:22:38] ==================== ttm_tt_init_basic  ====================
[20:22:38] [PASSED] Page-aligned size
[20:22:38] [PASSED] Extra pages requested
[20:22:38] ================ [PASSED] ttm_tt_init_basic ================
[20:22:38] [PASSED] ttm_tt_init_misaligned
[20:22:38] [PASSED] ttm_tt_fini_basic
[20:22:38] [PASSED] ttm_tt_fini_sg
[20:22:38] [PASSED] ttm_tt_fini_shmem
[20:22:38] [PASSED] ttm_tt_create_basic
[20:22:38] [PASSED] ttm_tt_create_invalid_bo_type
[20:22:38] [PASSED] ttm_tt_create_ttm_exists
[20:22:38] [PASSED] ttm_tt_create_failed
[20:22:38] [PASSED] ttm_tt_destroy_basic
[20:22:38] [PASSED] ttm_tt_populate_null_ttm
[20:22:38] [PASSED] ttm_tt_populate_populated_ttm
[20:22:38] [PASSED] ttm_tt_unpopulate_basic
[20:22:38] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:22:38] [PASSED] ttm_tt_swapin_basic
[20:22:38] ===================== [PASSED] ttm_tt ======================
[20:22:38] =================== ttm_bo (14 subtests) ===================
[20:22:38] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:22:38] [PASSED] Cannot be interrupted and sleeps
[20:22:38] [PASSED] Cannot be interrupted, locks straight away
[20:22:38] [PASSED] Can be interrupted, sleeps
[20:22:38] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:22:38] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:22:38] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:22:38] [PASSED] ttm_bo_reserve_double_resv
[20:22:38] [PASSED] ttm_bo_reserve_interrupted
[20:22:38] [PASSED] ttm_bo_reserve_deadlock
[20:22:38] [PASSED] ttm_bo_unreserve_basic
[20:22:38] [PASSED] ttm_bo_unreserve_pinned
[20:22:38] [PASSED] ttm_bo_unreserve_bulk
[20:22:38] [PASSED] ttm_bo_fini_basic
[20:22:38] [PASSED] ttm_bo_fini_shared_resv
[20:22:38] [PASSED] ttm_bo_pin_basic
[20:22:38] [PASSED] ttm_bo_pin_unpin_resource
[20:22:38] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:22:38] ===================== [PASSED] ttm_bo ======================
[20:22:38] ============== ttm_bo_validate (22 subtests) ===============
[20:22:38] ============== ttm_bo_init_reserved_sys_man  ===============
[20:22:38] [PASSED] Buffer object for userspace
[20:22:38] [PASSED] Kernel buffer object
[20:22:38] [PASSED] Shared buffer object
[20:22:38] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:22:38] ============== ttm_bo_init_reserved_mock_man  ==============
[20:22:38] [PASSED] Buffer object for userspace
[20:22:38] [PASSED] Kernel buffer object
[20:22:38] [PASSED] Shared buffer object
[20:22:38] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:22:38] [PASSED] ttm_bo_init_reserved_resv
[20:22:38] ================== ttm_bo_validate_basic  ==================
[20:22:38] [PASSED] Buffer object for userspace
[20:22:38] [PASSED] Kernel buffer object
[20:22:38] [PASSED] Shared buffer object
[20:22:38] ============== [PASSED] ttm_bo_validate_basic ==============
[20:22:38] [PASSED] ttm_bo_validate_invalid_placement
[20:22:38] ============= ttm_bo_validate_same_placement  ==============
[20:22:38] [PASSED] System manager
[20:22:38] [PASSED] VRAM manager
[20:22:38] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:22:38] [PASSED] ttm_bo_validate_failed_alloc
[20:22:38] [PASSED] ttm_bo_validate_pinned
[20:22:38] [PASSED] ttm_bo_validate_busy_placement
[20:22:38] ================ ttm_bo_validate_multihop  =================
[20:22:38] [PASSED] Buffer object for userspace
[20:22:38] [PASSED] Kernel buffer object
[20:22:38] [PASSED] Shared buffer object
[20:22:38] ============ [PASSED] ttm_bo_validate_multihop =============
[20:22:38] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:22:38] [PASSED] Buffer object in system domain, no page vector
[20:22:38] [PASSED] Buffer object in system domain with an existing page vector
[20:22:38] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:22:38] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:22:38] [PASSED] Buffer object for userspace
[20:22:38] [PASSED] Kernel buffer object
[20:22:38] [PASSED] Shared buffer object
[20:22:38] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:22:38] [PASSED] ttm_bo_validate_move_fence_signaled
[20:22:38] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:22:38] [PASSED] Waits for GPU
[20:22:38] [PASSED] Tries to lock straight away
[20:22:38] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:22:38] [PASSED] ttm_bo_validate_swapout
[20:22:38] [PASSED] ttm_bo_validate_happy_evict
[20:22:38] [PASSED] ttm_bo_validate_all_pinned_evict
[20:22:38] [PASSED] ttm_bo_validate_allowed_only_evict
[20:22:38] [PASSED] ttm_bo_validate_deleted_evict
[20:22:38] [PASSED] ttm_bo_validate_busy_domain_evict
[20:22:38] [PASSED] ttm_bo_validate_evict_gutting
[20:22:38] [PASSED] ttm_bo_validate_recrusive_evict
[20:22:38] ================= [PASSED] ttm_bo_validate =================
[20:22:38] ============================================================
[20:22:38] Testing complete. Ran 106 tests: passed: 106
[20:22:38] Elapsed time: 11.991s total, 1.795s configuring, 9.981s building, 0.183s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[20:22:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:22:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:22:48] Starting KUnit Kernel (1/1)...
[20:22:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:22:48] ============= refcount_interrupt (4 subtests) ==============
[20:22:48] [PASSED] test_single_irq_change
[20:22:48] [PASSED] test_nested_irq_change
[20:22:48] [PASSED] test_multiple_irq_change
[20:22:48] [PASSED] test_irq_save
[20:22:48] =============== [PASSED] refcount_interrupt ================
[20:22:48] =============== dma-buf-fence (12 subtests) ================
[20:22:48] [PASSED] test_sanitycheck
[20:22:48] [PASSED] test_signaling
[20:22:48] [PASSED] test_add_callback
[20:22:48] [PASSED] test_late_add_callback
[20:22:48] [PASSED] test_rm_callback
[20:22:48] [PASSED] test_late_rm_callback
[20:22:48] [PASSED] test_status
[20:22:48] [PASSED] test_error
[20:22:48] [PASSED] test_wait
[20:22:48] [PASSED] test_wait_timeout
[20:22:48] [PASSED] test_stub
[20:22:48] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[20:22:48] ================== [PASSED] dma-buf-fence ==================
[20:22:48] ============ dma-buf-fence-chain (11 subtests) =============
[20:22:48] [PASSED] test_sanitycheck
[20:22:48] [PASSED] test_find_seqno
[20:22:48] [PASSED] test_find_signaled
[20:22:48] [PASSED] test_find_out_of_order
[20:22:53] [PASSED] test_find_gap
[20:22:54] [PASSED] test_find_race
[20:22:54] [PASSED] test_signal_forward
[20:22:54] [PASSED] test_signal_backward
[20:22:54] [PASSED] test_wait_forward
[20:22:54] [PASSED] test_wait_backward
[20:22:54] [PASSED] test_wait_random
[20:22:54] =============== [PASSED] dma-buf-fence-chain ===============
[20:22:54] ============ dma-buf-fence-unwrap (10 subtests) ============
[20:22:54] [PASSED] test_sanitycheck
[20:22:54] [PASSED] test_unwrap_array
[20:22:54] [PASSED] test_unwrap_chain
[20:22:54] [PASSED] test_unwrap_chain_array
[20:22:54] [PASSED] test_unwrap_merge
[20:22:54] [PASSED] test_unwrap_merge_duplicate
[20:22:54] [PASSED] test_unwrap_merge_seqno
[20:22:54] [PASSED] test_unwrap_merge_order
[20:22:54] [PASSED] test_unwrap_merge_complex
[20:22:54] [PASSED] test_unwrap_merge_complex_seqno
[20:22:54] ============== [PASSED] dma-buf-fence-unwrap ===============
[20:22:54] ================ dma-buf-resv (5 subtests) =================
[20:22:54] [PASSED] test_sanitycheck
[20:22:54] ===================== test_signaling  ======================
[20:22:54] [PASSED] kernel
[20:22:54] [PASSED] write
[20:22:54] [PASSED] read
[20:22:54] [PASSED] bookkeep
[20:22:54] ================= [PASSED] test_signaling ==================
[20:22:54] ====================== test_for_each  ======================
[20:22:54] [PASSED] kernel
[20:22:54] [PASSED] write
[20:22:54] [PASSED] read
[20:22:54] [PASSED] bookkeep
[20:22:54] ================== [PASSED] test_for_each ==================
[20:22:54] ================= test_for_each_unlocked  ==================
[20:22:54] [PASSED] kernel
[20:22:54] [PASSED] write
[20:22:54] [PASSED] read
[20:22:54] [PASSED] bookkeep
[20:22:54] ============= [PASSED] test_for_each_unlocked ==============
[20:22:54] ===================== test_get_fences  =====================
[20:22:54] [PASSED] kernel
[20:22:54] [PASSED] write
[20:22:54] [PASSED] read
[20:22:54] [PASSED] bookkeep
[20:22:54] ================= [PASSED] test_get_fences =================
[20:22:54] ================== [PASSED] dma-buf-resv ===================
[20:22:54] ============================================================
[20:22:54] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[20:22:54] Elapsed time: 15.799s total, 1.858s configuring, 8.617s building, 5.273s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for i2c: designware: Add TI TDA54 I2C support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2749 bytes --]

== Series Details ==

Series: i2c: designware: Add TI TDA54 I2C support (rev2)
URL   : https://patchwork.freedesktop.org/series/175011/
State : success

== Summary ==

CI Bug Log - changes from xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74_BAT -> xe-pw-175011v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-175011v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@engine:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2] ([Intel XE#9109])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/bat-ptl-2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/bat-ptl-2/igt@xe_waitfence@engine.html

  
#### Possible fixes ####

  * igt@xe_waitfence@abstime:
    - bat-ptl-2:          [TIMEOUT][3] ([Intel XE#9152]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/bat-ptl-2/igt@xe_waitfence@abstime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/bat-ptl-2/igt@xe_waitfence@abstime.html
    - bat-wcl-1:          [TIMEOUT][5] ([Intel XE#9226]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/bat-wcl-1/igt@xe_waitfence@abstime.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/bat-wcl-1/igt@xe_waitfence@abstime.html

  * igt@xe_waitfence@engine:
    - bat-wcl-1:          [FAIL][7] ([Intel XE#9103]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/bat-wcl-1/igt@xe_waitfence@engine.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/bat-wcl-1/igt@xe_waitfence@engine.html

  
  [Intel XE#9103]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9103
  [Intel XE#9109]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9109
  [Intel XE#9152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9152
  [Intel XE#9226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9226


Build changes
-------------

  * Linux: xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74 -> xe-pw-175011v2

  IGT_9113: 691cc6fd50d5a3f6f2b5805c9698af1df28f6830 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74: d3e3b787ba0daa01200907e0efeaa3f7da201a74
  xe-pw-175011v2: 175011v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/index.html

[-- Attachment #2: Type: text/html, Size: 3371 bytes --]

✓ Xe.CI.FULL: success for i2c: designware: Add TI TDA54 I2C support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 95900 bytes --]

== Series Details ==

Series: i2c: designware: Add TI TDA54 I2C support (rev2)
URL   : https://patchwork.freedesktop.org/series/175011/
State : success

== Summary ==

CI Bug Log - changes from xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74_FULL -> xe-pw-175011v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-175011v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-read:
    - shard-lnl:          NOTRUN -> [SKIP][1] ([Intel XE#1125] / [Intel XE#7312])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@intel_hwmon@hwmon-read.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-ptl:          NOTRUN -> [SKIP][2] ([Intel XE#5947])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-ptl:          NOTRUN -> [SKIP][3] ([Intel XE#5901]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +5 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2328] / [Intel XE#7367])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][9] ([Intel XE#5808]) +6 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#7679])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#7679]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#367]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#367])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][14] ([Intel XE#5823] / [Intel XE#6918]) +4 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2652]) +7 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][18] ([Intel XE#5822]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][19] ([Intel XE#7084] / [Intel XE#8150])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-edp-1:
    - shard-ptl:          [PASS][20] -> [ABORT][21] ([Intel XE#9378]) +1 other test abort
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-ptl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-edp-1.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#3432])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2887]) +12 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2325] / [Intel XE#7358])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lim-lut1d:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7358])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lim-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim:
    - shard-ptl:          NOTRUN -> [SKIP][26] ([Intel XE#8391]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim-lut1d:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7358]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim-lut1d.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#373]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2252]) +4 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-ptl:          NOTRUN -> [SKIP][30] ([Intel XE#2252]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_color_pipeline@plane-ctm3x4@pipe-a-plane-3:
    - shard-ptl:          NOTRUN -> [SKIP][31] ([Intel XE#6969]) +7 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_color_pipeline@plane-ctm3x4@pipe-a-plane-3.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lim-lut1d@pipe-d-plane-1:
    - shard-bmg:          NOTRUN -> [FAIL][32] ([Intel XE#9333]) +24 other tests fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lim-lut1d@pipe-d-plane-1.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lim@pipe-c-plane-2:
    - shard-lnl:          NOTRUN -> [FAIL][33] ([Intel XE#9333]) +9 other tests fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lim@pipe-c-plane-2.html

  * igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-b-plane-4:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#6969]) +15 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-b-plane-4.html

  * igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4@pipe-b-plane-4:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#6969]) +5 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4@pipe-b-plane-4.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-ptl:          NOTRUN -> [SKIP][36] ([Intel XE#5832] / [Intel XE#6974])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#6974]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#307] / [Intel XE#6974])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][39] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2320]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-ptl:          NOTRUN -> [SKIP][41] ([Intel XE#5900]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#1424])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-ptl:          NOTRUN -> [SKIP][45] ([Intel XE#5962])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-ptl:          NOTRUN -> [SKIP][46] ([Intel XE#5962] / [Intel XE#7343])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-ptl:          NOTRUN -> [SKIP][48] ([Intel XE#6035])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2286] / [Intel XE#6035])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-fractional-bpp-ultrajoiner:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#8265]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_dsc@dsc-fractional-bpp-ultrajoiner.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#8265]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-ptl:          NOTRUN -> [SKIP][52] ([Intel XE#5907]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4422] / [Intel XE#7442])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_feature_discovery@display-4x:
    - shard-ptl:          NOTRUN -> [SKIP][54] ([Intel XE#7344])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2375])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@dsc:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#8586])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_feature_discovery@dsc.html

  * igt@kms_feature_discovery@hdr:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#8586])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_feature_discovery@hdr.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-ptl:          NOTRUN -> [SKIP][58] ([Intel XE#2316])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@wf_vblank-ts-check@b-edp1:
    - shard-ptl:          [PASS][59] -> [FAIL][60] ([Intel XE#3098] / [Intel XE#9171]) +1 other test fail
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-ptl-8/igt@kms_flip@wf_vblank-ts-check@b-edp1.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-3/igt@kms_flip@wf_vblank-ts-check@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#7179])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#7178] / [Intel XE#7351])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#7178] / [Intel XE#7349])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-ptl:          NOTRUN -> [SKIP][64] ([Intel XE#7178]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7178] / [Intel XE#7351])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2311]) +44 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][67] ([Intel XE#7061] / [Intel XE#7356])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-slowdraw:
    - shard-ptl:          NOTRUN -> [SKIP][68] ([Intel XE#5800] / [Intel XE#6312]) +4 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_frontbuffer_tracking@drrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-spr-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#6312]) +3 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#7905]) +13 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#4141]) +8 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#7061] / [Intel XE#7356])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#6312] / [Intel XE#651]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2352] / [Intel XE#7399])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][76] ([Intel XE#6312]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#7865]) +6 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#7061])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#7061]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-4:
    - shard-ptl:          NOTRUN -> [SKIP][80] ([Intel XE#7865]) +7 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-4.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][81] ([Intel XE#7061])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#2350] / [Intel XE#7503])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][83] ([Intel XE#5812]) +28 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#656] / [Intel XE#7905]) +9 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#2313]) +44 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-move.html

  * igt@kms_hdmi_audio_bw@dpms-audio-recovery:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#9312])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_hdmi_audio_bw@dpms-audio-recovery.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][87] -> [INCOMPLETE][88] ([Intel XE#9320]) +1 other test incomplete
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-10/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb2101010.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-1/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#6901])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#7086] / [Intel XE#7390])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-ptl:          NOTRUN -> [SKIP][91] ([Intel XE#7591])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#7283]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-ptl:          NOTRUN -> [SKIP][93] ([Intel XE#7283])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#7283]) +2 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-ptl:          NOTRUN -> [SKIP][95] ([Intel XE#4596] / [Intel XE#5854])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-ptl:          NOTRUN -> [SKIP][96] ([Intel XE#5879] / [Intel XE#7343])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-ptl:          NOTRUN -> [SKIP][97] ([Intel XE#5959])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b:
    - shard-ptl:          NOTRUN -> [SKIP][98] ([Intel XE#6886]) +4 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888:
    - shard-ptl:          NOTRUN -> [SKIP][101] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420:
    - shard-ptl:          NOTRUN -> [SKIP][102] ([Intel XE#8396]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-lnl:          NOTRUN -> [SKIP][104] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#2893] / [Intel XE#7304])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#4608])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#4608] / [Intel XE#7304])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][109] ([Intel XE#5858])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-b-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][110] ([Intel XE#5858] / [Intel XE#7304]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][111] ([Intel XE#1489]) +6 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-ptl:          NOTRUN -> [SKIP][112] ([Intel XE#7304])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-bmg:          NOTRUN -> [SKIP][113] ([Intel XE#2387] / [Intel XE#7429])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr-suspend@edp-1:
    - shard-ptl:          [PASS][114] -> [ABORT][115] ([Intel XE#9362]) +2 other tests abort
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-ptl-6/igt@kms_psr@fbc-psr-suspend@edp-1.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-6/igt@kms_psr@fbc-psr-suspend@edp-1.html

  * igt@kms_psr@fbc-psr2-no-drrs:
    - shard-ptl:          NOTRUN -> [SKIP][116] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_psr@fbc-psr2-no-drrs.html

  * igt@kms_psr@pr-primary-blt:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#1406]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@kms_psr@pr-primary-blt.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-ptl:          NOTRUN -> [SKIP][118] ([Intel XE#1406]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_psr@pr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@kms_psr@pr-suspend.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-ptl:          NOTRUN -> [SKIP][121] ([Intel XE#5813])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#3904] / [Intel XE#7342])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_sharpness_filter@filter-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][123] ([Intel XE#6503]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@kms_sharpness_filter@filter-toggle.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-ptl:          NOTRUN -> [SKIP][124] ([Intel XE#5848])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][125] ([Intel XE#2168] / [Intel XE#7444])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_vrr@lobf.html

  * igt@kms_vrr@negative-basic:
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#1499] / [Intel XE#9271])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@kms_vrr@negative-basic.html

  * igt@xe_ccs@suspend-resume:
    - shard-ptl:          NOTRUN -> [ABORT][127] ([Intel XE#9362]) +1 other test abort
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_ccs@suspend-resume.html

  * igt@xe_ccs@vm-bind-fault-mode-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][128] ([Intel XE#7644])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@xe_ccs@vm-bind-fault-mode-decompress.html

  * igt@xe_create@create-contexts:
    - shard-lnl:          [PASS][129] -> [ABORT][130] ([Intel XE#8007])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-lnl-3/igt@xe_create@create-contexts.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-4/igt@xe_create@create-contexts.html

  * igt@xe_evict@evict-beng-cm-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][131] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html

  * igt@xe_evict@evict-beng-small:
    - shard-ptl:          NOTRUN -> [SKIP][132] ([Intel XE#5764]) +2 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_evict@evict-beng-small.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#7482]) +3 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind.html

  * igt@xe_exec_balancer@twice-virtual-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][134] ([Intel XE#7482]) +5 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_exec_balancer@twice-virtual-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#1392]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-ptl:          NOTRUN -> [SKIP][136] ([Intel XE#5575] / [Intel XE#7484]) +2 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#2322] / [Intel XE#7372]) +4 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][138] ([Intel XE#8374]) +2 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch.html

  * igt@xe_exec_fault_mode@many-multi-queue-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][139] ([Intel XE#8374]) +5 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_exec_fault_mode@many-multi-queue-rebind.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race:
    - shard-ptl:          NOTRUN -> [SKIP][140] ([Intel XE#8374]) +2 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#8364]) +17 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem:
    - shard-ptl:          NOTRUN -> [SKIP][142] ([Intel XE#8364]) +10 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][143] ([Intel XE#8364]) +8 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_exec_multi_queue@two-queues-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#8369]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary.html

  * igt@xe_exec_reset@cm-multi-queue-close-fd:
    - shard-ptl:          NOTRUN -> [SKIP][145] ([Intel XE#8369]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_exec_reset@cm-multi-queue-close-fd.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][146] ([Intel XE#9130])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@xe_exec_reset@gt-reset-fault-injection.html
    - shard-lnl:          NOTRUN -> [DMESG-WARN][147] ([Intel XE#9130])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@xe_exec_reset@gt-reset-fault-injection.html

  * igt@xe_exec_system_allocator@many-stride-new-prefetch:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][148] ([Intel XE#7098] / [Intel XE#8159])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@xe_exec_system_allocator@many-stride-new-prefetch.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-multi-vma:
    - shard-ptl:          NOTRUN -> [SKIP][149] ([Intel XE#6196])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-multi-vma.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr:
    - shard-ptl:          NOTRUN -> [SKIP][150] ([Intel XE#8378]) +4 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_exec_threads@threads-multi-queue-fd-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][151] ([Intel XE#8378]) +5 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-bmg:          NOTRUN -> [SKIP][152] ([Intel XE#2833])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][153] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_media_fill@media-fill.html

  * igt@xe_mempage_offline@inject-duplicate-page:
    - shard-lnl:          NOTRUN -> [SKIP][154] ([Intel XE#9203])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_mempage_offline@inject-duplicate-page.html

  * igt@xe_mmap@pci-membarrier:
    - shard-ptl:          NOTRUN -> [SKIP][155] ([Intel XE#5100] / [Intel XE#7408])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_mmap@pci-membarrier.html

  * igt@xe_module_load@unload:
    - shard-bmg:          [PASS][156] -> [ABORT][157] ([Intel XE#8007]) +1 other test abort
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-8/igt@xe_module_load@unload.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-4/igt@xe_module_load@unload.html

  * igt@xe_multigpu_svm@mgpu-coherency-conflict:
    - shard-bmg:          NOTRUN -> [SKIP][158] ([Intel XE#6964]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_multigpu_svm@mgpu-coherency-conflict.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#6964])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_multigpu_svm@mgpu-latency-basic:
    - shard-ptl:          NOTRUN -> [SKIP][160] ([Intel XE#6964]) +2 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_multigpu_svm@mgpu-latency-basic.html

  * igt@xe_page_reclaim@binds-1g-partial:
    - shard-bmg:          NOTRUN -> [SKIP][161] ([Intel XE#7793])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_page_reclaim@binds-1g-partial.html

  * igt@xe_page_reclaim@invalid-1g:
    - shard-lnl:          NOTRUN -> [SKIP][162] ([Intel XE#7793])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_page_reclaim@invalid-1g.html

  * igt@xe_page_reclaim@pde-vs-pd:
    - shard-ptl:          NOTRUN -> [SKIP][163] ([Intel XE#7793])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_page_reclaim@pde-vs-pd.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][164] ([Intel XE#2245] / [Intel XE#7590])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-bmg:          NOTRUN -> [SKIP][165] ([Intel XE#7590])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-ptl:          NOTRUN -> [SKIP][166] ([Intel XE#5741])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@s3-vm-bind-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][167] ([Intel XE#6867])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-7/igt@xe_pm@s3-vm-bind-prefetch.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][168] ([Intel XE#584] / [Intel XE#7369])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-bmg:          NOTRUN -> [SKIP][169] ([Intel XE#4733] / [Intel XE#7417]) +2 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-ptl:          NOTRUN -> [SKIP][170] ([Intel XE#6019])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-invalid-query:
    - shard-bmg:          NOTRUN -> [SKIP][171] ([Intel XE#944]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_query@multigpu-query-invalid-query.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-lnl:          NOTRUN -> [SKIP][172] ([Intel XE#4130] / [Intel XE#7366])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-1/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  * igt@xe_sriov_flr@flr-basic:
    - shard-lnl:          NOTRUN -> [SKIP][173] ([Intel XE#7569])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@xe_sriov_flr@flr-basic.html

  * igt@xe_survivability@i2c-functionality:
    - shard-ptl:          NOTRUN -> [SKIP][174] ([Intel XE#8415] / [Intel XE#8432])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@xe_survivability@i2c-functionality.html

  
#### Possible fixes ####

  * igt@core_getversion@all-cards:
    - shard-bmg:          [FAIL][175] -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@core_getversion@all-cards.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@core_getversion@all-cards.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-bmg:          [SKIP][177] -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@device_reset@unbind-reset-rebind.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [FAIL][179] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2:
    - shard-bmg:          [FAIL][181] ([Intel XE#6078]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-dp-2:
    - shard-bmg:          [DMESG-WARN][183] ([Intel XE#9390]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-dp-2.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3:
    - shard-bmg:          [INCOMPLETE][185] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-ptl:          [ABORT][187] ([Intel XE#9362]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-ptl-7/igt@kms_fbcon_fbt@fbc-suspend.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [DMESG-WARN][189] ([Intel XE#9365]) -> [PASS][190] +1 other test pass
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-10/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-bmg:          [ABORT][191] ([Intel XE#9093]) -> [PASS][192] +2 other tests pass
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_properties@connector-properties-legacy:
    - shard-bmg:          [SKIP][193] ([Intel XE#8589]) -> [PASS][194] +145 other tests pass
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_properties@connector-properties-legacy.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_properties@connector-properties-legacy.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-ptl:          [FAIL][195] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-ptl-2/igt@kms_vrr@flip-basic-fastset.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-3/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1:
    - shard-ptl:          [FAIL][197] ([Intel XE#6293] / [Intel XE#7397]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-ptl-2/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-ptl-3/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html

  * igt@xe_compute_preempt@compute-preempt-many-vram:
    - shard-bmg:          [ABORT][199] ([Intel XE#7893] / [Intel XE#9250] / [Intel XE#9279]) -> [PASS][200] +1 other test pass
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-3/igt@xe_compute_preempt@compute-preempt-many-vram.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_compute_preempt@compute-preempt-many-vram.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-bmg:          [DMESG-WARN][201] ([Intel XE#7774]) -> [PASS][202] +1 other test pass
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][203] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_fault_mode@atomic-many:
    - shard-bmg:          [FAIL][205] ([Intel XE#8578]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-6/igt@xe_exec_fault_mode@atomic-many.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-5/igt@xe_exec_fault_mode@atomic-many.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-prefetch-race:
    - shard-bmg:          [ABORT][207] ([Intel XE#6652]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-prefetch-race.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-prefetch-race.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-lnl:          [FAIL][209] ([Intel XE#9096] / [Intel XE#9297]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-lnl-6/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-2/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-lnl:          [FAIL][211] ([Intel XE#9096]) -> [PASS][212]
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-lnl-1/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-3/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [SKIP][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [PASS][257], [PASS][258], [PASS][259], [PASS][260], [PASS][261], [PASS][262], [PASS][263])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-4/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-4/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-4/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-8/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-8/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-8/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-10/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-10/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-7/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-7/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-9/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-9/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-2/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-2/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-2/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-6/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-6/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-6/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-3/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-3/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-3/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-1/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-1/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-5/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-5/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-4/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-4/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-7/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-10/igt@xe_module_load@load.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-10/igt@xe_module_load@load.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-5/igt@xe_module_load@load.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-2/igt@xe_module_load@load.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-2/igt@xe_module_load@load.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_module_load@load.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_module_load@load.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_module_load@load.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-8/igt@xe_module_load@load.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_module_load@load.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_module_load@load.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-9/igt@xe_module_load@load.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-10/igt@xe_module_load@load.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@xe_module_load@load.html

  * igt@xe_pm@s4-basic:
    - shard-lnl:          [ABORT][264] ([Intel XE#9362]) -> [PASS][265] +1 other test pass
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-lnl-8/igt@xe_pm@s4-basic.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-lnl-8/igt@xe_pm@s4-basic.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-bmg:          [SKIP][266] ([Intel XE#8589]) -> [SKIP][267] ([Intel XE#2327]) +1 other test skip
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-bmg:          [SKIP][268] ([Intel XE#8589]) -> [SKIP][269] ([Intel XE#1124])
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][270] ([Intel XE#8589]) -> [SKIP][271] ([Intel XE#2652])
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][272] ([Intel XE#8589]) -> [SKIP][273] ([Intel XE#2887]) +3 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d:
    - shard-bmg:          [SKIP][274] ([Intel XE#8589]) -> [SKIP][275] ([Intel XE#7358])
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-bmg:          [SKIP][276] ([Intel XE#8589]) -> [SKIP][277] ([Intel XE#2252]) +1 other test skip
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_chamelium_hpd@dp-hpd.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601:
    - shard-bmg:          [SKIP][278] ([Intel XE#8589]) -> [FAIL][279] ([Intel XE#9333])
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-bmg:          [SKIP][280] ([Intel XE#8589]) -> [SKIP][281] ([Intel XE#6974])
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-bmg:          [SKIP][282] ([Intel XE#8589]) -> [SKIP][283] ([Intel XE#2320]) +1 other test skip
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          [SKIP][284] ([Intel XE#8589]) -> [SKIP][285] ([Intel XE#2321] / [Intel XE#7355])
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-512x512.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          [SKIP][286] ([Intel XE#8589]) -> [SKIP][287] ([Intel XE#4331] / [Intel XE#7227])
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-bmg:          [SKIP][288] ([Intel XE#8589]) -> [SKIP][289] ([Intel XE#8265])
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          [FAIL][290] -> [SKIP][291] ([Intel XE#2311])
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt:
    - shard-bmg:          [SKIP][292] ([Intel XE#8589]) -> [SKIP][293] ([Intel XE#7061]) +2 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][294] ([Intel XE#8589]) -> [SKIP][295] ([Intel XE#4141]) +2 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-mmap-wc:
    - shard-bmg:          [SKIP][296] ([Intel XE#8589]) -> [SKIP][297] ([Intel XE#7061] / [Intel XE#7356])
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-mmap-wc.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][298] ([Intel XE#8589]) -> [SKIP][299] ([Intel XE#2311]) +10 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-render.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][300] ([Intel XE#8589]) -> [SKIP][301] ([Intel XE#2313]) +13 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][302] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][303] ([Intel XE#3544])
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-bmg:          [SKIP][304] ([Intel XE#8589]) -> [SKIP][305] ([Intel XE#4329] / [Intel XE#6912] / [Intel XE#7375])
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping:
    - shard-bmg:          [SKIP][306] ([Intel XE#8589]) -> [SKIP][307] ([Intel XE#7283])
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][308] ([Intel XE#8589]) -> [SKIP][309] ([Intel XE#5021] / [Intel XE#7377])
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-bmg:          [SKIP][310] ([Intel XE#8589]) -> [SKIP][311] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870]) +1 other test skip
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_pm_backlight@basic-brightness.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          [SKIP][312] ([Intel XE#8589]) -> [SKIP][313] ([Intel XE#2387] / [Intel XE#7429])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_psr2_su@page_flip-p010.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-bmg:          [SKIP][314] ([Intel XE#8589]) -> [SKIP][315] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_psr@psr2-cursor-plane-move.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_sharpness_filter@invalid-plane-with-filter:
    - shard-bmg:          [SKIP][316] ([Intel XE#8589]) -> [SKIP][317] ([Intel XE#6503])
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@kms_sharpness_filter@invalid-plane-with-filter.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_sharpness_filter@invalid-plane-with-filter.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][318] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][319] ([Intel XE#2426] / [Intel XE#5848])
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][320] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][321] ([Intel XE#2509] / [Intel XE#7437])
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_evict@evict-small-multi-queue-priority-cm:
    - shard-bmg:          [SKIP][322] ([Intel XE#8589]) -> [SKIP][323] ([Intel XE#8370])
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_evict@evict-small-multi-queue-priority-cm.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_evict@evict-small-multi-queue-priority-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
    - shard-bmg:          [SKIP][324] ([Intel XE#8589]) -> [SKIP][325] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-prefetch:
    - shard-bmg:          [SKIP][326] ([Intel XE#8589]) -> [SKIP][327] ([Intel XE#8374]) +2 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-prefetch.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-prefetch.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr-invalidate:
    - shard-bmg:          [SKIP][328] ([Intel XE#8589]) -> [SKIP][329] ([Intel XE#8364]) +6 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr-invalidate.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-cm-userptr:
    - shard-bmg:          [SKIP][330] ([Intel XE#8589]) -> [SKIP][331] ([Intel XE#8378])
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-userptr.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_exec_threads@threads-multi-queue-cm-userptr.html

  * igt@xe_pat@l2-flush-opt-svm-pat-restrict:
    - shard-bmg:          [SKIP][332] ([Intel XE#8589]) -> [SKIP][333] ([Intel XE#7590])
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          [SKIP][334] ([Intel XE#8589]) -> [SKIP][335] ([Intel XE#2284] / [Intel XE#7370])
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_pm@d3cold-mocs.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_pm@d3cold-mocs.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          [SKIP][336] ([Intel XE#8589]) -> [SKIP][337] ([Intel XE#944])
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74/shard-bmg-5/igt@xe_query@multigpu-query-uc-fw-version-huc.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/shard-bmg-6/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
  [Intel XE#5832]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5832
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
  [Intel XE#5879]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5879
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5947
  [Intel XE#5959]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5959
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6293
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6867]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6867
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7227
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7444]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7444
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7503
  [Intel XE#7569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7569
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7893
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8159
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
  [Intel XE#8432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8432
  [Intel XE#8578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8578
  [Intel XE#8586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8586
  [Intel XE#8589]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8589
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#9093]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9093
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9171]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9171
  [Intel XE#9203]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9203
  [Intel XE#9250]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9250
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9279
  [Intel XE#9297]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9297
  [Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
  [Intel XE#9320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9320
  [Intel XE#9333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9333
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
  [Intel XE#9378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9378
  [Intel XE#9390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9390
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74 -> xe-pw-175011v2

  IGT_9113: 691cc6fd50d5a3f6f2b5805c9698af1df28f6830 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5827-d3e3b787ba0daa01200907e0efeaa3f7da201a74: d3e3b787ba0daa01200907e0efeaa3f7da201a74
  xe-pw-175011v2: 175011v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175011v2/index.html

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Re: [PATCH v3 0/3] i2c: designware: Add TI TDA54 I2C support

[Mark Brown]

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On Fri, Sep 25, 2026 at 12:26:27PM +0530, Aniket Limaye wrote:

> Add new compatible and update driver to support Synopsys Advanced I2C
> Controller (DWC_i2c [0]) present on TI TDA54 SoC. This is needed since
> this controller differs from the existing designware i2c (DW_apb_i2c
> [1]) in its register offsets and some register definitions.

> The new compatible updates driver logic due to changes in register
> definitions:

I'm working with a SoC with what looks to be another instance of this
new version of the DesignWare I2C controller - I saw your discussion
with Andy and the conclusion that a separate driver would be good.  I'm
really keen to help out with getting the support for these IPs upstream
however I can, not sure what your plans/thoughts are there?

The I2C needs of the systems I'm using are fairly basic so I should only
need a small subset of the capabilities that'll be visible in your
systems, the only thing I can think might not come up for you is that my
systems are servers so will be using ACPI rather than DT.

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