Re: [PATCH 2/3] cxl/pci: Program the Port GPF timeouts before caching the DVSEC

[Jonathan Cameron <jic23@kernel.org>]

On Tue, 22 Sep 2026 18:00:12 +0800
Guixin Liu <kanie@linux.alibaba.com> wrote:

> cxl_gpf_port_setup() caches the Port GPF DVSEC offset in the dport
> before programming the phase timeouts, and ignores the return value
> of both update_gpf_port_dvsec() calls: the function always reports
> success.
> 
> A failing config write is therefore not only silent, it is also
> permanent: the timeouts stay at the hardware defaults instead of the
> maximum flush window the kernel is asking for, and the cached offset
> keeps any later endpoint attach from retrying the update.
> 
> Propagate the errors and cache the offset only after both phases are
> programmed, so the next endpoint attach retries the setup.
> 
> Fixes: 6af941db6a60 ("cxl/pci: Update Port GPF timeout only when the first EP attaching")
> Cc: stable@vger.kernel.org
> Assisted-by: LLM
> Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>

Handling config write fails is a bit of an esoteric corner.
I don't mind it being improved but not for me that important unless
there is some reason we see these in the real world?

Definitely good to make it return errno rather than the pcibios_err_
though so overall I think this is good to have.

Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

> ---
>  drivers/cxl/core/pci.c | 30 +++++++++++++++++++++---------
>  1 file changed, 21 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index e31aad7a525a..1f470ab0df3b 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -840,7 +840,7 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
>  
>  	rc = pci_read_config_word(pdev, dvsec + offset, &ctrl);
>  	if (rc)
> -		return rc;
> +		return pcibios_err_to_errno(rc);
>  
>  	if (FIELD_GET(base, ctrl) == GPF_TIMEOUT_BASE_MAX &&
>  	    FIELD_GET(scale, ctrl) == GPF_TIMEOUT_SCALE_MAX)
> @@ -850,11 +850,17 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
>  	ctrl |= FIELD_PREP(scale, GPF_TIMEOUT_SCALE_MAX);
>  
>  	rc = pci_write_config_word(pdev, dvsec + offset, ctrl);
> -	if (!rc)
> -		pci_dbg(pdev, "Port GPF phase %d timeout: %d0 secs\n",
> -			phase, GPF_TIMEOUT_BASE_MAX);
> +	if (rc) {
> +		rc = pcibios_err_to_errno(rc);
> +		pci_warn(pdev, "Port GPF phase %d timeout write failed: %d\n",
> +			 phase, rc);

> +		return rc;
> +	}
>  
> -	return rc;
> +	pci_dbg(pdev, "Port GPF phase %d timeout: %d0 secs\n",
> +		phase, GPF_TIMEOUT_BASE_MAX);
> +
> +	return 0;
>  }
>  
>  int cxl_gpf_port_setup(struct cxl_dport *dport)
> @@ -864,16 +870,22 @@ int cxl_gpf_port_setup(struct cxl_dport *dport)
>  
>  	if (!dport->gpf_dvsec) {
>  		struct pci_dev *pdev;
> -		int dvsec;
> +		int dvsec, rc;
>  
>  		dvsec = cxl_gpf_get_dvsec(dport->dport_dev);
>  		if (!dvsec)
>  			return -EINVAL;
>  
> -		dport->gpf_dvsec = dvsec;
>  		pdev = to_pci_dev(dport->dport_dev);
> -		update_gpf_port_dvsec(pdev, dport->gpf_dvsec, 1);
> -		update_gpf_port_dvsec(pdev, dport->gpf_dvsec, 2);
> +		rc = update_gpf_port_dvsec(pdev, dvsec, 1);
> +		if (rc)
> +			return rc;
> +
> +		rc = update_gpf_port_dvsec(pdev, dvsec, 2);
> +		if (rc)
> +			return rc;
> +
> +		dport->gpf_dvsec = dvsec;
>  	}
>  
>  	return 0;