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From: Dave Jiang <dave.jiang@intel.com>
To: Guixin Liu <kanie@linux.alibaba.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Jonathan Cameron <jic23@kernel.org>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Dan Williams <djbw@kernel.org>, Ira Weiny <iweiny@kernel.org>,
	Li Ming <ming.li@zohomail.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH 1/3] cxl/pci: Use the Device GPF DVSEC for restricted endpoints
Date: Mon, 28 Sep 2026 16:45:35 -0700	[thread overview]
Message-ID: <5f468582-f9cc-4d13-951b-a8be833a157a@intel.com> (raw)
In-Reply-To: <20260922100026.3742401-2-kanie@linux.alibaba.com>



On 9/22/26 3:00 AM, Guixin Liu wrote:
> cxl_gpf_get_dvsec() picks between the Port and the Device GPF DVSEC
> from the PCIe type of the given device, and only a plain endpoint
> counts as a device. A restricted CXL device is an endpoint too, but
> it falls into the port case and is probed for the Port GPF DVSEC
> instead of the Device GPF DVSEC.
> 
> On an RCD, dirty shutdown tracking therefore never arms: the DVSEC
> lookup in cxl_nvdimm_arm_dirty_shutdown_tracking() fails, the dirty
> shutdown count stays invalid, and the warning complains about a
> missing Port GPF DVSEC on a device.
> 
> Treat restricted endpoints as devices.
> 
> Fixes: 36aace15d9bd ("cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()")
> Cc: stable@vger.kernel.org
> Assisted-by: LLM
> Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> ---
>  drivers/cxl/core/pci.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 9d807c1a002c..e31aad7a525a 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -804,7 +804,8 @@ u16 cxl_gpf_get_dvsec(struct device *dev)
>  		return 0;
>  
>  	pdev = to_pci_dev(dev);
> -	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ENDPOINT)
> +	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ENDPOINT ||
> +	    is_cxl_restricted(pdev))
>  		is_port = false;
>  
>  	dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,


  parent reply	other threads:[~2026-09-28 23:45 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 10:00 [PATCH 0/3] cxl/pci: Fix the GPF DVSEC setup path Guixin Liu
2026-09-22 10:00 ` [PATCH 1/3] cxl/pci: Use the Device GPF DVSEC for restricted endpoints Guixin Liu
2026-09-25 23:36   ` Jonathan Cameron
2026-09-28 23:45   ` Dave Jiang [this message]
2026-09-22 10:00 ` [PATCH 2/3] cxl/pci: Program the Port GPF timeouts before caching the DVSEC Guixin Liu
2026-09-25 23:43   ` Jonathan Cameron
2026-09-28 23:46   ` Dave Jiang
2026-09-22 10:00 ` [PATCH 3/3] cxl/pci: Update only the Port GPF timeout fields Guixin Liu
2026-09-25 23:44   ` Jonathan Cameron
2026-10-08  3:15     ` Guixin Liu

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