[PATCH 0/2] perf riscv: Implement rdtsc()

[Chen Pei <cp0613@linux.alibaba.com>]

tools/perf falls back to the __weak rdtsc() stub in tools/perf/util/tsc.c
on every architecture that does not override it, riscv included.  The
stub returns a constant 0, so anything that reaches for the counter gets
a value that means nothing and cannot tell it apart from a counter that
happens to be at 0.

The time CSR is a natural TSC equivalent on riscv: readable from user
mode, constant frequency, and the same counter that riscv's
arch_perf_update_userpage() feeds the user page conversion fields from,
ever since commit 83c5e13b8cbb ("riscv: Prepare for user-space perf
event mmap support").  This series registers that on the tools side.

The two patches are split so that the first stands on its own:

1. Implement rdtsc() over the time CSR for riscv.

2. Replace the compile-time TSC support check with a weak
   arch__rdtsc_supported() hook, so that support is declared next to
   the rdtsc() it describes rather than in the central list of compiler
   macros.

What this is worth beyond the subtest result:

1. The subtest is the only reader of those conversion fields riscv
   can run, so it guards arithmetic that has shipped unexercised;
   registering the counter at the same time leaves a future riscv
   auxtrace driver the reading and the conversion already in place.

2. The hook gives a caller something to ask the architecture before
   it uses the counter value, instead of each caller keeping its own
   copy of the macro list.

Tests:
======
- The "Convert perf time to TSC" test in a riscv64 QEMU virt guest
  with sscofpmf: the subtest skips before the series, passes after it.
- With the riscv implementation left out of the build, so that the
  weak defaults are in effect, the subtest still skips: the behaviour
  of an architecture without a counter is unchanged.

Chen Pei (2):
  perf riscv: Implement rdtsc()
  perf tsc: Replace the compile-time TSC support check with a weak hook

 tools/perf/arch/arm64/util/tsc.c    |  5 +++++
 tools/perf/arch/riscv/util/Build    |  1 +
 tools/perf/arch/riscv/util/tsc.c    | 24 ++++++++++++++++++++++++
 tools/perf/arch/x86/util/tsc.c      |  5 +++++
 tools/perf/tests/perf-time-to-tsc.c | 12 +-----------
 tools/perf/util/tsc.c               |  9 +++++++++
 tools/perf/util/tsc.h               |  1 +
 7 files changed, 46 insertions(+), 11 deletions(-)
 create mode 100644 tools/perf/arch/riscv/util/tsc.c

-- 
2.50.1