* [PATCH v10 0/2] Add LPASS VA CSR HeartBeat pulse clock support
@ 2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
0 siblings, 0 replies; 10+ messages in thread
From: Sarath Ganapathiraju via B4 Relay @ 2026-09-30 9:51 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, srinivas.kandagatla, sarath.ganapathiraju
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla
The LPASS VA CSR block contains rate generator hardware that produces
a HeartBeat Pulse (also known as RateGen Pulse). This pulse
synchronizes the start of the DMAs and Codec Interfaces for the audio
usecases and can serve as a periodic wakeup source for the DSP.
This series adds the DT binding and driver support to model this
rate generator as a clock provider.
Patch 1 adds the YAML binding for the new qcom,hawi-lpass-va-csr
clock provider node under Documentation/devicetree/bindings/clock/.
Patch 2 adds the lpass-va-csr driver under drivers/clk/qcom that
registers the lpass_heartbeat_pulse clock and enables/disables the
rate generator via regmap when the clock consumer requests it.
Changes in v10:
- Rebase the series on linux-next next-20260929.
- Add clk_is_enabled_regmap() to report the heartbeat gate state for
clk_disable_unused() (Sashiko).
- Add Rob's Reviewed-by tag to the binding patch.
- Link to v9: https://patch.msgid.link/20260928-master-v9-0-2277f09f9a09@oss.qualcomm.com
Changes in v9:
- Rebase the series on linux-next next-20260928.
- Add runtime PM callbacks so the LPASS LPR and audio vote clocks are
enabled by pm_runtime_resume_and_get() before touching VA CSR
registers.
- Keep the LPASS vote clocks enabled across heartbeat clock
enable/disable register accesses by taking a runtime PM reference from
the heartbeat clock prepare path.
- Use synchronous runtime PM put on probe success and error paths.
- Drop the one-use runtime PM error label while keeping synchronous puts (Konrad).
- Wrap the runtime PM ops with pm_ptr() from HTML review.
- Link to v8: https://patch.msgid.link/20260917-master-v8-0-823d2c5d090a@oss.qualcomm.com
Changes in v8:
- Rebase the series on linux-next next-20260916.
- Require the LPASS LPR and audio vote clocks to access VA CSR
register space safely.
- Attach the DT vote clocks to runtime PM and resume the device before
programming the rate generator registers.
- Program the counter and delay registers once during probe.
- Use qcom's simple regmap gate ops for the enable bit (Srinivas).
- Drop the unreachable of_device_get_match_data() NULL check (Srinivas).
- Drop stale Reviewed-by/Tested-by tags after the binding and driver
changes.
- Link to v7: https://patch.msgid.link/20260831-heartbeat-v7-next-20260828-v7-0-e3ffeac46a51@oss.qualcomm.com
Changes in v7:
- Rebase the series on linux-next next-20260828.
- Add Prasad's Reviewed-by and Tested-by tags to patch 2.
- Link to v6: https://patch.msgid.link/20260821-heartbeat-v6-next-20260821-send-v6-0-62c5df84ce21@oss.qualcomm.com
Changes in v6:
- Rebase the series on linux-next next-20260821.
- Capitalize Hawi in binding text (Bjorn).
- Simplify the binding example by removing the soc wrapper and
two-cell address/size setup (Bjorn).
- Keep the full VA CSR register window in the binding and describe it
as the VA CSR register block after Konrad clarified the earlier
register-range concern (Bjorn, Konrad).
- Link to v5: https://patch.msgid.link/20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com
Changes in v5:
- Add explicit ARM64 Kconfig gating and Qualcomm default-module policy
for QCOM_CLK_LPASS_HEARTBEAT_PULSE to align with nearby qcom clock
entries.
- Link to v4: https://patch.msgid.link/20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com
Changes in v4:
- Rename the binding filename and schema ID to hawi-specific naming:
qcom,lpass-va-csr.yaml -> qcom,hawi-lpass-va-csr.yaml (Krzysztof).
- Rename Kconfig symbol QCOM_CLK_LPASS_VA_CSR to
QCOM_CLK_LPASS_HEARTBEAT_PULSE (Konrad).
- Add devm_pm_runtime_enable() in the lpass-va-csr probe path.
- Drop the qcom,lpass-va-macro binding extension patch; it will be
resubmitted with the Hawi DTSI changes.
- Drop sound/soc/codecs/Kconfig select wiring to keep this series
clock-only (Konrad).
- Link to v3: https://lore.kernel.org/all/20260723-master-v3-0-3d67b79b0515@oss.qualcomm.com/
Changes in v3:
- Move the qcom,lpass-va-csr binding under
Documentation/devicetree/bindings/clock/ (Krzysztof).
- Move the driver under drivers/clk/qcom/ (Krzysztof).
- Improve the schema description and use generic clock-controller node
naming (Krzysztof).
- Use additionalProperties: false and keep compatibles sorted.
Changes in v2:
- Split the qcom,lpass-va-csr and qcom,lpass-va-macro bindings into
separate patches.
Changes in v1:
- Initial version
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
Sarath Ganapathiraju (2):
dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
clk: qcom: Add LPASS VA CSR heartbeat pulse clock
.../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 62 ++++++++
drivers/clk/qcom/Kconfig | 14 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpass-va-csr.c | 175 +++++++++++++++++++++
4 files changed, 252 insertions(+)
---
base-commit: 6474fa070f2b8013b4b87350b775b8c3be6e8aac
change-id: 20260917-master-6c2778f57a9a
Best regards,
--
Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v10 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
@ 2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
-1 siblings, 0 replies; 10+ messages in thread
From: Sarath Ganapathiraju @ 2026-09-30 9:51 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, srinivas.kandagatla, sarath.ganapathiraju
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla
Add a binding for the Qualcomm LPASS VA CSR rate generator node that
exposes the lpass_heartbeat_pulse clock on Hawi.
The HeartBeat Pulse, also known as RateGen Pulse, synchronizes the
start of DMAs and Codec Interfaces for the audio usecase and can serve
as a periodic wakeup source for the DSP.
Require the LPASS LPR and audio vote clocks to access VA CSR register
space safely.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
.../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 62 ++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
new file mode 100644
index 000000000000..601da83add2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS VA CSR heartbeat pulse clock provider
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
+ - Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
+
+description:
+ The Hawi LPASS (Low Power Audio Subsystem) VA CSR block contains a
+ rate generator that produces a periodic HeartBeat Pulse, also known
+ as the RateGen Pulse. This pulse synchronizes the start of DMAs and
+ Codec Interfaces for audio usecases and can serve as a periodic wakeup
+ source for the DSP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,hawi-lpass-va-csr
+
+ reg:
+ maxItems: 1
+ description: Address and size of the VA CSR register block.
+
+ clocks:
+ items:
+ - description: LPASS LPR (Low Power Resource) voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: lpr
+ - const: audio
+
+ "#clock-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+
+ clock-controller@7ee0000 {
+ compatible = "qcom,hawi-lpass-va-csr";
+ reg = <0x07ee0000 0xe000>;
+ clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "lpr", "audio";
+ #clock-cells = <0>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v10 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
@ 2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
0 siblings, 0 replies; 10+ messages in thread
From: Sarath Ganapathiraju via B4 Relay @ 2026-09-30 9:51 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, srinivas.kandagatla, sarath.ganapathiraju
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla
From: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
Add a binding for the Qualcomm LPASS VA CSR rate generator node that
exposes the lpass_heartbeat_pulse clock on Hawi.
The HeartBeat Pulse, also known as RateGen Pulse, synchronizes the
start of DMAs and Codec Interfaces for the audio usecase and can serve
as a periodic wakeup source for the DSP.
Require the LPASS LPR and audio vote clocks to access VA CSR register
space safely.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
.../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 62 ++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
new file mode 100644
index 000000000000..601da83add2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS VA CSR heartbeat pulse clock provider
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
+ - Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
+
+description:
+ The Hawi LPASS (Low Power Audio Subsystem) VA CSR block contains a
+ rate generator that produces a periodic HeartBeat Pulse, also known
+ as the RateGen Pulse. This pulse synchronizes the start of DMAs and
+ Codec Interfaces for audio usecases and can serve as a periodic wakeup
+ source for the DSP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,hawi-lpass-va-csr
+
+ reg:
+ maxItems: 1
+ description: Address and size of the VA CSR register block.
+
+ clocks:
+ items:
+ - description: LPASS LPR (Low Power Resource) voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: lpr
+ - const: audio
+
+ "#clock-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+
+ clock-controller@7ee0000 {
+ compatible = "qcom,hawi-lpass-va-csr";
+ reg = <0x07ee0000 0xe000>;
+ clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "lpr", "audio";
+ #clock-cells = <0>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v10 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock
2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
@ 2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
-1 siblings, 0 replies; 10+ messages in thread
From: Sarath Ganapathiraju @ 2026-09-30 9:51 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, srinivas.kandagatla, sarath.ganapathiraju
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla
The HeartBeat Pulse, also known as RateGen Pulse, synchronizes the
start of DMAs and Codec Interfaces for the audio usecases and can
serve as a periodic wakeup source for the DSP.
Add the LPASS VA CSR driver that models the rate generator as a clock
provider so consumers can enable and disable it through the common
clock framework.
Attach the DT vote clocks to runtime PM and resume the device before
programming the rate generator registers in probe. Also take a runtime
PM reference from the clock prepare path so later enable and disable
register accesses happen only while the LPASS votes are active.
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 14 ++++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpass-va-csr.c | 175 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 190 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 27d0ab24d50a..da2e8005d075 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -2137,6 +2137,20 @@ config CLK_GFM_LPASS_SM8250
Support for the Glitch Free Mux (GFM) Low power audio
subsystem (LPASS) clocks found on SM8250 SoCs.
+config QCOM_CLK_LPASS_HEARTBEAT_PULSE
+ tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider"
+ depends on COMMON_CLK
+ depends on ARM64 || COMPILE_TEST
+ select REGMAP_MMIO
+ default m if ARCH_QCOM
+ help
+ Qualcomm LPASS VA CSR block contains the rate generator hardware
+ that produces the HeartBeat Pulse (also known as RateGen Pulse).
+ This driver models the rate generator as a clock provider so
+ that consumers can enable or disable it via the common clock
+ framework, and it can be used to synchronize the start of DMAs
+ and Codec Interfaces or as a periodic wakeup source for the DSP.
+
config SM_VIDEOCC_8450
tristate "SM8450 Video Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6affb5073f26..787a3761af3b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o
obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
+obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) += lpass-va-csr.o
obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o
diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c
new file mode 100644
index 000000000000..b4c0f88187eb
--- /dev/null
+++ b/drivers/clk/qcom/lpass-va-csr.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_clk.h>
+#include <linux/pm_clock.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap.h"
+
+#define LPASS_RATE_GEN_CTRL 0xd000
+#define LPASS_RATE_GEN_COUNTER_0 0xd004
+#define LPASS_RATE_GEN_DELAY 0xd010
+
+#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY
+
+#define LPASS_RG_CTRL_EN BIT(0)
+
+struct lpass_va_csr_data {
+ u32 counter_0;
+ u32 delay;
+};
+
+static const struct lpass_va_csr_data hawi_csr_data = {
+ .counter_0 = 0x960,
+ .delay = 0x16,
+};
+
+static const struct regmap_config lpass_rate_gen_regmap_config = {
+ .name = "lpass_rate_gen",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = LPASS_RATE_GEN_MAX_REG,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+struct lpass_va_csr {
+ struct device *dev;
+ struct clk_regmap hb;
+};
+
+#define to_lpass_va_csr(_hw) \
+ container_of(to_clk_regmap(_hw), struct lpass_va_csr, hb)
+
+static int lpass_va_csr_hb_prepare(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+
+ return pm_runtime_resume_and_get(csr->dev);
+}
+
+static void lpass_va_csr_hb_unprepare(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+
+ pm_runtime_put_sync(csr->dev);
+}
+
+static const struct clk_ops lpass_va_csr_hb_ops = {
+ .prepare = lpass_va_csr_hb_prepare,
+ .unprepare = lpass_va_csr_hb_unprepare,
+ .enable = clk_enable_regmap,
+ .disable = clk_disable_regmap,
+ .is_enabled = clk_is_enabled_regmap,
+};
+
+static int lpass_va_csr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct lpass_va_csr_data *data = of_device_get_match_data(dev);
+ struct lpass_va_csr *csr;
+ struct clk_init_data init = {
+ .name = "lpass_heartbeat_pulse",
+ .ops = &lpass_va_csr_hb_ops,
+ };
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ csr = devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL);
+ if (!csr)
+ return -ENOMEM;
+
+ csr->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base,
+ &lpass_rate_gen_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "failed to init regmap\n");
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable PM runtime\n");
+
+ ret = devm_pm_clk_create(dev);
+ if (ret)
+ return ret;
+
+ ret = of_pm_clk_add_clks(dev);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to get vote clocks\n");
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(regmap, LPASS_RATE_GEN_COUNTER_0, data->counter_0);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ ret = regmap_write(regmap, LPASS_RATE_GEN_DELAY, data->delay);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ csr->hb.regmap = regmap;
+ csr->hb.enable_reg = LPASS_RATE_GEN_CTRL;
+ csr->hb.enable_mask = LPASS_RG_CTRL_EN;
+ csr->hb.hw.init = &init;
+
+ ret = devm_clk_register_regmap(dev, &csr->hb);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb.hw);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static const struct of_device_id lpass_va_csr_dt_match[] = {
+ { .compatible = "qcom,hawi-lpass-va-csr", .data = &hawi_csr_data },
+ {}
+};
+MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match);
+
+static const struct dev_pm_ops lpass_va_csr_pm_ops = {
+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
+};
+
+static struct platform_driver lpass_va_csr_driver = {
+ .driver = {
+ .name = "qcom-lpass-va-csr",
+ .of_match_table = lpass_va_csr_dt_match,
+ .pm = pm_ptr(&lpass_va_csr_pm_ops),
+ },
+ .probe = lpass_va_csr_probe,
+};
+
+module_platform_driver(lpass_va_csr_driver);
+
+MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v10 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock
@ 2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
0 siblings, 0 replies; 10+ messages in thread
From: Sarath Ganapathiraju via B4 Relay @ 2026-09-30 9:51 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, srinivas.kandagatla, sarath.ganapathiraju
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla
From: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
The HeartBeat Pulse, also known as RateGen Pulse, synchronizes the
start of DMAs and Codec Interfaces for the audio usecases and can
serve as a periodic wakeup source for the DSP.
Add the LPASS VA CSR driver that models the rate generator as a clock
provider so consumers can enable and disable it through the common
clock framework.
Attach the DT vote clocks to runtime PM and resume the device before
programming the rate generator registers in probe. Also take a runtime
PM reference from the clock prepare path so later enable and disable
register accesses happen only while the LPASS votes are active.
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 14 ++++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpass-va-csr.c | 175 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 190 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 27d0ab24d50a..da2e8005d075 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -2137,6 +2137,20 @@ config CLK_GFM_LPASS_SM8250
Support for the Glitch Free Mux (GFM) Low power audio
subsystem (LPASS) clocks found on SM8250 SoCs.
+config QCOM_CLK_LPASS_HEARTBEAT_PULSE
+ tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider"
+ depends on COMMON_CLK
+ depends on ARM64 || COMPILE_TEST
+ select REGMAP_MMIO
+ default m if ARCH_QCOM
+ help
+ Qualcomm LPASS VA CSR block contains the rate generator hardware
+ that produces the HeartBeat Pulse (also known as RateGen Pulse).
+ This driver models the rate generator as a clock provider so
+ that consumers can enable or disable it via the common clock
+ framework, and it can be used to synchronize the start of DMAs
+ and Codec Interfaces or as a periodic wakeup source for the DSP.
+
config SM_VIDEOCC_8450
tristate "SM8450 Video Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6affb5073f26..787a3761af3b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o
obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
+obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) += lpass-va-csr.o
obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o
diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c
new file mode 100644
index 000000000000..b4c0f88187eb
--- /dev/null
+++ b/drivers/clk/qcom/lpass-va-csr.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_clk.h>
+#include <linux/pm_clock.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap.h"
+
+#define LPASS_RATE_GEN_CTRL 0xd000
+#define LPASS_RATE_GEN_COUNTER_0 0xd004
+#define LPASS_RATE_GEN_DELAY 0xd010
+
+#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY
+
+#define LPASS_RG_CTRL_EN BIT(0)
+
+struct lpass_va_csr_data {
+ u32 counter_0;
+ u32 delay;
+};
+
+static const struct lpass_va_csr_data hawi_csr_data = {
+ .counter_0 = 0x960,
+ .delay = 0x16,
+};
+
+static const struct regmap_config lpass_rate_gen_regmap_config = {
+ .name = "lpass_rate_gen",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = LPASS_RATE_GEN_MAX_REG,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+struct lpass_va_csr {
+ struct device *dev;
+ struct clk_regmap hb;
+};
+
+#define to_lpass_va_csr(_hw) \
+ container_of(to_clk_regmap(_hw), struct lpass_va_csr, hb)
+
+static int lpass_va_csr_hb_prepare(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+
+ return pm_runtime_resume_and_get(csr->dev);
+}
+
+static void lpass_va_csr_hb_unprepare(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+
+ pm_runtime_put_sync(csr->dev);
+}
+
+static const struct clk_ops lpass_va_csr_hb_ops = {
+ .prepare = lpass_va_csr_hb_prepare,
+ .unprepare = lpass_va_csr_hb_unprepare,
+ .enable = clk_enable_regmap,
+ .disable = clk_disable_regmap,
+ .is_enabled = clk_is_enabled_regmap,
+};
+
+static int lpass_va_csr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct lpass_va_csr_data *data = of_device_get_match_data(dev);
+ struct lpass_va_csr *csr;
+ struct clk_init_data init = {
+ .name = "lpass_heartbeat_pulse",
+ .ops = &lpass_va_csr_hb_ops,
+ };
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ csr = devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL);
+ if (!csr)
+ return -ENOMEM;
+
+ csr->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base,
+ &lpass_rate_gen_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "failed to init regmap\n");
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable PM runtime\n");
+
+ ret = devm_pm_clk_create(dev);
+ if (ret)
+ return ret;
+
+ ret = of_pm_clk_add_clks(dev);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to get vote clocks\n");
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(regmap, LPASS_RATE_GEN_COUNTER_0, data->counter_0);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ ret = regmap_write(regmap, LPASS_RATE_GEN_DELAY, data->delay);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ csr->hb.regmap = regmap;
+ csr->hb.enable_reg = LPASS_RATE_GEN_CTRL;
+ csr->hb.enable_mask = LPASS_RG_CTRL_EN;
+ csr->hb.hw.init = &init;
+
+ ret = devm_clk_register_regmap(dev, &csr->hb);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb.hw);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static const struct of_device_id lpass_va_csr_dt_match[] = {
+ { .compatible = "qcom,hawi-lpass-va-csr", .data = &hawi_csr_data },
+ {}
+};
+MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match);
+
+static const struct dev_pm_ops lpass_va_csr_pm_ops = {
+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
+};
+
+static struct platform_driver lpass_va_csr_driver = {
+ .driver = {
+ .name = "qcom-lpass-va-csr",
+ .of_match_table = lpass_va_csr_dt_match,
+ .pm = pm_ptr(&lpass_va_csr_pm_ops),
+ },
+ .probe = lpass_va_csr_probe,
+};
+
+module_platform_driver(lpass_va_csr_driver);
+
+MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v10 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock
2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
(?)
@ 2026-09-30 10:06 ` sashiko-bot
-1 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-09-30 10:06 UTC (permalink / raw)
To: Sarath Ganapathiraju; +Cc: conor+dt, robh, devicetree, linux-clk
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] clk: qcom: missing hardware state restoration on runtime resume
- [Medium] clk: qcom: missing NULL check for of_device_get_match_data()
--
commit 506d9b3aab397203423c9181e755579f9ddb3dd7
Author: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
clk: qcom: Add LPASS VA CSR heartbeat pulse clock
This commit adds the LPASS VA CSR driver to model the rate generator as a
clock provider. It attaches DT vote clocks to runtime PM and programs the
rate generator registers during probe.
> diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c
> new file mode 100644
> index 0000000000000..b4c0f88187ebb
> --- /dev/null
> +++ b/drivers/clk/qcom/lpass-va-csr.c
[ ... ]
> +static int lpass_va_csr_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + const struct lpass_va_csr_data *data = of_device_get_match_data(dev);
[ ... ]
> + ret = pm_runtime_resume_and_get(dev);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(regmap, LPASS_RATE_GEN_COUNTER_0, data->counter_0);
[Severity: Medium]
Is there a risk of a NULL pointer dereference here?
If the device is bound manually via sysfs rather than instantiated through
Device Tree, of_device_get_match_data() will return NULL. The data pointer
is then unconditionally dereferenced when writing to LPASS_RATE_GEN_COUNTER_0
and LPASS_RATE_GEN_DELAY.
[Severity: High]
Does this hardware configuration get lost during runtime suspend and resume
cycles?
When the clock is unprepared by the consumer, the PM runtime reference is
dropped. The pm_clk_suspend callback disables the vote clocks, which can
allow the LPASS power domain to collapse and erase the register context.
The data written here to LPASS_RATE_GEN_COUNTER_0 and LPASS_RATE_GEN_DELAY
is only configured once during probe.
> + if (ret) {
> + pm_runtime_put_sync(dev);
> + return ret;
> + }
> +
> + ret = regmap_write(regmap, LPASS_RATE_GEN_DELAY, data->delay);
[ ... ]
> +static const struct dev_pm_ops lpass_va_csr_pm_ops = {
> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
> +};
[Severity: High]
Should there be a regcache_sync() call to restore the hardware state?
Because the generic pm_clk_resume is used directly without an additional
wrapper that syncs the regmap cache, the counter and delay registers are
not reprogrammed after waking up from runtime suspend. The subsequent
clk_enable_regmap() will only write the control register, leaving the
hardware with uninitialized or reset parameters which could break audio
DMAs and codec synchronization.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260930-master-v10-0-105207bc5275@oss.qualcomm.com?part=2
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v10 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock
2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
(?)
(?)
@ 2026-10-05 6:06 ` Ajay Kumar Nandam
2026-10-12 9:00 ` Sarath Ganapathiraju
-1 siblings, 1 reply; 10+ messages in thread
From: Ajay Kumar Nandam @ 2026-10-05 6:06 UTC (permalink / raw)
To: Sarath Ganapathiraju
Cc: Ajay Kumar Nandam, andersson, abelvesa, sboyd, bmasney+clk,
jbrunet+clk, robh, krzk+dt, conor+dt, srinivas.kandagatla,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla
> +static int lpass_va_csr_hb_prepare(struct clk_hw *hw)
> +{
> + struct lpass_va_csr *csr = to_lpass_va_csr(hw);
> +
> + return pm_runtime_resume_and_get(csr->dev);
> +}
Since this clock is registered with devm_clk_register_regmap(dev, ...)
after devm_pm_runtime_enable(dev), the clock core should already mark the
provider as runtime-PM managed and take a provider PM reference in
clk_core_prepare() before calling the clock's .prepare callback. It also
drops that reference after .unprepare.
So this explicit pm_runtime_resume_and_get()/pm_runtime_put_sync() pair
looks like it double-counts the same provider device rather than adding new
protection for the regmap gate ops. Is the extra reference intentional here?
If not, the custom prepare/unprepare callbacks could probably be dropped and
the driver could rely on the clock core's provider runtime-PM handling.
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v10 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock
2026-10-05 6:06 ` Ajay Kumar Nandam
@ 2026-10-12 9:00 ` Sarath Ganapathiraju
0 siblings, 0 replies; 10+ messages in thread
From: Sarath Ganapathiraju @ 2026-10-12 9:00 UTC (permalink / raw)
To: Ajay Kumar Nandam
Cc: Bjorn Andersson, Abel Vesa, Stephen Boyd, Brian Masney,
Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, linux-arm-msm, linux-clk, devicetree,
linux-kernel, prasad.kumpatla
On Mon, Oct 05, 2026 at 11:36:30AM +0530, Ajay Kumar Nandam wrote:
> Since this clock is registered with devm_clk_register_regmap(dev, ...)
> after devm_pm_runtime_enable(dev), the clock core should already mark the
> provider as runtime-PM managed and take a provider PM reference in
> clk_core_prepare() before calling the clock's .prepare callback. It also
> drops that reference after .unprepare.
>
> So this explicit pm_runtime_resume_and_get()/pm_runtime_put_sync() pair
> looks like it double-counts the same provider device rather than adding new
> protection for the regmap gate ops. Is the extra reference intentional here?
> If not, the custom prepare/unprepare callbacks could probably be dropped and
> the driver could rely on the clock core's provider runtime-PM handling.
Thanks, this extra reference was not intentional.
I will drop the custom prepare/unprepare callbacks in the next revision
and rely on the clock core provider runtime PM handling around the regmap
gate operations.
Thanks,
Sarath
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v10 0/2] Add LPASS VA CSR HeartBeat pulse clock support
2026-09-30 9:51 ` Sarath Ganapathiraju via B4 Relay
` (2 preceding siblings ...)
(?)
@ 2026-09-30 17:05 ` Prasad Kumpatla
-1 siblings, 0 replies; 10+ messages in thread
From: Prasad Kumpatla @ 2026-09-30 17:05 UTC (permalink / raw)
To: sarath.ganapathiraju, andersson, abelvesa, sboyd, bmasney+clk,
jbrunet+clk, robh, krzk+dt, conor+dt, srinivas.kandagatla
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel
On 9/30/2026 3:21 PM, Sarath Ganapathiraju via B4 Relay wrote:
> The LPASS VA CSR block contains rate generator hardware that produces
> a HeartBeat Pulse (also known as RateGen Pulse). This pulse
> synchronizes the start of the DMAs and Codec Interfaces for the audio
> usecases and can serve as a periodic wakeup source for the DSP.
>
> This series adds the DT binding and driver support to model this
> rate generator as a clock provider.
>
> Patch 1 adds the YAML binding for the new qcom,hawi-lpass-va-csr
> clock provider node under Documentation/devicetree/bindings/clock/.
>
> Patch 2 adds the lpass-va-csr driver under drivers/clk/qcom that
> registers the lpass_heartbeat_pulse clock and enables/disables the
> rate generator via regmap when the clock consumer requests it.
Tested on Hawi - WCD Headset Playback and Record working fine.
Reviewed-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Tested-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 10+ messages in thread