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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org,
	Srirangan Madhavan <smadhavan@nvidia.com>
Subject: [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges
Date: Thu,  1 Oct 2026 09:22:19 +0000	[thread overview]
Message-ID: <20261001092227.3004747-9-smadhavan@nvidia.com> (raw)
In-Reply-To: <20261001092227.3004747-1-smadhavan@nvidia.com>

An HDM decoder with a nonzero size can report a base and size whose end
address wraps the 64-bit address space. Reject that programming before
publishing the decoder range, so enumeration and later reset handling
cannot use the wrapped range.

Use check_add_overflow() for nonzero ranges. Preserve the existing
empty-range representation for zero-size decoders.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
 drivers/cxl/core/resource.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
index 8dfeb12de8c9..8d2fbc49a06f 100644
--- a/drivers/cxl/core/resource.c
+++ b/drivers/cxl/core/resource.c
@@ -115,16 +115,21 @@ int cxl_hdm_unpack_decoder(struct cxl_decoder_settings *settings, int id,
 	int interleave_ways;
 	unsigned long flags = 0;
 	struct range hpa_range;
+	u64 end;
 	int rc;
 
 	if (!committed)
 		size = 0;
 	if (base == U64_MAX || size == U64_MAX)
 		return -ENXIO;
+	if (size && check_add_overflow(base, size - 1, &end))
+		return -ENXIO;
+	if (!size)
+		end = base - 1;
 
 	hpa_range = (struct range) {
 		.start = base,
-		.end = base + size - 1,
+		.end = end,
 	};
 
 	if (committed) {
-- 
2.43.0


  parent reply	other threads:[~2026-10-01  9:23 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01  9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-01  9:25   ` sashiko-bot
2026-10-02  9:33   ` Richard Cheng
2026-10-07 12:07   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-01  9:30   ` sashiko-bot
2026-10-02  9:48   ` Richard Cheng
2026-10-07 12:22   ` Li Ming
2026-10-11  2:54     ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-01  9:30   ` sashiko-bot
2026-10-02  9:49   ` Richard Cheng
2026-10-07 12:29   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-01  9:49   ` sashiko-bot
2026-10-02 10:17   ` Richard Cheng
2026-10-11  2:38     ` Srirangan Madhavan
2026-10-02 19:07   ` Dave Jiang
2026-10-07 12:34   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-01  9:31   ` sashiko-bot
2026-10-02 19:59   ` Dave Jiang
2026-10-07 13:12     ` Li Ming
2026-10-07 16:23       ` Dave Jiang
2026-10-08 13:18         ` Li Ming
2026-10-08 15:19           ` Dave Jiang
2026-10-09 14:41             ` Li Ming
2026-10-11  2:48             ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-01  9:31   ` sashiko-bot
2026-10-05 21:42   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-01 10:02   ` sashiko-bot
2026-10-02 21:46   ` Dave Jiang
2026-10-01  9:22 ` Srirangan Madhavan [this message]
2026-10-01  9:35   ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges sashiko-bot
2026-10-02 21:50   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-01  9:37   ` sashiko-bot
2026-10-02 23:57   ` Dave Jiang
2026-10-11  2:52     ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-01 10:12   ` sashiko-bot
2026-10-06 15:39   ` Dave Jiang
2026-10-07 19:37     ` Alison Schofield
2026-10-11  2:45       ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01 10:18   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-01 10:23   ` sashiko-bot
2026-10-02  8:06   ` Richard Cheng
2026-10-11  2:35     ` Srirangan Madhavan
2026-10-07 19:44   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-01 10:31   ` sashiko-bot
2026-10-08 23:33   ` Bjorn Helgaas
2026-10-01  9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-01 10:49   ` sashiko-bot
2026-10-07 19:49   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-01 11:02   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-01 11:12   ` sashiko-bot
2026-10-08 23:35   ` Bjorn Helgaas

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