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From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v14 14/16] cxl: Restore CXL state after PCI reset
Date: Thu, 01 Oct 2026 10:49:03 +0000	[thread overview]
Message-ID: <20261001104903.8ED5A1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20261001092227.3004747-15-smadhavan@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] cxl: PCI config space corruption if state not saved before reset
--

commit ac710a7fdaa9ca778d4721319e9ec092a2bb0d6c
Author: Srirangan Madhavan <smadhavan@nvidia.com>

cxl: Restore CXL state after PCI reset

This commit restores the PCI configuration needed for HDM access, followed by
cached HDM decoder and CXL Device DVSEC state after a PCI reset. It stops at
the first restoration failure and preserves a disabled PCI command snapshot.

> diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
> index 679a605da24c4..0acc471d0d7e2 100644
> --- a/drivers/cxl/core/resource.c
> +++ b/drivers/cxl/core/resource.c

[ ... ]

> +static void cxl_restore_pci_state_for_hdm_restore(struct pci_dev *pdev,
> +						  u16 *command)
> +{
> +	u32 saved_config = pdev->saved_config_space[PCI_COMMAND / 4];
> +	u32 restore_config;
> +
> +	device_lock_assert(&pdev->dev);
> +	*command = saved_config & 0xffff;
> +
> +	/*
> +	 * pci_restore_state() is the available interface for restoring BARs and
> +	 * related PCI state needed to reach HDM MMIO. Temporarily alter its saved
> +	 * command value so that it enables MSE but cannot enable BME or INTx
> +	 * before CXL state restoration completes. Preserve the original saved
> +	 * value for the outer PCI reset path.
> +	 */
> +	restore_config = saved_config | PCI_COMMAND_MEMORY |
> +			 PCI_COMMAND_INTX_DISABLE;
> +	restore_config &= ~PCI_COMMAND_MASTER;
> +
> +	pdev->saved_config_space[PCI_COMMAND / 4] = restore_config;
> +	pci_restore_state(pdev);

[Severity: High]
Does this code corrupt the PCI configuration space if the state was not saved
before the reset?

cxl_restore_pci_state_for_hdm_restore() unconditionally calls
pci_restore_state() without verifying that pdev->state_saved is true.
pci_restore_state() writes the contents of pdev->saved_config_space back to
the hardware's PCI configuration registers. If the caller did not successfully
call pci_save_state() prior to the reset, this array contains uninitialized
zeroes (or stale data from a prior suspend cycle).

Writing this invalid state wipes the device's BARs and configuration,
permanently breaking access to the CXL device.

> +	pdev->saved_config_space[PCI_COMMAND / 4] = saved_config;
> +}

[ ... ]

> +static void cxl_reset_save_disabled_state(struct pci_dev *pdev)
> +{
> +	u32 *saved_command = &pdev->saved_config_space[PCI_COMMAND / 4];
> +	int rc;
> +
> +	rc = pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
> +	if (rc)
> +		pci_err(pdev,
> +			"failed to disable device after CXL reset failure: %d\n",
> +			pcibios_err_to_errno(rc));
> +
> +	/* Preserve the pre-reset snapshot if PCI state has not been restored. */
> +	if (!pdev->state_saved) {
> +		rc = pci_save_state(pdev);

[Severity: High]
This error path explicitly handles the !pdev->state_saved case, which indicates
that a missing saved state is anticipated during a reset, yet it is
unconditionally restored on the success path.

> +		if (rc)
> +			pci_err(pdev,
> +				"failed to save disabled state after CXL reset failure: %d\n",
> +				rc);
> +	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261001092227.3004747-1-smadhavan@nvidia.com?part=14

  reply	other threads:[~2026-10-01 10:49 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01  9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-01  9:25   ` sashiko-bot
2026-10-02  9:33   ` Richard Cheng
2026-10-07 12:07   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-01  9:30   ` sashiko-bot
2026-10-02  9:48   ` Richard Cheng
2026-10-07 12:22   ` Li Ming
2026-10-11  2:54     ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-01  9:30   ` sashiko-bot
2026-10-02  9:49   ` Richard Cheng
2026-10-07 12:29   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-01  9:49   ` sashiko-bot
2026-10-02 10:17   ` Richard Cheng
2026-10-11  2:38     ` Srirangan Madhavan
2026-10-02 19:07   ` Dave Jiang
2026-10-07 12:34   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-01  9:31   ` sashiko-bot
2026-10-02 19:59   ` Dave Jiang
2026-10-07 13:12     ` Li Ming
2026-10-07 16:23       ` Dave Jiang
2026-10-08 13:18         ` Li Ming
2026-10-08 15:19           ` Dave Jiang
2026-10-09 14:41             ` Li Ming
2026-10-11  2:48             ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-01  9:31   ` sashiko-bot
2026-10-05 21:42   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-01 10:02   ` sashiko-bot
2026-10-02 21:46   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges Srirangan Madhavan
2026-10-01  9:35   ` sashiko-bot
2026-10-02 21:50   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-01  9:37   ` sashiko-bot
2026-10-02 23:57   ` Dave Jiang
2026-10-11  2:52     ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-01 10:12   ` sashiko-bot
2026-10-06 15:39   ` Dave Jiang
2026-10-07 19:37     ` Alison Schofield
2026-10-11  2:45       ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01 10:18   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-01 10:23   ` sashiko-bot
2026-10-02  8:06   ` Richard Cheng
2026-10-11  2:35     ` Srirangan Madhavan
2026-10-07 19:44   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-01 10:31   ` sashiko-bot
2026-10-08 23:33   ` Bjorn Helgaas
2026-10-01  9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-01 10:49   ` sashiko-bot [this message]
2026-10-07 19:49   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-01 11:02   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-01 11:12   ` sashiko-bot
2026-10-08 23:35   ` Bjorn Helgaas

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