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From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
	linux-riscv@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org,
	pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org,
	tglx@kernel.org, kevin.tian@intel.com,
	fangyu.yu@linux.alibaba.com
Subject: Re: [PATCH v6 01/16] iommu/dma: Prepare MSI physical address lists
Date: Sat, 3 Oct 2026 09:10:49 -0300	[thread overview]
Message-ID: <20261003121049.GX1616761@nvidia.com> (raw)
In-Reply-To: <pph73bajtpgp3u5vb7xjqmbrz35zs2lw7fpkhobg5jdzbjw2vq@usg3jbbneskp>

On Sat, Oct 03, 2026 at 02:03:35PM +0200, Andrew Jones wrote:
> 
> Hi Robin,
> 
> On Fri, Oct 02, 2026 at 05:21:18PM +0100, Robin Murphy wrote:
> > You already end up adding what is effectively a RISC-V-specific
> > entrypoint, so you may as well just carry that all the way through to
> > its own effectively RISC-V-specific implementation
> 
> The list API came out of the v4[1] discussion with Jason. Preparing the
> targets as one contiguous IOVA range lets the MSI descriptor cache the
> base and IMSIC compose the address as base + CPU offset. That got
> rid of the separate domain-local lookup table and its lifetime handling,
> which I think was a worthwhile improvement.

Yeah, I prefer this idea to what you had earlier, however it is
accomodated.

> > it should merely be a case of whether a) this is the first call for
> > the given cookie so everything needs mapping, or b) it's not the
> > first call, so everything must already be mapped and we can just
> > return the IOVA.
> 
> For DMA-IOMMU, yes, remembering the base would let us drop the range
> matching. We'd still need the contiguous IOVA allocation, mapping loop,
> rollback on failure, and locking across the whole operation.

I fell like dma-iommu should have a way to map a page list to iova and
maybe that is all the shared code with arm there is.

Jason

WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
	linux-riscv@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org,
	pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org,
	tglx@kernel.org, kevin.tian@intel.com,
	fangyu.yu@linux.alibaba.com
Subject: Re: [PATCH v6 01/16] iommu/dma: Prepare MSI physical address lists
Date: Sat, 3 Oct 2026 09:10:49 -0300	[thread overview]
Message-ID: <20261003121049.GX1616761@nvidia.com> (raw)
In-Reply-To: <pph73bajtpgp3u5vb7xjqmbrz35zs2lw7fpkhobg5jdzbjw2vq@usg3jbbneskp>

On Sat, Oct 03, 2026 at 02:03:35PM +0200, Andrew Jones wrote:
> 
> Hi Robin,
> 
> On Fri, Oct 02, 2026 at 05:21:18PM +0100, Robin Murphy wrote:
> > You already end up adding what is effectively a RISC-V-specific
> > entrypoint, so you may as well just carry that all the way through to
> > its own effectively RISC-V-specific implementation
> 
> The list API came out of the v4[1] discussion with Jason. Preparing the
> targets as one contiguous IOVA range lets the MSI descriptor cache the
> base and IMSIC compose the address as base + CPU offset. That got
> rid of the separate domain-local lookup table and its lifetime handling,
> which I think was a worthwhile improvement.

Yeah, I prefer this idea to what you had earlier, however it is
accomodated.

> > it should merely be a case of whether a) this is the first call for
> > the given cookie so everything needs mapping, or b) it's not the
> > first call, so everything must already be mapped and we can just
> > return the IOVA.
> 
> For DMA-IOMMU, yes, remembering the base would let us drop the range
> matching. We'd still need the contiguous IOVA allocation, mapping loop,
> rollback on failure, and locking across the whole operation.

I fell like dma-iommu should have a way to map a page list to iova and
maybe that is all the shared code with arm there is.

Jason

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  reply	other threads:[~2026-10-03 12:10 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-25 15:16 [PATCH v6 00/16] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Andrew Jones
2026-09-25 15:16 ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 01/16] iommu/dma: Prepare MSI physical address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-10-02 16:21   ` Robin Murphy
2026-10-02 16:21     ` Robin Murphy
2026-10-03 12:03     ` Andrew Jones
2026-10-03 12:03       ` Andrew Jones
2026-10-03 12:10       ` Jason Gunthorpe [this message]
2026-10-03 12:10         ` Jason Gunthorpe
2026-09-25 15:16 ` [PATCH v6 02/16] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 03/16] iommufd: Split software MSI map lookup and allocation Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 04/16] iommufd: Bound software MSI mappings to the reserved range Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 05/16] iommufd: Prepare software MSI maps for address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 06/16] iommufd: Install software MSI map ranges atomically Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 07/16] iommufd: Prepare software MSI installation for address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28 10:23   ` Andrew Jones
2026-09-28 10:23     ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 08/16] iommu/dma: Introduce iommu_dma_prepare_msi_list() Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 09/16] iommu/riscv: Reserve an MSI IOVA window for iommufd Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 10/16] irqchip/riscv-imsic: Add MSI address list Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:51   ` Anup Patel
2026-09-25 15:51     ` Anup Patel
2026-09-28  3:27   ` Nutty.Liu
2026-09-28  3:27     ` Nutty.Liu
2026-09-28 10:20   ` Andrew Jones
2026-09-28 10:20     ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 11/16] irqchip/riscv-imsic: Support IOMMU MSI address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:52   ` Anup Patel
2026-09-25 15:52     ` Anup Patel
2026-09-28  3:18   ` Nutty.Liu
2026-09-28  3:18     ` Nutty.Liu
2026-09-25 15:16 ` [PATCH v6 12/16] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28  3:17   ` Nutty.Liu
2026-09-28  3:17     ` Nutty.Liu
2026-09-25 15:16 ` [PATCH v6 13/16] vfio: enable IOMMU_TYPE1 for RISC-V Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 14/16] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:51   ` Anup Patel
2026-09-25 15:51     ` Anup Patel
2026-09-25 15:16 ` [PATCH v6 15/16] riscv: defconfig: Enable IOMMUFD and VFIO Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28  3:17   ` Nutty.Liu
2026-09-28  3:17     ` Nutty.Liu
2026-09-25 15:16 ` [PATCH v6 16/16] selftests/vfio: Allow building on RISC-V Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28  3:16   ` Nutty.Liu
2026-09-28  3:16     ` Nutty.Liu
2026-09-28 10:24 ` [PATCH v6 00/16] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Andrew Jones
2026-09-28 10:24   ` Andrew Jones

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