From: sashiko-bot@kernel.org
To: "David Zhang" <yidong.zhang@amd.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH V2 09/20] accel/amdxdna: Add context switch hysteresis with debugfs control
Date: Tue, 06 Oct 2026 04:35:24 +0000 [thread overview]
Message-ID: <20261006043524.C1EE91F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20261006042230.547807-10-yidong.zhang@amd.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] amdxdna: unaligned memory access in aie4_set_runtime_cfg()
--
commit 1c7fe2fcd8c5df7169f8d7c14de7898318de0123
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Add context switch hysteresis with debugfs control
This commit adds aie4_set_ctx_hysteresis() to configure the AIE4 context
switch hysteresis timeout. It also exposes a debugfs node to change the
timeout at runtime.
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index 7112b0bc3725a..5720aa88e6d6d 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
[ ... ]
> @@ -262,3 +262,46 @@ int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
>
> return ret;
> }
> +
> +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
> + const void *data, size_t size)
> +{
> + DECLARE_AIE_MSG(aie4_msg_set_runtime_cfg, AIE4_MSG_OP_SET_RUNTIME_CONFIG);
> + u8 buf[sizeof(req.type) + AIE4_RUNTIME_CFG_MAX_DATA_SIZE] = { 0 };
[Severity: Medium]
Could this lead to unaligned memory access? The payload buffer is declared as
a byte array with no alignment guarantees, meaning its start address on the
stack might not be 4-byte aligned.
Later in this function, buf is assigned to msg.send_data and passed to
aie_send_mgmt_msg_wait(). When the mailbox code processes this message, it
does:
drivers/accel/amdxdna/amdxdna_mailbox.c:xdna_mailbox_send_msg() {
...
if (unlikely(((u32 *)msg->send_data)[0] == TOMBSTONE)) {
...
}
Dereferencing a potentially unaligned pointer via a u32 pointer cast is
undefined behavior. While x86_64 hardware typically handles unaligned reads
gracefully, the compiler is permitted to optimize assuming the pointer is
strictly 4-byte aligned, which can lead to miscompilation. Furthermore, this
will trigger Undefined Behavior Sanitizer (UBSAN) warnings during runtime
testing.
Could the buffer be aligned, perhaps by using __aligned(4) or an appropriately
typed struct?
> + int ret;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261006042230.547807-1-yidong.zhang@amd.com?part=9
next prev parent reply other threads:[~2026-10-06 4:35 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-06 4:22 [PATCH V2 00/20] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-06 4:22 ` [PATCH V2 01/20] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-10-06 4:22 ` [PATCH V2 02/20] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-10-06 4:22 ` [PATCH V2 03/20] accel/amdxdna: Add CERT firmware version support David Zhang
2026-10-06 4:22 ` [PATCH V2 04/20] accel/amdxdna: Upgrade firmware version to 6.0 David Zhang
2026-10-06 4:22 ` [PATCH V2 05/20] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-10-06 4:22 ` [PATCH V2 06/20] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-10-06 4:22 ` [PATCH V2 07/20] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-10-06 4:22 ` [PATCH V2 08/20] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
2026-10-06 4:22 ` [PATCH V2 09/20] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
2026-10-06 4:35 ` sashiko-bot [this message]
2026-10-06 4:22 ` [PATCH V2 10/20] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-10-06 4:22 ` [PATCH V2 11/20] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
2026-10-06 4:22 ` [PATCH V2 12/20] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-10-06 4:22 ` [PATCH V2 13/20] accel/amdxdna: Prepare for AIE4 command submission David Zhang
2026-10-06 4:35 ` sashiko-bot
2026-10-06 4:22 ` [PATCH V2 14/20] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-10-06 4:41 ` sashiko-bot
2026-10-06 7:12 ` Eva Crystal
2026-10-07 22:54 ` Zhang, Yidong (David)
2026-10-06 4:22 ` [PATCH V2 15/20] accel/amdxdna: Make hmm_invalidate common for AIE2 and AIE4 David Zhang
2026-10-06 4:22 ` [PATCH V2 16/20] accel/amdxdna: Finalize runtime PM before acquiring dev_lock on removal David Zhang
2026-10-06 7:13 ` Eva Crystal
2026-10-06 17:01 ` Lizhi Hou
2026-10-07 1:18 ` Eva Crystal
2026-10-06 4:22 ` [PATCH V2 17/20] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-10-06 4:22 ` [PATCH V2 18/20] accel/amdxdna: Link SR-IOV VFs for power management sequencing David Zhang
2026-10-06 4:35 ` sashiko-bot
2026-10-06 4:22 ` [PATCH V2 19/20] accel/amdxdna: Implement runtime suspend and resume support David Zhang
2026-10-06 4:43 ` sashiko-bot
2026-10-06 4:22 ` [PATCH V2 20/20] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
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