[PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix

[PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix

[Pufan Jin]

Add vendor prefix for ALINX (Shanghai Xin'yi Electronics Technology
Co., Ltd.).

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969..97e7ef340 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -90,6 +90,8 @@ patternProperties:
     description: AlgolTek, Inc.
   "^alientek,.*":
     description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
+  "^alinx,.*":
+    description: Shanghai Xin'yi Electronics Technology Co., Ltd. (ALINX)
   "^allegro,.*":
     description: Allegro DVT
   "^allegromicro,.*":
-- 
2.55.0

Re: [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix

[Conor Dooley]

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On Tue, Oct 06, 2026 at 01:33:06AM +0800, Pufan Jin wrote:
> Add vendor prefix for ALINX (Shanghai Xin'yi Electronics Technology
> Co., Ltd.).

Where does this ALINX come from? Website url?

> 
> Signed-off-by: Pufan Jin <2254650260@qq.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index ba2002969..97e7ef340 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -90,6 +90,8 @@ patternProperties:
>      description: AlgolTek, Inc.
>    "^alientek,.*":
>      description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
> +  "^alinx,.*":
> +    description: Shanghai Xin'yi Electronics Technology Co., Ltd. (ALINX)
>    "^allegro,.*":
>      description: Allegro DVT
>    "^allegromicro,.*":
> -- 
> 2.55.0
> 

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Re: [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix

[Pufan Jin]

On 2026/10/7 18:35, Conor Dooley wrote:
> On Tue, Oct 06, 2026 at 01:33:06AM +0800, Pufan Jin wrote:
>> Add vendor prefix for ALINX (Shanghai Xin'yi Electronics Technology
>> Co., Ltd.).
> Where does this ALINX come from? Website url?
>
>> Signed-off-by: Pufan Jin <2254650260@qq.com>
>> ---
>>   Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
>> index ba2002969..97e7ef340 100644
>> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
>> @@ -90,6 +90,8 @@ patternProperties:
>>       description: AlgolTek, Inc.
>>     "^alientek,.*":
>>       description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
>> +  "^alinx,.*":
>> +    description: Shanghai Xin'yi Electronics Technology Co., Ltd. (ALINX)
>>     "^allegro,.*":
>>       description: Allegro DVT
>>     "^allegromicro,.*":
>> -- 
>> 2.55.0

Hi Conor,

ALINX is the brand of Xinyi Electronic Technology (Shanghai) Co., Ltd.
(芯驿电子科技（上海）有限公司), https://www.alinx.com/ - an FPGA/SoC
company and official partner of AMD Xilinx, Unisoc and Baidu.

The board is not in the alinx.com shop because ALINX describes EdgeBoard
as a customisation done for Baidu: Baidu owns the EdgeBoard brand and the
sales channel, while ALINX designs and manufactures the hardware. From
ALINX's own product documentation [1]:

"...as a Baidu AI partner, it has customized the Edgeboard series edge
  devices of the domestic AI flying paddle system for Baidu."

The FZ3A hardware manual and the schematics are authored by ALINX - the
manual cover carries the ALINX logo, www.alinx.com and the legal name
above, and every schematic sheet has the same ALINX title block.

Since ALINX is the hardware designer, I used "alinx" as the prefix
instead of "baidu". Happy to switch if you prefer the marketing brand.

[1] 
https://vd100-20232-v101.readthedocs.io/zh-cn/en/VD100_S1_RSTdocument_EN/00_aboutALINX_EN.html

For v3:
   - Fix the v2 description mistransliteration of the legal name:
       "^alinx,.*":
         description: Xinyi Electronic Technology (Shanghai) Co., Ltd. 
(ALINX)
   - Put the website URL in the commit message.

Thanks for the ack on patch 2/3, I will carry it into v3.

Best regards,
Pufan Jin

Re: [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix

[Conor Dooley]

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On Thu, Oct 08, 2026 at 01:36:35AM +0800, Pufan Jin wrote:
> 
> On 2026/10/7 18:35, Conor Dooley wrote:
> > On Tue, Oct 06, 2026 at 01:33:06AM +0800, Pufan Jin wrote:
> > > Add vendor prefix for ALINX (Shanghai Xin'yi Electronics Technology
> > > Co., Ltd.).
> > Where does this ALINX come from? Website url?
> > 
> > > Signed-off-by: Pufan Jin <2254650260@qq.com>
> > > ---
> > >   Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> > >   1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > > index ba2002969..97e7ef340 100644
> > > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > > @@ -90,6 +90,8 @@ patternProperties:
> > >       description: AlgolTek, Inc.
> > >     "^alientek,.*":
> > >       description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
> > > +  "^alinx,.*":
> > > +    description: Shanghai Xin'yi Electronics Technology Co., Ltd. (ALINX)
> > >     "^allegro,.*":
> > >       description: Allegro DVT
> > >     "^allegromicro,.*":
> > > -- 
> > > 2.55.0
> 
> Hi Conor,
> 
> ALINX is the brand of Xinyi Electronic Technology (Shanghai) Co., Ltd.
> (芯驿电子科技（上海）有限公司), https://www.alinx.com/ - an FPGA/SoC
> company and official partner of AMD Xilinx, Unisoc and Baidu.

In that case,
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
Link: https://www.alinx.com/

Thanks,
Conor.

> 
> The board is not in the alinx.com shop because ALINX describes EdgeBoard
> as a customisation done for Baidu: Baidu owns the EdgeBoard brand and the
> sales channel, while ALINX designs and manufactures the hardware. From
> ALINX's own product documentation [1]:
> 
> "...as a Baidu AI partner, it has customized the Edgeboard series edge
>  devices of the domestic AI flying paddle system for Baidu."
> 
> The FZ3A hardware manual and the schematics are authored by ALINX - the
> manual cover carries the ALINX logo, www.alinx.com and the legal name
> above, and every schematic sheet has the same ALINX title block.
> 
> Since ALINX is the hardware designer, I used "alinx" as the prefix
> instead of "baidu". Happy to switch if you prefer the marketing brand.
> 
> [1] https://vd100-20232-v101.readthedocs.io/zh-cn/en/VD100_S1_RSTdocument_EN/00_aboutALINX_EN.html
> 
> For v3:
>   - Fix the v2 description mistransliteration of the legal name:
>       "^alinx,.*":
>         description: Xinyi Electronic Technology (Shanghai) Co., Ltd.
> (ALINX)
>   - Put the website URL in the commit message.
> 
> Thanks for the ack on patch 2/3, I will carry it into v3.
> 
> Best regards,
> Pufan Jin
> 
> 

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[PATCH v2 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A

[Pufan Jin]

Document the ALINX EdgeBoard FZ3A compatible.

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df..ad7c71f9b 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -46,6 +46,7 @@ properties:
 
       - items:
           - enum:
+              - alinx,edgeboard-fz3a
               - xlnx,zynqmp-zc1751
           - const: xlnx,zynqmp
 
-- 
2.55.0

Re: [PATCH v2 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A

[Conor Dooley]

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On Tue, Oct 06, 2026 at 01:33:07AM +0800, Pufan Jin wrote:
> Document the ALINX EdgeBoard FZ3A compatible.
> 
> Signed-off-by: Pufan Jin <2254650260@qq.com>

Modulo the prefix being acceptable,
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> ---
>  Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> index c9f99e0df..ad7c71f9b 100644
> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> @@ -46,6 +46,7 @@ properties:
>  
>        - items:
>            - enum:
> +              - alinx,edgeboard-fz3a
>                - xlnx,zynqmp-zc1751
>            - const: xlnx,zynqmp
>  
> -- 
> 2.55.0
> 

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[PATCH v2 3/3] arm64: zynqmp: Add ALINX EdgeBoard FZ3A

[Pufan Jin]

Add device tree for the ALINX EdgeBoard FZ3A, a single board computer
based on the Xilinx Zynq UltraScale+ XCZU3EG SoC.

Supported peripherals:
  - UART1 debug console
  - eMMC (HS200) and microSD card
  - GEM3 Ethernet with Micrel KSZ9031 PHY on the MDIO bus
  - I2C0 and I2C1
  - QSPI NOR flash
  - PCIe
  - USB 3.0 host
  - DisplayPort output

Tested on hardware with Linux 7.3.0-rc5: the board boots from SD card
into userspace over the serial console, gem3 negotiates 1000Mbps/Full
duplex with phy-mode = "rgmii-id", and the eMMC runs in HS200 mode.

The base DTB passes CHECK_DTBS=y, and the Xilinx SoC binding passes
dt_binding_check.

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 arch/arm64/boot/dts/xilinx/Makefile           |   1 +
 .../xilinx/zynqmp-alinx-edgeboard-fz3a.dts    | 350 ++++++++++++++++++
 2 files changed, 351 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts

diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 70fac0b27..3e07b36ef 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-alinx-edgeboard-fz3a.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts b/arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
new file mode 100644
index 000000000..ab6bda7a6
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for the ALINX EdgeBoard FZ3A
+ * based on the Xilinx Zynq UltraScale+ XCZU3EG
+ *
+ * Copyright (c) 2026 Pufan Jin
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+	model = "ALINX EdgeBoard FZ3A";
+	compatible = "alinx,edgeboard-fz3a", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dpcon: connector {
+		compatible = "dp-connector";
+		label = "mini-DP";
+		type = "mini";
+
+		port {
+			dpcon_in: endpoint {
+				remote-endpoint = <&dpsub_dp_out>;
+			};
+		};
+	};
+
+	dp_aclk: clock-dp-aclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	gtr_refclk0: clock-gtr-ref0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	gtr_refclk1: clock-gtr-ref1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	gtr_refclk2: clock-gtr-ref2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
+	/*
+	 * Vendor TF-A 1.8.1 does not register LPD_LSBUS (ID 31) into CCF.
+	 * Provide a fixed-clock fallback for bus peripherals to probe.
+	 */
+	lpd_lsbus: clock-lpd-lsbus {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x7ff00000>;
+	};
+
+	vcc_3v3_pcie: regulator-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie-reset";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux_cma: cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			size = <0x0 0x20000000>;	/* 512MB */
+			linux,cma-default;
+		};
+	};
+};
+
+&ams_pl {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&dwc3_0 {
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	snps,dis_enblslpm_quirk;
+	snps,dis_u2_susphy_quirk;
+	snps,hsphy_interface = "ulpi";
+	snps,usb3_lpm_capable;
+	status = "okay";
+};
+
+&gem3 {
+	clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
+		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+		 <&zynqmp_clk GEM_TSU>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gem3_default>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&phy0>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+			reg = <1>;
+			compatible = "ethernet-phy-id0022.1620";
+		};
+	};
+};
+
+&gpio {
+	clocks = <&lpd_lsbus>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_default>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_default>;
+	status = "okay";
+};
+
+&out_dp {
+	dpsub_dp_out: endpoint {
+		remote-endpoint = <&dpcon_in>;
+	};
+};
+
+&pcie {
+	phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
+	status = "okay";
+};
+
+&pinctrl0 {
+	status = "okay";
+
+	pinctrl_i2c0_default: i2c0-default {
+		conf {
+			bias-pull-up;
+			groups = "i2c0_8_grp";
+		};
+
+		mux {
+			function = "i2c0";
+			groups = "i2c0_8_grp";
+		};
+	};
+
+	pinctrl_i2c1_default: i2c1-default {
+		conf {
+			bias-pull-up;
+			groups = "i2c1_8_grp";
+		};
+
+		mux {
+			function = "i2c1";
+			groups = "i2c1_8_grp";
+		};
+	};
+
+	pinctrl_usb0_default: usb0-default {
+		mux {
+			function = "usb0";
+			groups = "usb0_0_grp";
+		};
+	};
+
+	pinctrl_sdhci0_default: sdhci0-default {
+		mux {
+			groups = "sdio0_0_grp";
+			function = "sdio0";
+		};
+
+		conf {
+			groups = "sdio0_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			bias-disable;
+		};
+	};
+
+	/*
+	 * Omit 'power-source' and 'bias-high-impedance' to avoid spurious
+	 * warnings on the board's pre-2023.1 PM firmware. Bank voltage
+	 * and pin directions are already configured by hardware.
+	 */
+	pinctrl_gem3_default: gem3-default {
+		mux {
+			function = "ethernet3";
+			groups = "ethernet3_0_grp";
+		};
+
+		conf {
+			groups = "ethernet3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+		};
+
+		conf-rx {
+			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+			       "MIO75";
+			low-power-disable;
+		};
+
+		conf-tx {
+			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+			       "MIO69";
+			bias-disable;
+			low-power-enable;
+		};
+
+		mux-mdio {
+			function = "mdio3";
+			groups = "mdio3_0_grp";
+		};
+
+		conf-mdio {
+			groups = "mdio3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			bias-disable;
+		};
+	};
+};
+
+&psgtr {
+	clocks = <&gtr_refclk0>, <&gtr_refclk1>, <&gtr_refclk2>;
+	clock-names = "ref0", "ref1", "ref2";
+	status = "okay";
+};
+
+&qspi {
+	clocks = <&zynqmp_clk QSPI_REF>, <&lpd_lsbus>;
+	num-cs = <1>;
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&sdhci0 {
+	clocks = <&zynqmp_clk SDIO0_REF>, <&lpd_lsbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci0_default>;
+	non-removable;
+	disable-wp;
+	no-sd;
+	no-sdio;
+	mmc-hs200-1_8v;
+	cap-mmc-hw-reset;
+	bus-width = <8>;
+	xlnx,mio-bank = <0>;
+	assigned-clock-rates = <187498125>;
+	status = "okay";
+};
+
+&sdhci1 {
+	clocks = <&zynqmp_clk SDIO1_REF>, <&lpd_lsbus>;
+	disable-wp;
+	no-1-8-v;
+	status = "okay";
+};
+
+&uart0 {
+	clocks = <&zynqmp_clk UART0_REF>, <&lpd_lsbus>;
+	status = "okay";
+};
+
+&uart1 {
+	clocks = <&zynqmp_clk UART1_REF>, <&lpd_lsbus>;
+	status = "okay";
+};
+
+&usb0 {
+	phy-names = "usb3-phy";
+	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_default>;
+	reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&zynqmp_dpdma {
+	status = "okay";
+};
+
+&zynqmp_dpsub {
+	clocks = <&dp_aclk>,
+		 <&zynqmp_clk DP_AUDIO_REF>,
+		 <&zynqmp_clk DP_VIDEO_REF>;
+	clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 3 PHY_TYPE_DP 0 2>,
+	       <&psgtr 2 PHY_TYPE_DP 1 2>;
+	status = "okay";
+};
-- 
2.55.0

Re: [PATCH v2 3/3] arm64: zynqmp: Add ALINX EdgeBoard FZ3A

[Michal Simek]

On 10/5/26 19:33, Pufan Jin wrote:
> Add device tree for the ALINX EdgeBoard FZ3A, a single board computer
> based on the Xilinx Zynq UltraScale+ XCZU3EG SoC.
> 
> Supported peripherals:
>    - UART1 debug console
>    - eMMC (HS200) and microSD card
>    - GEM3 Ethernet with Micrel KSZ9031 PHY on the MDIO bus
>    - I2C0 and I2C1
>    - QSPI NOR flash
>    - PCIe
>    - USB 3.0 host
>    - DisplayPort output
> 
> Tested on hardware with Linux 7.3.0-rc5: the board boots from SD card
> into userspace over the serial console, gem3 negotiates 1000Mbps/Full
> duplex with phy-mode = "rgmii-id", and the eMMC runs in HS200 mode.
> 
> The base DTB passes CHECK_DTBS=y, and the Xilinx SoC binding passes
> dt_binding_check.
> 
> Signed-off-by: Pufan Jin <2254650260@qq.com>
> ---
>   arch/arm64/boot/dts/xilinx/Makefile           |   1 +
>   .../xilinx/zynqmp-alinx-edgeboard-fz3a.dts    | 350 ++++++++++++++++++
>   2 files changed, 351 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
This series has no cover letter and I can't see any link to public board 
documentation. Please provide it and then I will take a look at it.
But please send proper v3.

Thanks,
Michal

[PATCH v2 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A

[Pufan Jin]

Document the ALINX EdgeBoard FZ3A compatible.

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df..ad7c71f9b 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -46,6 +46,7 @@ properties:
 
       - items:
           - enum:
+              - alinx,edgeboard-fz3a
               - xlnx,zynqmp-zc1751
           - const: xlnx,zynqmp
 
-- 
2.55.0