* [PATCH v15 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:16 ` [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
` (7 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su, Jonathan Cameron
From: Ira Weiny <iweiny@kernel.org>
Per the CXL 4.0 specification software must check the Command Effects
Log (CEL) for dynamic capacity command support.
Detect support for the DCD commands while reading the CEL, including:
Get DC Config
Get DC Extent List
Add DC Response
Release DC
Leave mds->dcd_supported false. Dynamic capacity is only usable once
the driver can handle Add and Release Capacity events. Detect and log
the capability here and let the commit which adds DCD event handling set
the flag.
Based on an original patch by Navneet Singh.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Gregory Price (Meta) <gourry@gourry.net>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
drivers/cxl/core/mbox.c | 39 +++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxlmem.h | 20 ++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 55828a836c01..199bb986d674 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -171,6 +171,33 @@ static void cxl_set_security_cmd_enabled(struct cxl_security_state *security,
}
}
+static bool cxl_is_dcd_command(u16 opcode)
+{
+#define CXL_MBOX_OP_DCD_CMDS 0x48
+
+ return (opcode >> 8) == CXL_MBOX_OP_DCD_CMDS;
+}
+
+static void cxl_set_dcd_cmd_enabled(u16 opcode, unsigned long *cmd_mask)
+{
+ switch (opcode) {
+ case CXL_MBOX_OP_GET_DC_CONFIG:
+ set_bit(CXL_DCD_ENABLED_GET_CONFIG, cmd_mask);
+ break;
+ case CXL_MBOX_OP_GET_DC_EXTENT_LIST:
+ set_bit(CXL_DCD_ENABLED_GET_EXTENT_LIST, cmd_mask);
+ break;
+ case CXL_MBOX_OP_ADD_DC_RESPONSE:
+ set_bit(CXL_DCD_ENABLED_ADD_RESPONSE, cmd_mask);
+ break;
+ case CXL_MBOX_OP_RELEASE_DC:
+ set_bit(CXL_DCD_ENABLED_RELEASE, cmd_mask);
+ break;
+ default:
+ break;
+ }
+}
+
static bool cxl_is_poison_command(u16 opcode)
{
#define CXL_MBOX_OP_POISON_CMDS 0x43
@@ -759,6 +786,7 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
struct cxl_cel_entry *cel_entry;
const int cel_entries = size / sizeof(*cel_entry);
+ DECLARE_BITMAP(dcd_cmds, CXL_DCD_ENABLED_MAX) = {};
struct device *dev = mds->cxlds.dev;
int i, ro_cmds = 0, wr_cmds = 0;
@@ -787,11 +815,22 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)
enabled++;
}
+ if (cxl_is_dcd_command(opcode)) {
+ cxl_set_dcd_cmd_enabled(opcode, dcd_cmds);
+ enabled++;
+ }
+
dev_dbg(dev, "Opcode 0x%04x %s\n", opcode,
enabled ? "enabled" : "unsupported by driver");
}
set_features_cap(cxl_mbox, ro_cmds, wr_cmds);
+ /*
+ * Disabled until event handling implemented.
+ */
+ if (bitmap_full(dcd_cmds, CXL_DCD_ENABLED_MAX))
+ dev_dbg(dev, "Device supports DCD; capability disabled\n");
+ mds->dcd_supported = false;
}
static struct cxl_mbox_get_supported_logs *cxl_get_gsl(struct cxl_memdev_state *mds)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index c401e3a1af06..0c8e23276dc6 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -252,6 +252,20 @@ struct cxl_event_state {
struct mutex log_lock;
};
+/*
+ * CXL r4.0 Section 8.2.10.9 - Memory Device Command Sets. See Table 8-308.
+ *
+ * The 48h Command Set (Opcodes 4800h - 4803h) defines the device-enabled DCD
+ * commands.
+ */
+enum dcd_cmd_enabled_bits {
+ CXL_DCD_ENABLED_GET_CONFIG,
+ CXL_DCD_ENABLED_GET_EXTENT_LIST,
+ CXL_DCD_ENABLED_ADD_RESPONSE,
+ CXL_DCD_ENABLED_RELEASE,
+ CXL_DCD_ENABLED_MAX
+};
+
/* Device enabled poison commands */
enum poison_cmd_enabled_bits {
CXL_POISON_ENABLED_LIST,
@@ -427,6 +441,7 @@ static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)
* @partition_align_bytes: alignment size for partition-able capacity
* @active_volatile_bytes: sum of hard + soft volatile
* @active_persistent_bytes: sum of hard + soft persistent
+ * @dcd_supported: all DCD commands are supported
* @event: event log driver state
* @poison: poison driver state info
* @security: security driver state info
@@ -445,6 +460,7 @@ struct cxl_memdev_state {
u64 partition_align_bytes;
u64 active_volatile_bytes;
u64 active_persistent_bytes;
+ bool dcd_supported;
struct cxl_event_state event;
struct cxl_poison_state poison;
@@ -505,6 +521,10 @@ enum cxl_opcode {
CXL_MBOX_OP_UNLOCK = 0x4503,
CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
+ CXL_MBOX_OP_GET_DC_CONFIG = 0x4800,
+ CXL_MBOX_OP_GET_DC_EXTENT_LIST = 0x4801,
+ CXL_MBOX_OP_ADD_DC_RESPONSE = 0x4802,
+ CXL_MBOX_OP_RELEASE_DC = 0x4803,
CXL_MBOX_OP_MAX = 0x10000
};
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
2026-10-07 20:16 ` [PATCH v15 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:29 ` sashiko-bot
` (2 more replies)
2026-10-07 20:16 ` [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
` (6 subsequent siblings)
8 siblings, 3 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Devices which support Dynamic Capacity (DC) are configured via mailbox
commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
Configuration command in order to obtain DCD partition characteristics.
Implement the DC mailbox commands as specified in CXL 4.0 section
8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
information. Disable DCD if an invalid configuration is found.
Initial enablement for Linux only supports one dynamic capacity
partition. Read all the partitions the device reports but validate
only the first, and configure it as 'dynamic ram'.
The specification requires that volatile capacity starts at DPA 0 and
pmem starts at the DPA immediately following it, but DC partitions only
need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
Table 8-347. So a device could leave a gap between ram/pmem (static)
capacity and its first DC partition, or between one DC partition and
the next.
However, Linux chooses not to support gaps between static and dynamic
capacity, and requires the first DC partition to begin at the DPA
immediately following static capacity.
Based on an original patch by Navneet Singh.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
---
Changes:
1. Partition mode renamed CXL_PARTMODE_DYNAMIC_RAM: the mode says what
kind of capacity this is, not which partition. The DC partition's
resource name carries its position instead, dynamic_ram_1 for the
first, formatted in cxl_dpa_setup().
---
drivers/cxl/core/hdm.c | 13 ++-
drivers/cxl/core/mbox.c | 237 ++++++++++++++++++++++++++++++++++++++
drivers/cxl/core/memdev.c | 47 ++++++++
drivers/cxl/cxlmem.h | 55 +++++++++
drivers/cxl/pci.c | 6 +
include/cxl/cxl.h | 3 +-
6 files changed, 359 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 0c80b76a5f9b..5fa2177cefcc 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -446,6 +446,8 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
return "ram";
case CXL_PARTMODE_PMEM:
return "pmem";
+ case CXL_PARTMODE_DYNAMIC_RAM:
+ return "dynamic_ram";
default:
return "";
};
@@ -455,6 +457,7 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
{
struct device *dev = cxlds->dev;
+ int dc_nth = 0;
guard(rwsem_write)(&cxl_rwsem.dpa);
@@ -471,8 +474,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
for (int i = 0; i < info->nr_partitions; i++) {
const struct cxl_dpa_part_info *part = &info->part[i];
+ const char *name = cxl_mode_name(part->mode);
int rc;
+ if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", name,
+ ++dc_nth);
+ if (!name)
+ return -ENOMEM;
+ }
+
cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
cxlds->part[i].mode = part->mode;
@@ -485,7 +496,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
}
rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->part[i].res,
part->range.start, range_len(&part->range),
- cxl_mode_name(part->mode));
+ name);
if (rc)
return rc;
cxlds->nr_partitions++;
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 199bb986d674..72af23ba288e 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1349,6 +1349,243 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
return -EBUSY;
}
+/*
+ * A partition unavailable for Dynamic Capacity reports zeros for decode_length,
+ * length, and block_size.
+ */
+static bool cxl_dc_partition_unavailable(struct cxl_dc_partition *dev_part)
+{
+ return !le64_to_cpu(dev_part->decode_length) &&
+ !le64_to_cpu(dev_part->length) &&
+ !le64_to_cpu(dev_part->block_size);
+}
+
+static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
+ struct cxl_dc_partition *dev_part)
+{
+ u64 decode_len = le64_to_cpu(dev_part->decode_length);
+ u64 blk_size = le64_to_cpu(dev_part->block_size);
+ u64 len = le64_to_cpu(dev_part->length);
+ u64 size;
+
+ /*
+ * Not an error; leave the entry empty. A partially zeroed partition
+ * is rejected by the checks below. CXL r4.0 Table 8-347.
+ */
+ if (cxl_dc_partition_unavailable(dev_part)) {
+ *part = (struct cxl_dc_partition_info) { };
+ dev_dbg(dev, "Partition 0 unavailable for DC\n");
+ return 0;
+ }
+
+ /*
+ * Decode length is a count of 256M units, so a device reporting 2^36
+ * or more wraps.
+ */
+ if (check_mul_overflow(decode_len, (u64)CXL_CAPACITY_MULTIPLIER, &size)) {
+ dev_err(dev, "DC partition 0 decode length %#llx overflows\n",
+ decode_len);
+ return -EINVAL;
+ }
+
+ *part = (struct cxl_dc_partition_info) {
+ .start = le64_to_cpu(dev_part->base),
+ .size = size,
+ };
+
+ /*
+ * Block size is a power of 2 and a multiple of 40h. is_power_of_2()
+ * takes an unsigned long, which truncates blk_size on 32 bit.
+ */
+ if (blk_size == 0 || (blk_size & (blk_size - 1)) ||
+ blk_size % CXL_DCD_BLOCK_LINE_SIZE) {
+ dev_err(dev, "DC partition 0 invalid block size %#llx\n", blk_size);
+ return -EINVAL;
+ }
+
+ if (part->size == 0) {
+ dev_err(dev, "DC partition 0 zero decode length\n");
+ return -EINVAL;
+ }
+
+ if (len == 0) {
+ dev_err(dev, "DC partition 0 zero length\n");
+ return -EINVAL;
+ }
+
+ if (len > part->size) {
+ dev_err(dev, "DC partition 0 length %#llx exceeds decode length %#llx\n",
+ len, part->size);
+ return -EINVAL;
+ }
+
+ if (!IS_ALIGNED(len, blk_size)) {
+ dev_err(dev, "DC partition 0 length %#llx not a multiple of block size %#llx\n",
+ len, blk_size);
+ return -EINVAL;
+ }
+
+ if (!IS_ALIGNED(part->start, SZ_256M)) {
+ dev_err(dev, "DC partition 0 base %#llx not aligned to 256M\n",
+ part->start);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "DC partition 0 start %#llx size %#llx blk_size: %#llx\n",
+ part->start, part->size, blk_size);
+
+ return 0;
+}
+
+/* Returns the number of partitions in dc_resp or -ERRNO */
+static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
+ u8 partition_count,
+ struct cxl_mbox_get_dc_config_out *dc_resp,
+ size_t dc_resp_size)
+{
+ struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
+ .partition_count = partition_count,
+ .start_partition_index = start_partition,
+ };
+ struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
+ .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
+ .payload_in = &get_dc,
+ .size_in = sizeof(get_dc),
+ .size_out = dc_resp_size,
+ .payload_out = dc_resp,
+ /* The device must return at least the fixed header */
+ .min_out = sizeof(*dc_resp),
+ };
+ size_t expected_sz;
+ int rc;
+
+ rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
+ if (rc < 0)
+ return rc;
+
+ if (dc_resp->partitions_returned > partition_count) {
+ dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
+ dc_resp->partitions_returned, partition_count);
+ return -EIO;
+ }
+
+ /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
+ expected_sz = struct_size(dc_resp, partition,
+ dc_resp->partitions_returned);
+
+ if (mbox_cmd.size_out < expected_sz) {
+ dev_err(mbox->host,
+ "Payload size %zu less than expected %zu for %u partitions\n",
+ mbox_cmd.size_out,
+ expected_sz,
+ dc_resp->partitions_returned);
+ return -EIO;
+ }
+
+ dev_dbg(mbox->host, "Read %d/%d DC partitions\n",
+ dc_resp->partitions_returned, dc_resp->avail_partition_count);
+ return dc_resp->partitions_returned;
+}
+
+/**
+ * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
+ * device.
+ * @mbox: Mailbox to query
+ * @dc_info: The dynamic partition information to return
+ *
+ * Read every partition the device reports, but validate only the first:
+ * Linux maps partition 0 and nothing else, so a defect in capacity the
+ * driver never touches is not a reason to refuse the device dynamic
+ * capacity. The remaining partitions are read but not recorded.
+ *
+ * Return: 0 if identify was executed successfully, -ERRNO on error.
+ * On error, @dc_info is left unchanged.
+ */
+int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
+ struct cxl_dc_partition_info *dc_info)
+{
+ struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
+ struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
+ struct device *dev = mbox->host;
+ u8 avail_partitions = 0;
+ u8 start_partition;
+ u8 num_partitions;
+ u8 partition_count;
+ size_t dc_resp_size;
+
+ /*
+ * Bound requested number of partitions by mailbox payload size. The
+ * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
+ * the subtraction below from underflowing.
+ */
+ partition_count = min(CXL_MAX_DC_PARTITIONS,
+ (mbox->payload_size - sizeof(*dc_resp) -
+ sizeof(struct cxl_mbox_get_dc_config_tail)) /
+ sizeof(struct cxl_dc_partition));
+ dc_resp_size = struct_size(dc_resp, partition, partition_count) +
+ sizeof(struct cxl_mbox_get_dc_config_tail);
+
+ dc_resp = kmalloc(dc_resp_size, GFP_KERNEL);
+ if (!dc_resp)
+ return -ENOMEM;
+
+ start_partition = 0;
+ num_partitions = 0;
+ do {
+ int returned, rc;
+
+ returned = cxl_get_dc_config(mbox, start_partition,
+ partition_count, dc_resp,
+ dc_resp_size);
+ if (returned < 0) {
+ dev_err(dev, "Failed to get DC config: %d\n", returned);
+ return returned;
+ }
+
+ if (returned == 0) {
+ dev_err(dev,
+ "Device reported %u partitions available but returned none at index %u\n",
+ dc_resp->avail_partition_count, start_partition);
+ return -EIO;
+ }
+
+ /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
+ if (dc_resp->avail_partition_count == 0) {
+ dev_err(dev, "Device reported no DC partitions\n");
+ return -EIO;
+ }
+
+ avail_partitions = min(dc_resp->avail_partition_count,
+ CXL_MAX_DC_PARTITIONS);
+
+ /*
+ * Only partition 0 is mapped, so it is the only one checked.
+ * The rest are read to complete the enumeration and dropped.
+ */
+ if (start_partition == 0) {
+ rc = cxl_dc_check(dev, &partitions[0],
+ &dc_resp->partition[0]);
+ if (rc)
+ return rc;
+ }
+
+ num_partitions += returned;
+ start_partition = num_partitions;
+
+ } while (num_partitions < avail_partitions);
+
+ /* Linux only supports the 1st partition; nothing to do if it is unavailable */
+ if (partitions[0].size == 0)
+ return -ENODEV;
+
+ *dc_info = partitions[0];
+ dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
+ dc_info->start, dc_info->size);
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
+
int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
{
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index b3419df586b9..def26c490dfe 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -643,6 +643,53 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
+int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
+{
+ struct cxl_dc_partition_info dc_info = { };
+ struct device *dev = mds->cxlds.dev;
+ u64 total;
+ int rc;
+
+ if (!mds->cxlds.media_ready)
+ return 0;
+
+ rc = cxl_dev_dc_identify(&mds->cxlds.cxl_mbox, &dc_info);
+ if (rc) {
+ dev_warn(dev,
+ "Failed to read Dynamic Capacity config: %d\n", rc);
+ return rc;
+ }
+
+ if (dc_info.start < info->size) {
+ dev_err(dev,
+ "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
+ dc_info.start, info->size);
+ return -EINVAL;
+ }
+
+ /* A gap between static capacity and the DC partition is not supported */
+ if (dc_info.start > info->size) {
+ dev_warn(dev,
+ "DC partition 0 base %#llx leaves a gap from static capacity ending at %#llx\n",
+ dc_info.start, info->size);
+ return -EOPNOTSUPP;
+ }
+
+ if (check_add_overflow(info->size, dc_info.size, &total)) {
+ dev_err(dev,
+ "DC partition 0 size %#llx overflows DPA space ending at %#llx\n",
+ dc_info.size, info->size);
+ return -EINVAL;
+ }
+
+ info->size = total;
+ dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
+ dc_info.start, dc_info.size);
+ add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_configure_dcd, "CXL");
/**
* cxl_set_capacity: initialize dpa by a driver without a mailbox.
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 0c8e23276dc6..4fac65dbb808 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -407,6 +407,8 @@ struct cxl_security_state {
struct kernfs_node *sanitize_node;
};
+#define CXL_MAX_DC_PARTITIONS 8
+
static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
{
/*
@@ -689,6 +691,39 @@ struct cxl_mbox_set_shutdown_state_in {
u8 state;
} __packed;
+/* See CXL r4.0 Table 8-345 get dynamic capacity config Input Payload */
+struct cxl_mbox_get_dc_config_in {
+ u8 partition_count;
+ u8 start_partition_index;
+} __packed;
+
+/* See CXL r4.0 Table 8-346 get dynamic capacity config Output Payload */
+struct cxl_mbox_get_dc_config_out {
+ u8 avail_partition_count;
+ u8 partitions_returned;
+ u8 rsvd[6];
+ /* See CXL r4.0 Table 8-347 */
+ struct cxl_dc_partition {
+ __le64 base;
+ __le64 decode_length;
+ __le64 length;
+ __le64 block_size;
+ __le32 dsmad_handle;
+ u8 flags;
+ u8 rsvd[3];
+ } __packed partition[] __counted_by(partitions_returned);
+ /* Trailing extent/tag count fields unused */
+} __packed;
+
+/* Trailing counts; cannot be a member after the flex array above */
+struct cxl_mbox_get_dc_config_tail {
+ __le32 num_extents_supported;
+ __le32 num_extents_available;
+ __le32 num_tags_supported;
+ __le32 num_tags_available;
+} __packed;
+#define CXL_DCD_BLOCK_LINE_SIZE 0x40
+
/* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
struct cxl_mbox_set_timestamp_in {
__le64 timestamp;
@@ -812,9 +847,18 @@ enum {
int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
struct cxl_mbox_cmd *cmd);
int cxl_dev_state_identify(struct cxl_memdev_state *mds);
+
+struct cxl_dc_partition_info {
+ u64 start;
+ u64 size;
+};
+
+int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
+ struct cxl_dc_partition_info *dc_info);
int cxl_await_media_ready(struct cxl_dev_state *cxlds);
int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
+int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
u16 dvsec);
void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
@@ -828,6 +872,17 @@ void cxl_event_trace_record(struct cxl_memdev *cxlmd,
const uuid_t *uuid, union cxl_event *evt);
int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
+
+static inline bool cxl_dcd_supported(struct cxl_memdev_state *mds)
+{
+ return mds->dcd_supported;
+}
+
+static inline void cxl_disable_dcd(struct cxl_memdev_state *mds)
+{
+ mds->dcd_supported = false;
+}
+
int cxl_set_timestamp(struct cxl_memdev_state *mds);
int cxl_poison_state_init(struct cxl_memdev_state *mds);
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index c7c91e8dc51d..2fe9db4b3d86 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -868,6 +868,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ if (cxl_dcd_supported(mds)) {
+ rc = cxl_configure_dcd(mds, &range_info);
+ if (rc)
+ cxl_disable_dcd(mds);
+ }
+
rc = cxl_dpa_setup(cxlds, &range_info);
if (rc)
return rc;
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 802b143de83d..e07360849344 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -133,6 +133,7 @@ struct cxl_dpa_perf {
enum cxl_partition_mode {
CXL_PARTMODE_RAM,
CXL_PARTMODE_PMEM,
+ CXL_PARTMODE_DYNAMIC_RAM,
};
/**
@@ -147,7 +148,7 @@ struct cxl_dpa_partition {
enum cxl_partition_mode mode;
};
-#define CXL_NR_PARTITIONS_MAX 2
+#define CXL_NR_PARTITIONS_MAX 3
/**
* struct cxl_dev_state - The driver device state
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-07 20:16 ` [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
@ 2026-10-07 20:29 ` sashiko-bot
2026-10-07 21:25 ` Anisa Su
2026-10-07 23:43 ` Alison Schofield
2026-10-08 8:33 ` Richard Cheng
2 siblings, 1 reply; 20+ messages in thread
From: sashiko-bot @ 2026-10-07 20:29 UTC (permalink / raw)
To: Anisa Su; +Cc: nvdimm, linux-cxl
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] cxl: cxl_configure_dcd() falsely fails overlap check and double-counts total DPA capacity
--
commit e491a6175f0241ed507a397807a28860fd54aadf
Author: Ira Weiny <iweiny@kernel.org>
cxl/mem: Read dynamic capacity configuration from the device
This commit implements Dynamic Capacity (DC) mailbox commands to read and
store DCD configuration information. It validates the first dynamic capacity
partition and configures it as dynamic ram, disabling DCD if the
configuration is invalid.
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index b3419df586b9c..def26c490dfe4 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
[ ... ]
> @@ -643,6 +643,53 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
>
> +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> +{
[ ... ]
> + if (dc_info.start < info->size) {
> + dev_err(dev,
> + "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
> + dc_info.start, info->size);
> + return -EINVAL;
> + }
[Severity: High]
Will this overlap check unconditionally fail for any valid DCD configuration?
Earlier in the execution flow, cxl_mem_dpa_fetch() initializes info->size to
the total DPA capacity (including both static and dynamic capacity):
info->size = mds->total_bytes;
Since the DC partition is placed within this total space, dc_info.start will
always be strictly less than the total info->size. This appears to cause a
regression where cxl_pci_probe() silently disables DCD support.
[ ... ]
> + if (check_add_overflow(info->size, dc_info.size, &total)) {
> + dev_err(dev,
> + "DC partition 0 size %#llx overflows DPA space ending at %#llx\n",
> + dc_info.size, info->size);
> + return -EINVAL;
> + }
> +
> + info->size = total;
[Severity: High]
If the above overlap check were bypassed, would this assignment double-count
the dynamic capacity size?
Since info->size already includes the dynamic capacity initialized from
cxl_mem_dpa_fetch(), adding dc_info.size again to the total could cause
cxl_dpa_setup() to allocate a dpa_res root resource larger than the physical
device limit.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261007201828.952-1-anisa.su@samsung.com?part=2
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-07 20:29 ` sashiko-bot
@ 2026-10-07 21:25 ` Anisa Su
0 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 21:25 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Anisa Su, nvdimm, linux-cxl
On Wed, Oct 07, 2026 at 08:29:34PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] cxl: cxl_configure_dcd() falsely fails overlap check and double-counts total DPA capacity
False Positive
> --
>
> commit e491a6175f0241ed507a397807a28860fd54aadf
> Author: Ira Weiny <iweiny@kernel.org>
>
> cxl/mem: Read dynamic capacity configuration from the device
>
> This commit implements Dynamic Capacity (DC) mailbox commands to read and
> store DCD configuration information. It validates the first dynamic capacity
> partition and configures it as dynamic ram, disabling DCD if the
> configuration is invalid.
>
> > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> > index b3419df586b9c..def26c490dfe4 100644
> > --- a/drivers/cxl/core/memdev.c
> > +++ b/drivers/cxl/core/memdev.c
> [ ... ]
> > @@ -643,6 +643,53 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> > }
> > EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
> >
> > +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> > +{
> [ ... ]
> > + if (dc_info.start < info->size) {
> > + dev_err(dev,
> > + "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
> > + dc_info.start, info->size);
> > + return -EINVAL;
> > + }
>
> [Severity: High]
> Will this overlap check unconditionally fail for any valid DCD configuration?
>
> Earlier in the execution flow, cxl_mem_dpa_fetch() initializes info->size to
> the total DPA capacity (including both static and dynamic capacity):
>
info->size does not include dynamic capacity.
> info->size = mds->total_bytes;
>
> Since the DC partition is placed within this total space, dc_info.start will
> always be strictly less than the total info->size. This appears to cause a
> regression where cxl_pci_probe() silently disables DCD support.
>
> [ ... ]
> > + if (check_add_overflow(info->size, dc_info.size, &total)) {
> > + dev_err(dev,
> > + "DC partition 0 size %#llx overflows DPA space ending at %#llx\n",
> > + dc_info.size, info->size);
> > + return -EINVAL;
> > + }
> > +
> > + info->size = total;
>
> [Severity: High]
> If the above overlap check were bypassed, would this assignment double-count
> the dynamic capacity size?
>
> Since info->size already includes the dynamic capacity initialized from
info->size does not include dynamic capacity.
> cxl_mem_dpa_fetch(), adding dc_info.size again to the total could cause
> cxl_dpa_setup() to allocate a dpa_res root resource larger than the physical
> device limit.
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20261007201828.952-1-anisa.su@samsung.com?part=2
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-07 20:16 ` [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-10-07 20:29 ` sashiko-bot
@ 2026-10-07 23:43 ` Alison Schofield
2026-10-08 8:15 ` Anisa Su
2026-10-08 8:33 ` Richard Cheng
2 siblings, 1 reply; 20+ messages in thread
From: Alison Schofield @ 2026-10-07 23:43 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dan Williams, Dave Jiang,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
On Wed, Oct 07, 2026 at 01:16:35PM -0700, Anisa Su wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Devices which support Dynamic Capacity (DC) are configured via mailbox
> commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
> Configuration command in order to obtain DCD partition characteristics.
>
> Implement the DC mailbox commands as specified in CXL 4.0 section
> 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
> information. Disable DCD if an invalid configuration is found.
>
> Initial enablement for Linux only supports one dynamic capacity
> partition. Read all the partitions the device reports but validate
> only the first, and configure it as 'dynamic ram'.
>
> The specification requires that volatile capacity starts at DPA 0 and
> pmem starts at the DPA immediately following it, but DC partitions only
> need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
> Table 8-347. So a device could leave a gap between ram/pmem (static)
> capacity and its first DC partition, or between one DC partition and
> the next.
>
> However, Linux chooses not to support gaps between static and dynamic
> capacity, and requires the first DC partition to begin at the DPA
> immediately following static capacity.
>
> Based on an original patch by Navneet Singh.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
Did you needlessly drop tags. Here's my Review again, and I think you also
dropped other folks Tested-by tags. Take a look at history.
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>
> ---
> Changes:
> 1. Partition mode renamed CXL_PARTMODE_DYNAMIC_RAM: the mode says what
> kind of capacity this is, not which partition. The DC partition's
> resource name carries its position instead, dynamic_ram_1 for the
> first, formatted in cxl_dpa_setup().
> ---
> drivers/cxl/core/hdm.c | 13 ++-
> drivers/cxl/core/mbox.c | 237 ++++++++++++++++++++++++++++++++++++++
> drivers/cxl/core/memdev.c | 47 ++++++++
> drivers/cxl/cxlmem.h | 55 +++++++++
> drivers/cxl/pci.c | 6 +
> include/cxl/cxl.h | 3 +-
> 6 files changed, 359 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 0c80b76a5f9b..5fa2177cefcc 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -446,6 +446,8 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
> return "ram";
> case CXL_PARTMODE_PMEM:
> return "pmem";
> + case CXL_PARTMODE_DYNAMIC_RAM:
> + return "dynamic_ram";
> default:
> return "";
> };
> @@ -455,6 +457,7 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
> int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> {
> struct device *dev = cxlds->dev;
> + int dc_nth = 0;
>
> guard(rwsem_write)(&cxl_rwsem.dpa);
>
> @@ -471,8 +474,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
>
> for (int i = 0; i < info->nr_partitions; i++) {
> const struct cxl_dpa_part_info *part = &info->part[i];
> + const char *name = cxl_mode_name(part->mode);
> int rc;
>
> + if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
> + name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", name,
> + ++dc_nth);
> + if (!name)
> + return -ENOMEM;
> + }
> +
> cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
> cxlds->part[i].mode = part->mode;
>
> @@ -485,7 +496,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> }
> rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->part[i].res,
> part->range.start, range_len(&part->range),
> - cxl_mode_name(part->mode));
> + name);
> if (rc)
> return rc;
> cxlds->nr_partitions++;
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index 199bb986d674..72af23ba288e 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1349,6 +1349,243 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
> return -EBUSY;
> }
>
> +/*
> + * A partition unavailable for Dynamic Capacity reports zeros for decode_length,
> + * length, and block_size.
> + */
> +static bool cxl_dc_partition_unavailable(struct cxl_dc_partition *dev_part)
> +{
> + return !le64_to_cpu(dev_part->decode_length) &&
> + !le64_to_cpu(dev_part->length) &&
> + !le64_to_cpu(dev_part->block_size);
> +}
> +
> +static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
> + struct cxl_dc_partition *dev_part)
> +{
> + u64 decode_len = le64_to_cpu(dev_part->decode_length);
> + u64 blk_size = le64_to_cpu(dev_part->block_size);
> + u64 len = le64_to_cpu(dev_part->length);
> + u64 size;
> +
> + /*
> + * Not an error; leave the entry empty. A partially zeroed partition
> + * is rejected by the checks below. CXL r4.0 Table 8-347.
> + */
> + if (cxl_dc_partition_unavailable(dev_part)) {
> + *part = (struct cxl_dc_partition_info) { };
> + dev_dbg(dev, "Partition 0 unavailable for DC\n");
> + return 0;
> + }
> +
> + /*
> + * Decode length is a count of 256M units, so a device reporting 2^36
> + * or more wraps.
> + */
> + if (check_mul_overflow(decode_len, (u64)CXL_CAPACITY_MULTIPLIER, &size)) {
> + dev_err(dev, "DC partition 0 decode length %#llx overflows\n",
> + decode_len);
> + return -EINVAL;
> + }
> +
> + *part = (struct cxl_dc_partition_info) {
> + .start = le64_to_cpu(dev_part->base),
> + .size = size,
> + };
> +
> + /*
> + * Block size is a power of 2 and a multiple of 40h. is_power_of_2()
> + * takes an unsigned long, which truncates blk_size on 32 bit.
> + */
> + if (blk_size == 0 || (blk_size & (blk_size - 1)) ||
> + blk_size % CXL_DCD_BLOCK_LINE_SIZE) {
> + dev_err(dev, "DC partition 0 invalid block size %#llx\n", blk_size);
> + return -EINVAL;
> + }
> +
> + if (part->size == 0) {
> + dev_err(dev, "DC partition 0 zero decode length\n");
> + return -EINVAL;
> + }
> +
> + if (len == 0) {
> + dev_err(dev, "DC partition 0 zero length\n");
> + return -EINVAL;
> + }
> +
> + if (len > part->size) {
> + dev_err(dev, "DC partition 0 length %#llx exceeds decode length %#llx\n",
> + len, part->size);
> + return -EINVAL;
> + }
> +
> + if (!IS_ALIGNED(len, blk_size)) {
> + dev_err(dev, "DC partition 0 length %#llx not a multiple of block size %#llx\n",
> + len, blk_size);
> + return -EINVAL;
> + }
> +
> + if (!IS_ALIGNED(part->start, SZ_256M)) {
> + dev_err(dev, "DC partition 0 base %#llx not aligned to 256M\n",
> + part->start);
> + return -EINVAL;
> + }
> +
> + dev_dbg(dev, "DC partition 0 start %#llx size %#llx blk_size: %#llx\n",
> + part->start, part->size, blk_size);
> +
> + return 0;
> +}
> +
> +/* Returns the number of partitions in dc_resp or -ERRNO */
> +static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
> + u8 partition_count,
> + struct cxl_mbox_get_dc_config_out *dc_resp,
> + size_t dc_resp_size)
> +{
> + struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
> + .partition_count = partition_count,
> + .start_partition_index = start_partition,
> + };
> + struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
> + .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
> + .payload_in = &get_dc,
> + .size_in = sizeof(get_dc),
> + .size_out = dc_resp_size,
> + .payload_out = dc_resp,
> + /* The device must return at least the fixed header */
> + .min_out = sizeof(*dc_resp),
> + };
> + size_t expected_sz;
> + int rc;
> +
> + rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
> + if (rc < 0)
> + return rc;
> +
> + if (dc_resp->partitions_returned > partition_count) {
> + dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
> + dc_resp->partitions_returned, partition_count);
> + return -EIO;
> + }
> +
> + /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
> + expected_sz = struct_size(dc_resp, partition,
> + dc_resp->partitions_returned);
> +
> + if (mbox_cmd.size_out < expected_sz) {
> + dev_err(mbox->host,
> + "Payload size %zu less than expected %zu for %u partitions\n",
> + mbox_cmd.size_out,
> + expected_sz,
> + dc_resp->partitions_returned);
> + return -EIO;
> + }
> +
> + dev_dbg(mbox->host, "Read %d/%d DC partitions\n",
> + dc_resp->partitions_returned, dc_resp->avail_partition_count);
> + return dc_resp->partitions_returned;
> +}
> +
> +/**
> + * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
> + * device.
> + * @mbox: Mailbox to query
> + * @dc_info: The dynamic partition information to return
> + *
> + * Read every partition the device reports, but validate only the first:
> + * Linux maps partition 0 and nothing else, so a defect in capacity the
> + * driver never touches is not a reason to refuse the device dynamic
> + * capacity. The remaining partitions are read but not recorded.
> + *
> + * Return: 0 if identify was executed successfully, -ERRNO on error.
> + * On error, @dc_info is left unchanged.
> + */
> +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> + struct cxl_dc_partition_info *dc_info)
> +{
> + struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
> + struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
> + struct device *dev = mbox->host;
> + u8 avail_partitions = 0;
> + u8 start_partition;
> + u8 num_partitions;
> + u8 partition_count;
> + size_t dc_resp_size;
> +
> + /*
> + * Bound requested number of partitions by mailbox payload size. The
> + * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
> + * the subtraction below from underflowing.
> + */
> + partition_count = min(CXL_MAX_DC_PARTITIONS,
> + (mbox->payload_size - sizeof(*dc_resp) -
> + sizeof(struct cxl_mbox_get_dc_config_tail)) /
> + sizeof(struct cxl_dc_partition));
> + dc_resp_size = struct_size(dc_resp, partition, partition_count) +
> + sizeof(struct cxl_mbox_get_dc_config_tail);
> +
> + dc_resp = kmalloc(dc_resp_size, GFP_KERNEL);
> + if (!dc_resp)
> + return -ENOMEM;
> +
> + start_partition = 0;
> + num_partitions = 0;
> + do {
> + int returned, rc;
> +
> + returned = cxl_get_dc_config(mbox, start_partition,
> + partition_count, dc_resp,
> + dc_resp_size);
> + if (returned < 0) {
> + dev_err(dev, "Failed to get DC config: %d\n", returned);
> + return returned;
> + }
> +
> + if (returned == 0) {
> + dev_err(dev,
> + "Device reported %u partitions available but returned none at index %u\n",
> + dc_resp->avail_partition_count, start_partition);
> + return -EIO;
> + }
> +
> + /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
> + if (dc_resp->avail_partition_count == 0) {
> + dev_err(dev, "Device reported no DC partitions\n");
> + return -EIO;
> + }
> +
> + avail_partitions = min(dc_resp->avail_partition_count,
> + CXL_MAX_DC_PARTITIONS);
> +
> + /*
> + * Only partition 0 is mapped, so it is the only one checked.
> + * The rest are read to complete the enumeration and dropped.
> + */
> + if (start_partition == 0) {
> + rc = cxl_dc_check(dev, &partitions[0],
> + &dc_resp->partition[0]);
> + if (rc)
> + return rc;
> + }
> +
> + num_partitions += returned;
> + start_partition = num_partitions;
> +
> + } while (num_partitions < avail_partitions);
> +
> + /* Linux only supports the 1st partition; nothing to do if it is unavailable */
> + if (partitions[0].size == 0)
> + return -ENODEV;
> +
> + *dc_info = partitions[0];
> + dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
> + dc_info->start, dc_info->size);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
> +
> int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
> {
> struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index b3419df586b9..def26c490dfe 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -643,6 +643,53 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
>
> +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> +{
> + struct cxl_dc_partition_info dc_info = { };
> + struct device *dev = mds->cxlds.dev;
> + u64 total;
> + int rc;
> +
> + if (!mds->cxlds.media_ready)
> + return 0;
> +
> + rc = cxl_dev_dc_identify(&mds->cxlds.cxl_mbox, &dc_info);
> + if (rc) {
> + dev_warn(dev,
> + "Failed to read Dynamic Capacity config: %d\n", rc);
> + return rc;
> + }
> +
> + if (dc_info.start < info->size) {
> + dev_err(dev,
> + "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
> + dc_info.start, info->size);
> + return -EINVAL;
> + }
> +
> + /* A gap between static capacity and the DC partition is not supported */
> + if (dc_info.start > info->size) {
> + dev_warn(dev,
> + "DC partition 0 base %#llx leaves a gap from static capacity ending at %#llx\n",
> + dc_info.start, info->size);
> + return -EOPNOTSUPP;
> + }
> +
> + if (check_add_overflow(info->size, dc_info.size, &total)) {
> + dev_err(dev,
> + "DC partition 0 size %#llx overflows DPA space ending at %#llx\n",
> + dc_info.size, info->size);
> + return -EINVAL;
> + }
> +
> + info->size = total;
> + dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
> + dc_info.start, dc_info.size);
> + add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_configure_dcd, "CXL");
>
> /**
> * cxl_set_capacity: initialize dpa by a driver without a mailbox.
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 0c8e23276dc6..4fac65dbb808 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -407,6 +407,8 @@ struct cxl_security_state {
> struct kernfs_node *sanitize_node;
> };
>
> +#define CXL_MAX_DC_PARTITIONS 8
> +
> static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
> {
> /*
> @@ -689,6 +691,39 @@ struct cxl_mbox_set_shutdown_state_in {
> u8 state;
> } __packed;
>
> +/* See CXL r4.0 Table 8-345 get dynamic capacity config Input Payload */
> +struct cxl_mbox_get_dc_config_in {
> + u8 partition_count;
> + u8 start_partition_index;
> +} __packed;
> +
> +/* See CXL r4.0 Table 8-346 get dynamic capacity config Output Payload */
> +struct cxl_mbox_get_dc_config_out {
> + u8 avail_partition_count;
> + u8 partitions_returned;
> + u8 rsvd[6];
> + /* See CXL r4.0 Table 8-347 */
> + struct cxl_dc_partition {
> + __le64 base;
> + __le64 decode_length;
> + __le64 length;
> + __le64 block_size;
> + __le32 dsmad_handle;
> + u8 flags;
> + u8 rsvd[3];
> + } __packed partition[] __counted_by(partitions_returned);
> + /* Trailing extent/tag count fields unused */
> +} __packed;
> +
> +/* Trailing counts; cannot be a member after the flex array above */
> +struct cxl_mbox_get_dc_config_tail {
> + __le32 num_extents_supported;
> + __le32 num_extents_available;
> + __le32 num_tags_supported;
> + __le32 num_tags_available;
> +} __packed;
> +#define CXL_DCD_BLOCK_LINE_SIZE 0x40
> +
> /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
> struct cxl_mbox_set_timestamp_in {
> __le64 timestamp;
> @@ -812,9 +847,18 @@ enum {
> int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
> struct cxl_mbox_cmd *cmd);
> int cxl_dev_state_identify(struct cxl_memdev_state *mds);
> +
> +struct cxl_dc_partition_info {
> + u64 start;
> + u64 size;
> +};
> +
> +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> + struct cxl_dc_partition_info *dc_info);
> int cxl_await_media_ready(struct cxl_dev_state *cxlds);
> int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
> int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
> +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
> struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> u16 dvsec);
> void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
> @@ -828,6 +872,17 @@ void cxl_event_trace_record(struct cxl_memdev *cxlmd,
> const uuid_t *uuid, union cxl_event *evt);
> int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
> int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
> +
> +static inline bool cxl_dcd_supported(struct cxl_memdev_state *mds)
> +{
> + return mds->dcd_supported;
> +}
> +
> +static inline void cxl_disable_dcd(struct cxl_memdev_state *mds)
> +{
> + mds->dcd_supported = false;
> +}
> +
> int cxl_set_timestamp(struct cxl_memdev_state *mds);
> int cxl_poison_state_init(struct cxl_memdev_state *mds);
> int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index c7c91e8dc51d..2fe9db4b3d86 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -868,6 +868,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> + if (cxl_dcd_supported(mds)) {
> + rc = cxl_configure_dcd(mds, &range_info);
> + if (rc)
> + cxl_disable_dcd(mds);
> + }
> +
> rc = cxl_dpa_setup(cxlds, &range_info);
> if (rc)
> return rc;
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 802b143de83d..e07360849344 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -133,6 +133,7 @@ struct cxl_dpa_perf {
> enum cxl_partition_mode {
> CXL_PARTMODE_RAM,
> CXL_PARTMODE_PMEM,
> + CXL_PARTMODE_DYNAMIC_RAM,
> };
>
> /**
> @@ -147,7 +148,7 @@ struct cxl_dpa_partition {
> enum cxl_partition_mode mode;
> };
>
> -#define CXL_NR_PARTITIONS_MAX 2
> +#define CXL_NR_PARTITIONS_MAX 3
>
> /**
> * struct cxl_dev_state - The driver device state
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-07 23:43 ` Alison Schofield
@ 2026-10-08 8:15 ` Anisa Su
0 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-08 8:15 UTC (permalink / raw)
To: Alison Schofield
Cc: Anisa Su, linux-cxl, nvdimm, linux-kernel, Dan Williams,
Dave Jiang, Jonathan Cameron, Davidlohr Bueso, Ira Weiny,
Vishal Verma, Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price,
Richard Cheng
On Wed, Oct 07, 2026 at 04:43:34PM -0700, Alison Schofield wrote:
> On Wed, Oct 07, 2026 at 01:16:35PM -0700, Anisa Su wrote:
> > From: Ira Weiny <iweiny@kernel.org>
> >
> > Devices which support Dynamic Capacity (DC) are configured via mailbox
> > commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
> > Configuration command in order to obtain DCD partition characteristics.
> >
> > Implement the DC mailbox commands as specified in CXL 4.0 section
> > 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
> > information. Disable DCD if an invalid configuration is found.
> >
> > Initial enablement for Linux only supports one dynamic capacity
> > partition. Read all the partitions the device reports but validate
> > only the first, and configure it as 'dynamic ram'.
> >
> > The specification requires that volatile capacity starts at DPA 0 and
> > pmem starts at the DPA immediately following it, but DC partitions only
> > need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
> > Table 8-347. So a device could leave a gap between ram/pmem (static)
> > capacity and its first DC partition, or between one DC partition and
> > the next.
> >
> > However, Linux chooses not to support gaps between static and dynamic
> > capacity, and requires the first DC partition to begin at the DPA
> > immediately following static capacity.
> >
> > Based on an original patch by Navneet Singh.
> >
> > Signed-off-by: Ira Weiny <iweiny@kernel.org>
> > Co-developed-by: Anisa Su <anisa.su@samsung.com>
> > Signed-off-by: Anisa Su <anisa.su@samsung.com>
>
>
> Did you needlessly drop tags. Here's my Review again, and I think you also
> dropped other folks Tested-by tags. Take a look at history.
>
Oh yeah I guess I should have kept them since the change is pretty trivial.
Thanks for the re-review!
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>
>
> >
> > ---
> > Changes:
> > 1. Partition mode renamed CXL_PARTMODE_DYNAMIC_RAM: the mode says what
> > kind of capacity this is, not which partition. The DC partition's
> > resource name carries its position instead, dynamic_ram_1 for the
> > first, formatted in cxl_dpa_setup().
> > ---
> > drivers/cxl/core/hdm.c | 13 ++-
> > drivers/cxl/core/mbox.c | 237 ++++++++++++++++++++++++++++++++++++++
> > drivers/cxl/core/memdev.c | 47 ++++++++
> > drivers/cxl/cxlmem.h | 55 +++++++++
> > drivers/cxl/pci.c | 6 +
> > include/cxl/cxl.h | 3 +-
> > 6 files changed, 359 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index 0c80b76a5f9b..5fa2177cefcc 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
> > @@ -446,6 +446,8 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
> > return "ram";
> > case CXL_PARTMODE_PMEM:
> > return "pmem";
> > + case CXL_PARTMODE_DYNAMIC_RAM:
> > + return "dynamic_ram";
> > default:
> > return "";
> > };
> > @@ -455,6 +457,7 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
> > int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> > {
> > struct device *dev = cxlds->dev;
> > + int dc_nth = 0;
> >
> > guard(rwsem_write)(&cxl_rwsem.dpa);
> >
> > @@ -471,8 +474,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> >
> > for (int i = 0; i < info->nr_partitions; i++) {
> > const struct cxl_dpa_part_info *part = &info->part[i];
> > + const char *name = cxl_mode_name(part->mode);
> > int rc;
> >
> > + if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
> > + name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", name,
> > + ++dc_nth);
> > + if (!name)
> > + return -ENOMEM;
> > + }
> > +
> > cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
> > cxlds->part[i].mode = part->mode;
> >
> > @@ -485,7 +496,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> > }
> > rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->part[i].res,
> > part->range.start, range_len(&part->range),
> > - cxl_mode_name(part->mode));
> > + name);
> > if (rc)
> > return rc;
> > cxlds->nr_partitions++;
> > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> > index 199bb986d674..72af23ba288e 100644
> > --- a/drivers/cxl/core/mbox.c
> > +++ b/drivers/cxl/core/mbox.c
> > @@ -1349,6 +1349,243 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
> > return -EBUSY;
> > }
> >
> > +/*
> > + * A partition unavailable for Dynamic Capacity reports zeros for decode_length,
> > + * length, and block_size.
> > + */
> > +static bool cxl_dc_partition_unavailable(struct cxl_dc_partition *dev_part)
> > +{
> > + return !le64_to_cpu(dev_part->decode_length) &&
> > + !le64_to_cpu(dev_part->length) &&
> > + !le64_to_cpu(dev_part->block_size);
> > +}
> > +
> > +static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
> > + struct cxl_dc_partition *dev_part)
> > +{
> > + u64 decode_len = le64_to_cpu(dev_part->decode_length);
> > + u64 blk_size = le64_to_cpu(dev_part->block_size);
> > + u64 len = le64_to_cpu(dev_part->length);
> > + u64 size;
> > +
> > + /*
> > + * Not an error; leave the entry empty. A partially zeroed partition
> > + * is rejected by the checks below. CXL r4.0 Table 8-347.
> > + */
> > + if (cxl_dc_partition_unavailable(dev_part)) {
> > + *part = (struct cxl_dc_partition_info) { };
> > + dev_dbg(dev, "Partition 0 unavailable for DC\n");
> > + return 0;
> > + }
> > +
> > + /*
> > + * Decode length is a count of 256M units, so a device reporting 2^36
> > + * or more wraps.
> > + */
> > + if (check_mul_overflow(decode_len, (u64)CXL_CAPACITY_MULTIPLIER, &size)) {
> > + dev_err(dev, "DC partition 0 decode length %#llx overflows\n",
> > + decode_len);
> > + return -EINVAL;
> > + }
> > +
> > + *part = (struct cxl_dc_partition_info) {
> > + .start = le64_to_cpu(dev_part->base),
> > + .size = size,
> > + };
> > +
> > + /*
> > + * Block size is a power of 2 and a multiple of 40h. is_power_of_2()
> > + * takes an unsigned long, which truncates blk_size on 32 bit.
> > + */
> > + if (blk_size == 0 || (blk_size & (blk_size - 1)) ||
> > + blk_size % CXL_DCD_BLOCK_LINE_SIZE) {
> > + dev_err(dev, "DC partition 0 invalid block size %#llx\n", blk_size);
> > + return -EINVAL;
> > + }
> > +
> > + if (part->size == 0) {
> > + dev_err(dev, "DC partition 0 zero decode length\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (len == 0) {
> > + dev_err(dev, "DC partition 0 zero length\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (len > part->size) {
> > + dev_err(dev, "DC partition 0 length %#llx exceeds decode length %#llx\n",
> > + len, part->size);
> > + return -EINVAL;
> > + }
> > +
> > + if (!IS_ALIGNED(len, blk_size)) {
> > + dev_err(dev, "DC partition 0 length %#llx not a multiple of block size %#llx\n",
> > + len, blk_size);
> > + return -EINVAL;
> > + }
> > +
> > + if (!IS_ALIGNED(part->start, SZ_256M)) {
> > + dev_err(dev, "DC partition 0 base %#llx not aligned to 256M\n",
> > + part->start);
> > + return -EINVAL;
> > + }
> > +
> > + dev_dbg(dev, "DC partition 0 start %#llx size %#llx blk_size: %#llx\n",
> > + part->start, part->size, blk_size);
> > +
> > + return 0;
> > +}
> > +
> > +/* Returns the number of partitions in dc_resp or -ERRNO */
> > +static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
> > + u8 partition_count,
> > + struct cxl_mbox_get_dc_config_out *dc_resp,
> > + size_t dc_resp_size)
> > +{
> > + struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
> > + .partition_count = partition_count,
> > + .start_partition_index = start_partition,
> > + };
> > + struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
> > + .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
> > + .payload_in = &get_dc,
> > + .size_in = sizeof(get_dc),
> > + .size_out = dc_resp_size,
> > + .payload_out = dc_resp,
> > + /* The device must return at least the fixed header */
> > + .min_out = sizeof(*dc_resp),
> > + };
> > + size_t expected_sz;
> > + int rc;
> > +
> > + rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
> > + if (rc < 0)
> > + return rc;
> > +
> > + if (dc_resp->partitions_returned > partition_count) {
> > + dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
> > + dc_resp->partitions_returned, partition_count);
> > + return -EIO;
> > + }
> > +
> > + /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
> > + expected_sz = struct_size(dc_resp, partition,
> > + dc_resp->partitions_returned);
> > +
> > + if (mbox_cmd.size_out < expected_sz) {
> > + dev_err(mbox->host,
> > + "Payload size %zu less than expected %zu for %u partitions\n",
> > + mbox_cmd.size_out,
> > + expected_sz,
> > + dc_resp->partitions_returned);
> > + return -EIO;
> > + }
> > +
> > + dev_dbg(mbox->host, "Read %d/%d DC partitions\n",
> > + dc_resp->partitions_returned, dc_resp->avail_partition_count);
> > + return dc_resp->partitions_returned;
> > +}
> > +
> > +/**
> > + * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
> > + * device.
> > + * @mbox: Mailbox to query
> > + * @dc_info: The dynamic partition information to return
> > + *
> > + * Read every partition the device reports, but validate only the first:
> > + * Linux maps partition 0 and nothing else, so a defect in capacity the
> > + * driver never touches is not a reason to refuse the device dynamic
> > + * capacity. The remaining partitions are read but not recorded.
> > + *
> > + * Return: 0 if identify was executed successfully, -ERRNO on error.
> > + * On error, @dc_info is left unchanged.
> > + */
> > +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> > + struct cxl_dc_partition_info *dc_info)
> > +{
> > + struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
> > + struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
> > + struct device *dev = mbox->host;
> > + u8 avail_partitions = 0;
> > + u8 start_partition;
> > + u8 num_partitions;
> > + u8 partition_count;
> > + size_t dc_resp_size;
> > +
> > + /*
> > + * Bound requested number of partitions by mailbox payload size. The
> > + * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
> > + * the subtraction below from underflowing.
> > + */
> > + partition_count = min(CXL_MAX_DC_PARTITIONS,
> > + (mbox->payload_size - sizeof(*dc_resp) -
> > + sizeof(struct cxl_mbox_get_dc_config_tail)) /
> > + sizeof(struct cxl_dc_partition));
> > + dc_resp_size = struct_size(dc_resp, partition, partition_count) +
> > + sizeof(struct cxl_mbox_get_dc_config_tail);
> > +
> > + dc_resp = kmalloc(dc_resp_size, GFP_KERNEL);
> > + if (!dc_resp)
> > + return -ENOMEM;
> > +
> > + start_partition = 0;
> > + num_partitions = 0;
> > + do {
> > + int returned, rc;
> > +
> > + returned = cxl_get_dc_config(mbox, start_partition,
> > + partition_count, dc_resp,
> > + dc_resp_size);
> > + if (returned < 0) {
> > + dev_err(dev, "Failed to get DC config: %d\n", returned);
> > + return returned;
> > + }
> > +
> > + if (returned == 0) {
> > + dev_err(dev,
> > + "Device reported %u partitions available but returned none at index %u\n",
> > + dc_resp->avail_partition_count, start_partition);
> > + return -EIO;
> > + }
> > +
> > + /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
> > + if (dc_resp->avail_partition_count == 0) {
> > + dev_err(dev, "Device reported no DC partitions\n");
> > + return -EIO;
> > + }
> > +
> > + avail_partitions = min(dc_resp->avail_partition_count,
> > + CXL_MAX_DC_PARTITIONS);
> > +
> > + /*
> > + * Only partition 0 is mapped, so it is the only one checked.
> > + * The rest are read to complete the enumeration and dropped.
> > + */
> > + if (start_partition == 0) {
> > + rc = cxl_dc_check(dev, &partitions[0],
> > + &dc_resp->partition[0]);
> > + if (rc)
> > + return rc;
> > + }
> > +
> > + num_partitions += returned;
> > + start_partition = num_partitions;
> > +
> > + } while (num_partitions < avail_partitions);
> > +
> > + /* Linux only supports the 1st partition; nothing to do if it is unavailable */
> > + if (partitions[0].size == 0)
> > + return -ENODEV;
> > +
> > + *dc_info = partitions[0];
> > + dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
> > + dc_info->start, dc_info->size);
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
> > +
> > int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
> > {
> > struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> > index b3419df586b9..def26c490dfe 100644
> > --- a/drivers/cxl/core/memdev.c
> > +++ b/drivers/cxl/core/memdev.c
> > @@ -643,6 +643,53 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> > }
> > EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
> >
> > +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> > +{
> > + struct cxl_dc_partition_info dc_info = { };
> > + struct device *dev = mds->cxlds.dev;
> > + u64 total;
> > + int rc;
> > +
> > + if (!mds->cxlds.media_ready)
> > + return 0;
> > +
> > + rc = cxl_dev_dc_identify(&mds->cxlds.cxl_mbox, &dc_info);
> > + if (rc) {
> > + dev_warn(dev,
> > + "Failed to read Dynamic Capacity config: %d\n", rc);
> > + return rc;
> > + }
> > +
> > + if (dc_info.start < info->size) {
> > + dev_err(dev,
> > + "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
> > + dc_info.start, info->size);
> > + return -EINVAL;
> > + }
> > +
> > + /* A gap between static capacity and the DC partition is not supported */
> > + if (dc_info.start > info->size) {
> > + dev_warn(dev,
> > + "DC partition 0 base %#llx leaves a gap from static capacity ending at %#llx\n",
> > + dc_info.start, info->size);
> > + return -EOPNOTSUPP;
> > + }
> > +
> > + if (check_add_overflow(info->size, dc_info.size, &total)) {
> > + dev_err(dev,
> > + "DC partition 0 size %#llx overflows DPA space ending at %#llx\n",
> > + dc_info.size, info->size);
> > + return -EINVAL;
> > + }
> > +
> > + info->size = total;
> > + dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
> > + dc_info.start, dc_info.size);
> > + add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_NS_GPL(cxl_configure_dcd, "CXL");
> >
> > /**
> > * cxl_set_capacity: initialize dpa by a driver without a mailbox.
> > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> > index 0c8e23276dc6..4fac65dbb808 100644
> > --- a/drivers/cxl/cxlmem.h
> > +++ b/drivers/cxl/cxlmem.h
> > @@ -407,6 +407,8 @@ struct cxl_security_state {
> > struct kernfs_node *sanitize_node;
> > };
> >
> > +#define CXL_MAX_DC_PARTITIONS 8
> > +
> > static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
> > {
> > /*
> > @@ -689,6 +691,39 @@ struct cxl_mbox_set_shutdown_state_in {
> > u8 state;
> > } __packed;
> >
> > +/* See CXL r4.0 Table 8-345 get dynamic capacity config Input Payload */
> > +struct cxl_mbox_get_dc_config_in {
> > + u8 partition_count;
> > + u8 start_partition_index;
> > +} __packed;
> > +
> > +/* See CXL r4.0 Table 8-346 get dynamic capacity config Output Payload */
> > +struct cxl_mbox_get_dc_config_out {
> > + u8 avail_partition_count;
> > + u8 partitions_returned;
> > + u8 rsvd[6];
> > + /* See CXL r4.0 Table 8-347 */
> > + struct cxl_dc_partition {
> > + __le64 base;
> > + __le64 decode_length;
> > + __le64 length;
> > + __le64 block_size;
> > + __le32 dsmad_handle;
> > + u8 flags;
> > + u8 rsvd[3];
> > + } __packed partition[] __counted_by(partitions_returned);
> > + /* Trailing extent/tag count fields unused */
> > +} __packed;
> > +
> > +/* Trailing counts; cannot be a member after the flex array above */
> > +struct cxl_mbox_get_dc_config_tail {
> > + __le32 num_extents_supported;
> > + __le32 num_extents_available;
> > + __le32 num_tags_supported;
> > + __le32 num_tags_available;
> > +} __packed;
> > +#define CXL_DCD_BLOCK_LINE_SIZE 0x40
> > +
> > /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
> > struct cxl_mbox_set_timestamp_in {
> > __le64 timestamp;
> > @@ -812,9 +847,18 @@ enum {
> > int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
> > struct cxl_mbox_cmd *cmd);
> > int cxl_dev_state_identify(struct cxl_memdev_state *mds);
> > +
> > +struct cxl_dc_partition_info {
> > + u64 start;
> > + u64 size;
> > +};
> > +
> > +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> > + struct cxl_dc_partition_info *dc_info);
> > int cxl_await_media_ready(struct cxl_dev_state *cxlds);
> > int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
> > int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
> > +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
> > struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> > u16 dvsec);
> > void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
> > @@ -828,6 +872,17 @@ void cxl_event_trace_record(struct cxl_memdev *cxlmd,
> > const uuid_t *uuid, union cxl_event *evt);
> > int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
> > int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
> > +
> > +static inline bool cxl_dcd_supported(struct cxl_memdev_state *mds)
> > +{
> > + return mds->dcd_supported;
> > +}
> > +
> > +static inline void cxl_disable_dcd(struct cxl_memdev_state *mds)
> > +{
> > + mds->dcd_supported = false;
> > +}
> > +
> > int cxl_set_timestamp(struct cxl_memdev_state *mds);
> > int cxl_poison_state_init(struct cxl_memdev_state *mds);
> > int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index c7c91e8dc51d..2fe9db4b3d86 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -868,6 +868,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> > if (rc)
> > return rc;
> >
> > + if (cxl_dcd_supported(mds)) {
> > + rc = cxl_configure_dcd(mds, &range_info);
> > + if (rc)
> > + cxl_disable_dcd(mds);
> > + }
> > +
> > rc = cxl_dpa_setup(cxlds, &range_info);
> > if (rc)
> > return rc;
> > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> > index 802b143de83d..e07360849344 100644
> > --- a/include/cxl/cxl.h
> > +++ b/include/cxl/cxl.h
> > @@ -133,6 +133,7 @@ struct cxl_dpa_perf {
> > enum cxl_partition_mode {
> > CXL_PARTMODE_RAM,
> > CXL_PARTMODE_PMEM,
> > + CXL_PARTMODE_DYNAMIC_RAM,
> > };
> >
> > /**
> > @@ -147,7 +148,7 @@ struct cxl_dpa_partition {
> > enum cxl_partition_mode mode;
> > };
> >
> > -#define CXL_NR_PARTITIONS_MAX 2
> > +#define CXL_NR_PARTITIONS_MAX 3
> >
> > /**
> > * struct cxl_dev_state - The driver device state
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-07 20:16 ` [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-10-07 20:29 ` sashiko-bot
2026-10-07 23:43 ` Alison Schofield
@ 2026-10-08 8:33 ` Richard Cheng
2 siblings, 0 replies; 20+ messages in thread
From: Richard Cheng @ 2026-10-08 8:33 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dan Williams, Dave Jiang,
Alison Schofield, Jonathan Cameron, Davidlohr Bueso, Ira Weiny,
Vishal Verma, Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price,
Anisa Su
On Wed, Oct 07, 2026 at 01:16:35PM +0800, Anisa Su wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Devices which support Dynamic Capacity (DC) are configured via mailbox
> commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
> Configuration command in order to obtain DCD partition characteristics.
>
> Implement the DC mailbox commands as specified in CXL 4.0 section
> 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
> information. Disable DCD if an invalid configuration is found.
>
> Initial enablement for Linux only supports one dynamic capacity
> partition. Read all the partitions the device reports but validate
> only the first, and configure it as 'dynamic ram'.
>
> The specification requires that volatile capacity starts at DPA 0 and
> pmem starts at the DPA immediately following it, but DC partitions only
> need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
> Table 8-347. So a device could leave a gap between ram/pmem (static)
> capacity and its first DC partition, or between one DC partition and
> the next.
>
> However, Linux chooses not to support gaps between static and dynamic
> capacity, and requires the first DC partition to begin at the DPA
> immediately following static capacity.
>
> Based on an original patch by Navneet Singh.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
>
> ---
> Changes:
> 1. Partition mode renamed CXL_PARTMODE_DYNAMIC_RAM: the mode says what
> kind of capacity this is, not which partition. The DC partition's
> resource name carries its position instead, dynamic_ram_1 for the
> first, formatted in cxl_dpa_setup().
> ---
> drivers/cxl/core/hdm.c | 13 ++-
> drivers/cxl/core/mbox.c | 237 ++++++++++++++++++++++++++++++++++++++
> drivers/cxl/core/memdev.c | 47 ++++++++
> drivers/cxl/cxlmem.h | 55 +++++++++
> drivers/cxl/pci.c | 6 +
> include/cxl/cxl.h | 3 +-
> 6 files changed, 359 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 0c80b76a5f9b..5fa2177cefcc 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -446,6 +446,8 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
> return "ram";
> case CXL_PARTMODE_PMEM:
> return "pmem";
> + case CXL_PARTMODE_DYNAMIC_RAM:
> + return "dynamic_ram";
> default:
> return "";
> };
> @@ -455,6 +457,7 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
> int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> {
> struct device *dev = cxlds->dev;
> + int dc_nth = 0;
>
> guard(rwsem_write)(&cxl_rwsem.dpa);
>
> @@ -471,8 +474,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
>
> for (int i = 0; i < info->nr_partitions; i++) {
> const struct cxl_dpa_part_info *part = &info->part[i];
> + const char *name = cxl_mode_name(part->mode);
> int rc;
>
> + if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
> + name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", name,
> + ++dc_nth);
> + if (!name)
> + return -ENOMEM;
> + }
> +
> cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
> cxlds->part[i].mode = part->mode;
>
> @@ -485,7 +496,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
> }
> rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->part[i].res,
> part->range.start, range_len(&part->range),
> - cxl_mode_name(part->mode));
> + name);
> if (rc)
> return rc;
> cxlds->nr_partitions++;
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index 199bb986d674..72af23ba288e 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1349,6 +1349,243 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
> return -EBUSY;
> }
>
> +/*
> + * A partition unavailable for Dynamic Capacity reports zeros for decode_length,
> + * length, and block_size.
> + */
> +static bool cxl_dc_partition_unavailable(struct cxl_dc_partition *dev_part)
> +{
> + return !le64_to_cpu(dev_part->decode_length) &&
> + !le64_to_cpu(dev_part->length) &&
> + !le64_to_cpu(dev_part->block_size);
> +}
> +
> +static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
> + struct cxl_dc_partition *dev_part)
> +{
> + u64 decode_len = le64_to_cpu(dev_part->decode_length);
> + u64 blk_size = le64_to_cpu(dev_part->block_size);
> + u64 len = le64_to_cpu(dev_part->length);
> + u64 size;
> +
> + /*
> + * Not an error; leave the entry empty. A partially zeroed partition
> + * is rejected by the checks below. CXL r4.0 Table 8-347.
> + */
> + if (cxl_dc_partition_unavailable(dev_part)) {
> + *part = (struct cxl_dc_partition_info) { };
> + dev_dbg(dev, "Partition 0 unavailable for DC\n");
> + return 0;
> + }
> +
> + /*
> + * Decode length is a count of 256M units, so a device reporting 2^36
> + * or more wraps.
> + */
> + if (check_mul_overflow(decode_len, (u64)CXL_CAPACITY_MULTIPLIER, &size)) {
> + dev_err(dev, "DC partition 0 decode length %#llx overflows\n",
> + decode_len);
> + return -EINVAL;
> + }
> +
> + *part = (struct cxl_dc_partition_info) {
> + .start = le64_to_cpu(dev_part->base),
> + .size = size,
> + };
> +
> + /*
> + * Block size is a power of 2 and a multiple of 40h. is_power_of_2()
> + * takes an unsigned long, which truncates blk_size on 32 bit.
> + */
> + if (blk_size == 0 || (blk_size & (blk_size - 1)) ||
> + blk_size % CXL_DCD_BLOCK_LINE_SIZE) {
> + dev_err(dev, "DC partition 0 invalid block size %#llx\n", blk_size);
> + return -EINVAL;
> + }
> +
> + if (part->size == 0) {
> + dev_err(dev, "DC partition 0 zero decode length\n");
> + return -EINVAL;
> + }
> +
> + if (len == 0) {
> + dev_err(dev, "DC partition 0 zero length\n");
> + return -EINVAL;
> + }
> +
> + if (len > part->size) {
> + dev_err(dev, "DC partition 0 length %#llx exceeds decode length %#llx\n",
> + len, part->size);
> + return -EINVAL;
> + }
> +
> + if (!IS_ALIGNED(len, blk_size)) {
> + dev_err(dev, "DC partition 0 length %#llx not a multiple of block size %#llx\n",
> + len, blk_size);
> + return -EINVAL;
> + }
> +
> + if (!IS_ALIGNED(part->start, SZ_256M)) {
> + dev_err(dev, "DC partition 0 base %#llx not aligned to 256M\n",
> + part->start);
> + return -EINVAL;
> + }
> +
> + dev_dbg(dev, "DC partition 0 start %#llx size %#llx blk_size: %#llx\n",
> + part->start, part->size, blk_size);
> +
> + return 0;
> +}
> +
> +/* Returns the number of partitions in dc_resp or -ERRNO */
> +static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
> + u8 partition_count,
> + struct cxl_mbox_get_dc_config_out *dc_resp,
> + size_t dc_resp_size)
> +{
> + struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
> + .partition_count = partition_count,
> + .start_partition_index = start_partition,
> + };
> + struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
> + .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
> + .payload_in = &get_dc,
> + .size_in = sizeof(get_dc),
> + .size_out = dc_resp_size,
> + .payload_out = dc_resp,
> + /* The device must return at least the fixed header */
> + .min_out = sizeof(*dc_resp),
> + };
> + size_t expected_sz;
> + int rc;
> +
> + rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
> + if (rc < 0)
> + return rc;
> +
> + if (dc_resp->partitions_returned > partition_count) {
> + dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
> + dc_resp->partitions_returned, partition_count);
> + return -EIO;
> + }
> +
> + /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
> + expected_sz = struct_size(dc_resp, partition,
> + dc_resp->partitions_returned);
> +
> + if (mbox_cmd.size_out < expected_sz) {
> + dev_err(mbox->host,
> + "Payload size %zu less than expected %zu for %u partitions\n",
> + mbox_cmd.size_out,
> + expected_sz,
> + dc_resp->partitions_returned);
> + return -EIO;
> + }
> +
> + dev_dbg(mbox->host, "Read %d/%d DC partitions\n",
> + dc_resp->partitions_returned, dc_resp->avail_partition_count);
> + return dc_resp->partitions_returned;
> +}
> +
> +/**
> + * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
> + * device.
> + * @mbox: Mailbox to query
> + * @dc_info: The dynamic partition information to return
> + *
> + * Read every partition the device reports, but validate only the first:
> + * Linux maps partition 0 and nothing else, so a defect in capacity the
> + * driver never touches is not a reason to refuse the device dynamic
> + * capacity. The remaining partitions are read but not recorded.
> + *
> + * Return: 0 if identify was executed successfully, -ERRNO on error.
> + * On error, @dc_info is left unchanged.
> + */
> +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> + struct cxl_dc_partition_info *dc_info)
> +{
> + struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
> + struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
> + struct device *dev = mbox->host;
> + u8 avail_partitions = 0;
> + u8 start_partition;
> + u8 num_partitions;
> + u8 partition_count;
> + size_t dc_resp_size;
> +
> + /*
> + * Bound requested number of partitions by mailbox payload size. The
> + * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
> + * the subtraction below from underflowing.
> + */
> + partition_count = min(CXL_MAX_DC_PARTITIONS,
> + (mbox->payload_size - sizeof(*dc_resp) -
> + sizeof(struct cxl_mbox_get_dc_config_tail)) /
> + sizeof(struct cxl_dc_partition));
> + dc_resp_size = struct_size(dc_resp, partition, partition_count) +
> + sizeof(struct cxl_mbox_get_dc_config_tail);
> +
> + dc_resp = kmalloc(dc_resp_size, GFP_KERNEL);
> + if (!dc_resp)
> + return -ENOMEM;
> +
> + start_partition = 0;
> + num_partitions = 0;
> + do {
> + int returned, rc;
> +
> + returned = cxl_get_dc_config(mbox, start_partition,
> + partition_count, dc_resp,
> + dc_resp_size);
> + if (returned < 0) {
> + dev_err(dev, "Failed to get DC config: %d\n", returned);
> + return returned;
> + }
> +
> + if (returned == 0) {
> + dev_err(dev,
> + "Device reported %u partitions available but returned none at index %u\n",
> + dc_resp->avail_partition_count, start_partition);
> + return -EIO;
> + }
> +
> + /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
> + if (dc_resp->avail_partition_count == 0) {
> + dev_err(dev, "Device reported no DC partitions\n");
> + return -EIO;
> + }
> +
> + avail_partitions = min(dc_resp->avail_partition_count,
> + CXL_MAX_DC_PARTITIONS);
> +
> + /*
> + * Only partition 0 is mapped, so it is the only one checked.
> + * The rest are read to complete the enumeration and dropped.
> + */
> + if (start_partition == 0) {
> + rc = cxl_dc_check(dev, &partitions[0],
> + &dc_resp->partition[0]);
> + if (rc)
> + return rc;
> + }
> +
> + num_partitions += returned;
> + start_partition = num_partitions;
> +
> + } while (num_partitions < avail_partitions);
> +
> + /* Linux only supports the 1st partition; nothing to do if it is unavailable */
> + if (partitions[0].size == 0)
> + return -ENODEV;
> +
> + *dc_info = partitions[0];
> + dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
> + dc_info->start, dc_info->size);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
> +
> int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
> {
> struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index b3419df586b9..def26c490dfe 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -643,6 +643,53 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
>
> +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
> +{
> + struct cxl_dc_partition_info dc_info = { };
> + struct device *dev = mds->cxlds.dev;
> + u64 total;
> + int rc;
> +
> + if (!mds->cxlds.media_ready)
> + return 0;
> +
> + rc = cxl_dev_dc_identify(&mds->cxlds.cxl_mbox, &dc_info);
> + if (rc) {
> + dev_warn(dev,
> + "Failed to read Dynamic Capacity config: %d\n", rc);
> + return rc;
> + }
> +
> + if (dc_info.start < info->size) {
> + dev_err(dev,
> + "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
> + dc_info.start, info->size);
> + return -EINVAL;
> + }
> +
> + /* A gap between static capacity and the DC partition is not supported */
> + if (dc_info.start > info->size) {
> + dev_warn(dev,
> + "DC partition 0 base %#llx leaves a gap from static capacity ending at %#llx\n",
> + dc_info.start, info->size);
> + return -EOPNOTSUPP;
> + }
> +
> + if (check_add_overflow(info->size, dc_info.size, &total)) {
> + dev_err(dev,
> + "DC partition 0 size %#llx overflows DPA space ending at %#llx\n",
> + dc_info.size, info->size);
> + return -EINVAL;
> + }
> +
> + info->size = total;
> + dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
> + dc_info.start, dc_info.size);
> + add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_configure_dcd, "CXL");
>
Hi Anisa,
This function uses info->size, which is Total Capacity, as the end of static
capacity, but now we require DC partition to start at the end of the last
static partition, which is RAM + PMEM. CXL r4.0 8.2.10.9.1.1 "Identify Memory
Device" only requires Total Capacity to be >= the sum of RAM + PMEM.
If they differ and device place DCD region base at Total, we can pass the check
here but cxl_dpa_setup() fails probe with -EINVAL, so a DCD config
quirk costs the whole memdev instead of just DCD.
Think of an example, Total capacity 12G, RAM has 8G, PMEM has 2G, now if
DC starts at 12G, this function check will be passed, but cxl_dpa_setup()
will see PMEM end at 10G, DC start at 12G, think of it as a hole.
If the DC start at 10G, we can pass cxl_dpa_setup(), but the test here will see
10G < 12 G and think DC region start inside the device memory and print
"overlaps"
Maybe derive the static end from info->part[nr_partitions - 1] and size
info->size from DC partition end ?
Best regards,
Richard Cheng.
> /**
> * cxl_set_capacity: initialize dpa by a driver without a mailbox.
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 0c8e23276dc6..4fac65dbb808 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -407,6 +407,8 @@ struct cxl_security_state {
> struct kernfs_node *sanitize_node;
> };
>
> +#define CXL_MAX_DC_PARTITIONS 8
> +
> static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
> {
> /*
> @@ -689,6 +691,39 @@ struct cxl_mbox_set_shutdown_state_in {
> u8 state;
> } __packed;
>
> +/* See CXL r4.0 Table 8-345 get dynamic capacity config Input Payload */
> +struct cxl_mbox_get_dc_config_in {
> + u8 partition_count;
> + u8 start_partition_index;
> +} __packed;
> +
> +/* See CXL r4.0 Table 8-346 get dynamic capacity config Output Payload */
> +struct cxl_mbox_get_dc_config_out {
> + u8 avail_partition_count;
> + u8 partitions_returned;
> + u8 rsvd[6];
> + /* See CXL r4.0 Table 8-347 */
> + struct cxl_dc_partition {
> + __le64 base;
> + __le64 decode_length;
> + __le64 length;
> + __le64 block_size;
> + __le32 dsmad_handle;
> + u8 flags;
> + u8 rsvd[3];
> + } __packed partition[] __counted_by(partitions_returned);
> + /* Trailing extent/tag count fields unused */
> +} __packed;
> +
> +/* Trailing counts; cannot be a member after the flex array above */
> +struct cxl_mbox_get_dc_config_tail {
> + __le32 num_extents_supported;
> + __le32 num_extents_available;
> + __le32 num_tags_supported;
> + __le32 num_tags_available;
> +} __packed;
> +#define CXL_DCD_BLOCK_LINE_SIZE 0x40
> +
> /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
> struct cxl_mbox_set_timestamp_in {
> __le64 timestamp;
> @@ -812,9 +847,18 @@ enum {
> int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
> struct cxl_mbox_cmd *cmd);
> int cxl_dev_state_identify(struct cxl_memdev_state *mds);
> +
> +struct cxl_dc_partition_info {
> + u64 start;
> + u64 size;
> +};
> +
> +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> + struct cxl_dc_partition_info *dc_info);
> int cxl_await_media_ready(struct cxl_dev_state *cxlds);
> int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
> int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
> +int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
> struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> u16 dvsec);
> void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
> @@ -828,6 +872,17 @@ void cxl_event_trace_record(struct cxl_memdev *cxlmd,
> const uuid_t *uuid, union cxl_event *evt);
> int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
> int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
> +
> +static inline bool cxl_dcd_supported(struct cxl_memdev_state *mds)
> +{
> + return mds->dcd_supported;
> +}
> +
> +static inline void cxl_disable_dcd(struct cxl_memdev_state *mds)
> +{
> + mds->dcd_supported = false;
> +}
> +
> int cxl_set_timestamp(struct cxl_memdev_state *mds);
> int cxl_poison_state_init(struct cxl_memdev_state *mds);
> int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index c7c91e8dc51d..2fe9db4b3d86 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -868,6 +868,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> + if (cxl_dcd_supported(mds)) {
> + rc = cxl_configure_dcd(mds, &range_info);
> + if (rc)
> + cxl_disable_dcd(mds);
> + }
> +
> rc = cxl_dpa_setup(cxlds, &range_info);
> if (rc)
> return rc;
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 802b143de83d..e07360849344 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -133,6 +133,7 @@ struct cxl_dpa_perf {
> enum cxl_partition_mode {
> CXL_PARTMODE_RAM,
> CXL_PARTMODE_PMEM,
> + CXL_PARTMODE_DYNAMIC_RAM,
> };
>
> /**
> @@ -147,7 +148,7 @@ struct cxl_dpa_partition {
> enum cxl_partition_mode mode;
> };
>
> -#define CXL_NR_PARTITIONS_MAX 2
> +#define CXL_NR_PARTITIONS_MAX 3
>
> /**
> * struct cxl_dev_state - The driver device state
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
2026-10-07 20:16 ` [PATCH v15 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
2026-10-07 20:16 ` [PATCH v15 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:33 ` sashiko-bot
2026-10-07 23:45 ` Alison Schofield
2026-10-07 20:16 ` [PATCH v15 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
` (5 subsequent siblings)
8 siblings, 2 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Additional DCD partition (AKA region) information is contained in the
DSMAS CDAT tables, including performance, shareable and read-only
attributes.
Match DCD partitions with DSMAS tables and store the meta data. A DCD
shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3), so
if the CDAT is absent, fails to parse, or has no entry matching the DC
partition, disable DCD rather than run with unknown attributes.
DSLBIS is optional, but cxl_cdat_endpoint_process() treated zero DSLBIS
entries as a parse failure, which would now disable DCD on a device with
a valid DSMAS. Accept an empty DSLBIS, and skip DSMAS entries with no
DSLBIS coordinates.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
---
Changes:
1. cdat.c: disable DCD when the DC partition has no valid DSMAS entry:
no CDAT, CDAT parse failure, or no entry matching the partition.
[Richard, Dave]
2. cdat.c: DSLBIS is optional. An empty DSLBIS no longer fails the
CDAT parse, and cxl_port_perf_data_calculate() skips entries that
have no DSLBIS coordinates.
[Richard, Dave]
3. cdat.c: cxl_memdev_apply_dsmas() takes an enum cxl_dsmas_apply
instead of a bool so the call sites say what is applied.
[Dave]
4. Also record the DSMAS read-only flag (CDAT 1.04, Flags bit 6) on
the partition, alongside shareable.
[Jonathan]
---
drivers/cxl/core/cdat.c | 97 ++++++++++++++++++++++++++++++++++-----
drivers/cxl/core/hdm.c | 1 +
drivers/cxl/core/mbox.c | 9 ++++
drivers/cxl/core/memdev.c | 17 ++++---
drivers/cxl/cxlmem.h | 2 +
include/cxl/cxl.h | 6 +++
6 files changed, 113 insertions(+), 19 deletions(-)
diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
index 5c9f07262513..07aedff657d9 100644
--- a/drivers/cxl/core/cdat.c
+++ b/drivers/cxl/core/cdat.c
@@ -17,6 +17,8 @@ struct dsmas_entry {
struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
int entries;
int qos_class;
+ bool shareable;
+ bool read_only;
};
static u32 cdat_normalize(u16 entry, u64 base, u8 type)
@@ -74,6 +76,10 @@ static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg,
return -ENOMEM;
dent->handle = dsmas->dsmad_handle;
+ /* Shareable is CDAT 1.03 and later, DSMAS Flags bit 3 */
+ dent->shareable = dsmas->flags & ACPI_CDAT_DSMAS_SHAREABLE;
+ /* Read Only is CDAT 1.04 and later, DSMAS Flags bit 6 */
+ dent->read_only = dsmas->flags & ACPI_CDAT_DSMAS_READ_ONLY;
dent->dpa_range.start = le64_to_cpu((__force __le64)dsmas->dpa_base_address);
dent->dpa_range.end = le64_to_cpu((__force __le64)dsmas->dpa_base_address) +
le64_to_cpu((__force __le64)dsmas->dpa_length) - 1;
@@ -188,9 +194,10 @@ static int cxl_cdat_endpoint_process(struct cxl_port *port,
if (rc)
return rc;
+ /* DSLBIS is optional; zero entries is not an error */
rc = cdat_table_parse(ACPI_CDAT_TYPE_DSLBIS, cdat_dslbis_handler,
dsmas_xa, port->cdat.table, port->cdat.length);
- return cdat_table_parse_output(rc);
+ return rc < 0 ? rc : 0;
}
static int cxl_port_perf_data_calculate(struct cxl_port *port,
@@ -219,6 +226,13 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
xa_for_each(dsmas_xa, index, dent) {
int qos_class;
+ /* No DSLBIS for this DSMAS; nothing to hand the QTG _DSM */
+ if (!dent->cdat_coord[ACCESS_COORDINATE_CPU].read_bandwidth &&
+ !dent->cdat_coord[ACCESS_COORDINATE_CPU].write_bandwidth &&
+ !dent->cdat_coord[ACCESS_COORDINATE_CPU].read_latency &&
+ !dent->cdat_coord[ACCESS_COORDINATE_CPU].write_latency)
+ continue;
+
cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c);
dent->entries = 1;
rc = cxl_root->ops.qos_class(cxl_root,
@@ -255,35 +269,90 @@ static void update_perf_entry(struct device *dev, struct dsmas_entry *dent,
dent->coord[ACCESS_COORDINATE_CPU].write_latency);
}
-static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,
- struct xarray *dsmas_xa)
+/*
+ * A DCD shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3).
+ * Without one the partition's attributes are unknown, so disable DCD.
+ */
+static void cxl_dcd_dsmas_missing(struct cxl_dev_state *cxlds, const char *why)
+{
+ struct cxl_memdev_state *mds;
+
+ if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
+ return;
+
+ mds = to_cxl_memdev_state(cxlds);
+ if (!cxl_dcd_supported(mds) ||
+ !cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM))
+ return;
+
+ dev_warn(cxlds->dev, "DC partition has no valid DSMAS entry (%s), disabling DCD\n",
+ why);
+ cxl_disable_dcd(mds);
+}
+
+enum cxl_dsmas_apply {
+ CXL_DSMAS_APPLY_FLAGS, /* shareable etc.; no QTG data */
+ CXL_DSMAS_APPLY_FLAGS_PERF, /* perf coordinates and qos_class */
+};
+
+/*
+ * DSMAS flags such as shareable are properties of the CDAT entry and are
+ * applied regardless; perf data is applied only if the QTG lookup produced
+ * recommendations.
+ */
+static void cxl_memdev_apply_dsmas(struct cxl_dev_state *cxlds,
+ struct xarray *dsmas_xa,
+ enum cxl_dsmas_apply attrs)
{
struct device *dev = cxlds->dev;
struct dsmas_entry *dent;
+ bool dc_matched = false;
unsigned long index;
xa_for_each(dsmas_xa, index, dent) {
bool found = false;
for (int i = 0; i < cxlds->nr_partitions; i++) {
- struct resource *res = &cxlds->part[i].res;
+ struct cxl_dpa_partition *part = &cxlds->part[i];
struct range range = {
- .start = res->start,
- .end = res->end,
+ .start = part->res.start,
+ .end = part->res.end,
};
- if (range_contains(&range, &dent->dpa_range)) {
- update_perf_entry(dev, dent,
- &cxlds->part[i].perf);
- found = true;
+ if (!range_contains(&range, &dent->dpa_range))
+ continue;
+
+ found = true;
+ /*
+ * part->handle is from Get DC Config, dent->handle
+ * from the CDAT DSMAS entry.
+ */
+ if (part->mode == CXL_PARTMODE_DYNAMIC_RAM &&
+ dent->handle != part->handle) {
+ dev_warn(dev,
+ "DSMAD handle mismatch: %pra has %u, DSMAS %pra has %u\n",
+ &range, part->handle,
+ &dent->dpa_range, dent->handle);
break;
}
+
+ if (attrs == CXL_DSMAS_APPLY_FLAGS_PERF)
+ update_perf_entry(dev, dent, &part->perf);
+ if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
+ part->shareable = dent->shareable;
+ part->read_only = dent->read_only;
+ dc_matched = true;
+ }
+ break;
}
if (!found)
dev_dbg(dev, "no partition for dsmas dpa: %pra\n",
&dent->dpa_range);
}
+
+ if (!dc_matched)
+ cxl_dcd_dsmas_missing(cxlds, "no matching entry");
}
static int match_cxlrd_qos_class(struct device *dev, void *data)
@@ -409,22 +478,26 @@ void cxl_endpoint_parse_cdat(struct cxl_port *port)
int rc;
xa_init(&__dsmas_xa);
- if (!port->cdat.table)
+ if (!port->cdat.table) {
+ cxl_dcd_dsmas_missing(cxlds, "no CDAT");
return;
+ }
rc = cxl_cdat_endpoint_process(port, dsmas_xa);
if (rc < 0) {
dev_dbg(&port->dev, "Failed to parse CDAT: %d\n", rc);
+ cxl_dcd_dsmas_missing(cxlds, "CDAT parse failed");
return;
}
rc = cxl_port_perf_data_calculate(port, dsmas_xa);
if (rc) {
dev_dbg(&port->dev, "Failed to do perf coord calculations.\n");
+ cxl_memdev_apply_dsmas(cxlds, dsmas_xa, CXL_DSMAS_APPLY_FLAGS);
return;
}
- cxl_memdev_set_qos_class(cxlds, dsmas_xa);
+ cxl_memdev_apply_dsmas(cxlds, dsmas_xa, CXL_DSMAS_APPLY_FLAGS_PERF);
cxl_qos_class_verify(cxlmd);
cxl_memdev_update_perf(cxlmd);
}
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 5fa2177cefcc..379540246333 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -486,6 +486,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
cxlds->part[i].mode = part->mode;
+ cxlds->part[i].handle = part->handle;
/* Require ordered + contiguous partitions */
if (i) {
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 72af23ba288e..12598d329e95 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1366,6 +1366,7 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
u64 decode_len = le64_to_cpu(dev_part->decode_length);
u64 blk_size = le64_to_cpu(dev_part->block_size);
u64 len = le64_to_cpu(dev_part->length);
+ u32 handle = le32_to_cpu(dev_part->dsmad_handle);
u64 size;
/*
@@ -1378,6 +1379,13 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
return 0;
}
+ /* The CDAT DSMAD handle this refers to is 8 bits */
+ if (handle & ~0xFF) {
+ dev_warn(dev, "DSMAD handle 0x%x exceeds the 8 bit CDAT DSMAD handle\n",
+ handle);
+ return -EINVAL;
+ }
+
/*
* Decode length is a count of 256M units, so a device reporting 2^36
* or more wraps.
@@ -1391,6 +1399,7 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
*part = (struct cxl_dc_partition_info) {
.start = le64_to_cpu(dev_part->base),
.size = size,
+ .handle = handle,
};
/*
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index def26c490dfe..7aa79a1a53e4 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -594,7 +594,8 @@ bool is_cxl_memdev(const struct device *dev)
}
EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
-static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode)
+static void add_part(struct cxl_dpa_info *info, u64 start, u64 size,
+ enum cxl_partition_mode mode, u8 handle)
{
int i = info->nr_partitions;
@@ -606,6 +607,7 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa
.end = start + size - 1,
};
info->part[i].mode = mode;
+ info->part[i].handle = handle;
info->nr_partitions++;
}
@@ -623,9 +625,9 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
info->size = mds->total_bytes;
if (mds->partition_align_bytes == 0) {
- add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
+ add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM, 0);
add_part(info, mds->volatile_only_bytes,
- mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
+ mds->persistent_only_bytes, CXL_PARTMODE_PMEM, 0);
return 0;
}
@@ -635,9 +637,9 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
return rc;
}
- add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM);
+ add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM, 0);
add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes,
- CXL_PARTMODE_PMEM);
+ CXL_PARTMODE_PMEM, 0);
return 0;
}
@@ -685,7 +687,8 @@ int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
info->size = total;
dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
dc_info.start, dc_info.size);
- add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
+ add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM,
+ dc_info.handle);
return 0;
}
@@ -703,7 +706,7 @@ int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity)
.size = capacity,
};
- add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM);
+ add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM, 0);
return cxl_dpa_setup(cxlds, &range_info);
}
EXPORT_SYMBOL_NS_GPL(cxl_set_capacity, "CXL");
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 4fac65dbb808..9fd5af2e41d4 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -140,6 +140,7 @@ struct cxl_dpa_info {
struct cxl_dpa_part_info {
struct range range;
enum cxl_partition_mode mode;
+ u8 handle;
} part[CXL_NR_PARTITIONS_MAX];
int nr_partitions;
};
@@ -851,6 +852,7 @@ int cxl_dev_state_identify(struct cxl_memdev_state *mds);
struct cxl_dc_partition_info {
u64 start;
u64 size;
+ u8 handle;
};
int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index e07360849344..728decda57fd 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -141,11 +141,17 @@ enum cxl_partition_mode {
* @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
* @perf: performance attributes of the partition from CDAT
* @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
+ * @handle: DSMAS handle that represents this partition
+ * @shareable: Is the partition shareable (from its CDAT DSMAS entry)
+ * @read_only: Is the partition read-only (from its CDAT DSMAS entry)
*/
struct cxl_dpa_partition {
struct resource res;
struct cxl_dpa_perf perf;
enum cxl_partition_mode mode;
+ u8 handle;
+ bool shareable;
+ bool read_only;
};
#define CXL_NR_PARTITIONS_MAX 3
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions
2026-10-07 20:16 ` [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
@ 2026-10-07 20:33 ` sashiko-bot
2026-10-07 23:45 ` Alison Schofield
1 sibling, 0 replies; 20+ messages in thread
From: sashiko-bot @ 2026-10-07 20:33 UTC (permalink / raw)
To: Anisa Su; +Cc: linux-cxl, nvdimm
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] cxl: Ineffective DCD disablement leaves partially configured partitions exposed
- [Medium] cxl: QoS class 0 incorrectly overwrites CXL_QOS_CLASS_INVALID
- [Low] cxl: Lockless modification of DPA partition attributes exposes torn reads
--
commit 6722908eab4fa5c8dd9820d34f1ec3beb729c8f0
Author: Ira Weiny <iweiny@kernel.org>
cxl/cdat: Gather DSMAS data for DCD partitions
Additional DCD partition (AKA region) information is contained in the
DSMAS CDAT tables, including performance, shareable and read-only
attributes. Match DCD partitions with DSMAS tables and store the meta
data.
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index 5c9f072625135..07aedff657d9e 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
[ ... ]
> @@ -219,6 +226,13 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
> xa_for_each(dsmas_xa, index, dent) {
> int qos_class;
>
> + /* No DSLBIS for this DSMAS; nothing to hand the QTG _DSM */
> + if (!dent->cdat_coord[ACCESS_COORDINATE_CPU].read_bandwidth &&
> + !dent->cdat_coord[ACCESS_COORDINATE_CPU].write_bandwidth &&
> + !dent->cdat_coord[ACCESS_COORDINATE_CPU].read_latency &&
> + !dent->cdat_coord[ACCESS_COORDINATE_CPU].write_latency)
> + continue;
[Severity: Medium]
When this continue statement is taken, dent->qos_class remains 0 (from
kzalloc_obj zero-initialization).
If at least one other entry succeeds, cxl_memdev_apply_dsmas() will be called
with CXL_DSMAS_APPLY_FLAGS_PERF, which unconditionally calls update_perf_entry()
and overwrites part->perf.qos_class (previously CXL_QOS_CLASS_INVALID) with 0.
Since 0 is a valid QoS class in CXL, does this falsely advertise a QoS class of
0 to userspace for partitions lacking DSLBIS performance coordinates?
> +
> cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c);
> dent->entries = 1;
> rc = cxl_root->ops.qos_class(cxl_root,
[ ... ]
> @@ -255,35 +269,90 @@ static void update_perf_entry(struct device *dev, struct dsmas_entry *dent,
> dent->coord[ACCESS_COORDINATE_CPU].write_latency);
> }
>
> -static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,
> - struct xarray *dsmas_xa)
> +/*
> + * A DCD shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3).
> + * Without one the partition's attributes are unknown, so disable DCD.
> + */
> +static void cxl_dcd_dsmas_missing(struct cxl_dev_state *cxlds, const char *why)
> +{
> + struct cxl_memdev_state *mds;
> +
> + if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
> + return;
> +
> + mds = to_cxl_memdev_state(cxlds);
> + if (!cxl_dcd_supported(mds) ||
> + !cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM))
> + return;
> +
> + dev_warn(cxlds->dev, "DC partition has no valid DSMAS entry (%s), disabling DCD\n",
> + why);
> + cxl_disable_dcd(mds);
[Severity: High]
Does clearing the mds->dcd_supported flag effectively disable the partition?
Since cxl_configure_dcd() and cxl_dpa_setup() have already executed during
cxl_pci_probe(), the DCD partition is permanently added to cxlds->part and its
DPA resource is registered.
Because mds->dcd_supported is never evaluated again during region creation or
sysfs access, does the partition remain fully exposed and usable by userspace
without valid DSMAS attributes?
> +}
> +
> +enum cxl_dsmas_apply {
> + CXL_DSMAS_APPLY_FLAGS, /* shareable etc.; no QTG data */
> + CXL_DSMAS_APPLY_FLAGS_PERF, /* perf coordinates and qos_class */
> +};
> +
> +/*
> + * DSMAS flags such as shareable are properties of the CDAT entry and are
> + * applied regardless; perf data is applied only if the QTG lookup produced
> + * recommendations.
> + */
> +static void cxl_memdev_apply_dsmas(struct cxl_dev_state *cxlds,
> + struct xarray *dsmas_xa,
> + enum cxl_dsmas_apply attrs)
> {
> struct device *dev = cxlds->dev;
> struct dsmas_entry *dent;
> + bool dc_matched = false;
> unsigned long index;
>
> xa_for_each(dsmas_xa, index, dent) {
> bool found = false;
>
> for (int i = 0; i < cxlds->nr_partitions; i++) {
> - struct resource *res = &cxlds->part[i].res;
> + struct cxl_dpa_partition *part = &cxlds->part[i];
[ ... ]
> + if (attrs == CXL_DSMAS_APPLY_FLAGS_PERF)
> + update_perf_entry(dev, dent, &part->perf);
> + if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
> + part->shareable = dent->shareable;
> + part->read_only = dent->read_only;
> + dc_matched = true;
> + }
[Severity: Low]
Are these partition attributes being modified locklessly?
The CXL memdev and its sysfs attributes are registered and visible during
cxl_pci_probe(), while this CDAT parsing happens later in
cxl_endpoint_port_probe().
If part->perf, part->shareable, and part->read_only are updated without holding
the cxl_rwsem.dpa lock, can concurrent userspace sysfs readers observe
intermediate, torn, or partially updated performance states?
> + break;
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261007201828.952-1-anisa.su@samsung.com?part=3
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions
2026-10-07 20:16 ` [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-10-07 20:33 ` sashiko-bot
@ 2026-10-07 23:45 ` Alison Schofield
1 sibling, 0 replies; 20+ messages in thread
From: Alison Schofield @ 2026-10-07 23:45 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dan Williams, Dave Jiang,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
On Wed, Oct 07, 2026 at 01:16:36PM -0700, Anisa Su wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Additional DCD partition (AKA region) information is contained in the
> DSMAS CDAT tables, including performance, shareable and read-only
> attributes.
>
> Match DCD partitions with DSMAS tables and store the meta data. A DCD
> shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3), so
> if the CDAT is absent, fails to parse, or has no entry matching the DC
> partition, disable DCD rather than run with unknown attributes.
>
> DSLBIS is optional, but cxl_cdat_endpoint_process() treated zero DSLBIS
> entries as a parse failure, which would now disable DCD on a device with
> a valid DSMAS. Accept an empty DSLBIS, and skip DSMAS entries with no
> DSLBIS coordinates.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v15 4/8] cxl/events: Split event msgnum configuration from irq setup
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
` (2 preceding siblings ...)
2026-10-07 20:16 ` [PATCH v15 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:16 ` [PATCH v15 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
` (4 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Dynamic Capacity Devices (DCD) require event interrupts to process
memory addition or removal. BIOS may have control over non-DCD event
processing. DCD interrupt configuration needs to be separate from
memory event interrupt configuration.
Split cxl_event_config_msgnums() from irq setup in preparation for
separate DCD interrupts configuration.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Jonathan Cameron <jic23@kernel.org>
Reviewed-by: Fan Ni <nifan.cxl@gmail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
---
drivers/cxl/pci.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 2fe9db4b3d86..4867657f5526 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -600,35 +600,31 @@ static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
return cxl_event_get_int_policy(mds, policy);
}
-static int cxl_event_irqsetup(struct cxl_memdev_state *mds)
+static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
+ struct cxl_event_interrupt_policy *policy)
{
struct cxl_dev_state *cxlds = &mds->cxlds;
- struct cxl_event_interrupt_policy policy;
int rc;
- rc = cxl_event_config_msgnums(mds, &policy);
- if (rc)
- return rc;
-
- rc = cxl_event_req_irq(cxlds, policy.info_settings);
+ rc = cxl_event_req_irq(cxlds, policy->info_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n");
return rc;
}
- rc = cxl_event_req_irq(cxlds, policy.warn_settings);
+ rc = cxl_event_req_irq(cxlds, policy->warn_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n");
return rc;
}
- rc = cxl_event_req_irq(cxlds, policy.failure_settings);
+ rc = cxl_event_req_irq(cxlds, policy->failure_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n");
return rc;
}
- rc = cxl_event_req_irq(cxlds, policy.fatal_settings);
+ rc = cxl_event_req_irq(cxlds, policy->fatal_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n");
return rc;
@@ -675,11 +671,15 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge,
return -EBUSY;
}
+ rc = cxl_event_config_msgnums(mds, &policy);
+ if (rc)
+ return rc;
+
rc = cxl_mem_alloc_event_buf(mds);
if (rc)
return rc;
- rc = cxl_event_irqsetup(mds);
+ rc = cxl_event_irqsetup(mds, &policy);
if (rc)
return rc;
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v15 5/8] cxl/pci: Factor out interrupt policy check
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
` (3 preceding siblings ...)
2026-10-07 20:16 ` [PATCH v15 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:16 ` [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
` (3 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Dynamic Capacity Devices (DCD) require event interrupts to process
memory addition or removal. BIOS may have control over non-DCD event
processing. DCD interrupt configuration needs to be separate from
memory event interrupt configuration.
Factor out check for firmware ownership of memory event logs.
Link: https://lore.kernel.org/all/663922b475e50_d54d72945b@dwillia2-xfh.jf.intel.com.notmuch/ [1]
Suggested-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jic23@kernel.org>
Reviewed-by: Fan Ni <nifan.cxl@gmail.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
---
drivers/cxl/pci.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 4867657f5526..7b754af2168d 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -640,6 +640,14 @@ static bool cxl_event_int_is_fw(u8 setting)
return mode == CXL_INT_FW;
}
+static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy)
+{
+ return cxl_event_int_is_fw(policy->info_settings) ||
+ cxl_event_int_is_fw(policy->warn_settings) ||
+ cxl_event_int_is_fw(policy->failure_settings) ||
+ cxl_event_int_is_fw(policy->fatal_settings);
+}
+
static int cxl_event_config(struct pci_host_bridge *host_bridge,
struct cxl_memdev_state *mds, bool irq_avail)
{
@@ -662,10 +670,7 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge,
if (rc)
return rc;
- if (cxl_event_int_is_fw(policy.info_settings) ||
- cxl_event_int_is_fw(policy.warn_settings) ||
- cxl_event_int_is_fw(policy.failure_settings) ||
- cxl_event_int_is_fw(policy.fatal_settings)) {
+ if (cxl_event_fw_owns_mem_logs(&policy)) {
dev_err(mds->cxlds.dev,
"FW still in control of Event Logs despite _OSC settings\n");
return -EBUSY;
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
` (4 preceding siblings ...)
2026-10-07 20:16 ` [PATCH v15 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:30 ` sashiko-bot
` (2 more replies)
2026-10-07 20:16 ` [PATCH v15 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
` (2 subsequent siblings)
8 siblings, 3 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Dynamic Capacity Devices (DCD) support extent change notifications
through the event log mechanism. The interrupt mailbox commands were
extended in CXL 3.1 to support these notifications. Firmware can't
configure DCD events to be FW controlled but can retain control of
memory events.
Configure DCD event log interrupts on devices supporting dynamic
capacity. Disable DCD if interrupts are not supported.
The DCD event log is not drained here. cxl_event_drain_mask() reports
only the logs the driver can service, and the DCD bit is added by
the patch introducing DCD event handling. Until then a DCD interrupt
wakes the event thread, which finds no log it owns and returns.
Care is taken to preserve the interrupt policy set by the FW if FW first
has been selected by the BIOS.
Based on an original patch by Navneet Singh.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
---
Changes:
1. cxl.h: add CXLDEV_EVENT_STATUS_STANDARD_LOGS for the four logs whose
ownership follows native_cxl_error, and use it in
cxl_event_drain_mask() and the cxl_test mock instead of spelling the
mask out in both places.
[Dave, Richard, Jonathan]
2. On platforms where BIOS owns the event logs, a failed Get/Set Event
Interrupt Policy disables DCD instead of failing probe. Before DCD
this path never reached the mailbox there; now DCD is the only
reason it does, so its failure costs DCD, not the memdev.
[Sashiko]
---
drivers/cxl/cxl.h | 14 ++--
drivers/cxl/cxlmem.h | 2 +
drivers/cxl/pci.c | 143 +++++++++++++++++++++++++++++------
tools/testing/cxl/test/mem.c | 2 +-
4 files changed, 133 insertions(+), 28 deletions(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index cab8ce39f465..15356d25369d 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -192,11 +192,15 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
#define CXLDEV_EVENT_STATUS_WARN BIT(1)
#define CXLDEV_EVENT_STATUS_FAIL BIT(2)
#define CXLDEV_EVENT_STATUS_FATAL BIT(3)
-
-#define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
- CXLDEV_EVENT_STATUS_WARN | \
- CXLDEV_EVENT_STATUS_FAIL | \
- CXLDEV_EVENT_STATUS_FATAL)
+#define CXLDEV_EVENT_STATUS_DCD BIT(4)
+/*
+ * Logs whose ownership follows native_cxl_error; the DCD log is always
+ * OS owned.
+ */
+#define CXLDEV_EVENT_STATUS_STANDARD_LOGS (CXLDEV_EVENT_STATUS_INFO | \
+ CXLDEV_EVENT_STATUS_WARN | \
+ CXLDEV_EVENT_STATUS_FAIL | \
+ CXLDEV_EVENT_STATUS_FATAL)
/* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
#define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 9fd5af2e41d4..9106affd7c81 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -240,7 +240,9 @@ struct cxl_event_interrupt_policy {
u8 warn_settings;
u8 failure_settings;
u8 fatal_settings;
+ u8 dcd_settings;
} __packed;
+#define CXL_EVENT_INT_POLICY_BASE_SIZE 4 /* info, warn, failure, fatal */
/**
* struct cxl_event_state - Event log driver state
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 7b754af2168d..d2bed92be30d 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -510,11 +510,22 @@ static bool cxl_alloc_irq_vectors(struct pci_dev *pdev)
return true;
}
+/* Event logs the driver drains: standard logs when native_cxl */
+static u32 cxl_event_drain_mask(struct pci_host_bridge *host_bridge)
+{
+ if (host_bridge->native_cxl_error)
+ return CXLDEV_EVENT_STATUS_STANDARD_LOGS;
+ return 0;
+}
+
static irqreturn_t cxl_event_thread(int irq, void *id)
{
struct cxl_dev_id *dev_id = id;
struct cxl_dev_state *cxlds = dev_id->cxlds;
struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ struct pci_host_bridge *host_bridge =
+ pci_find_host_bridge(to_pci_dev(cxlds->dev)->bus);
+ u32 mask = cxl_event_drain_mask(host_bridge);
u32 status;
do {
@@ -523,8 +534,8 @@ static irqreturn_t cxl_event_thread(int irq, void *id)
* ignore the reserved upper 32 bits
*/
status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET);
- /* Ignore logs unknown to the driver */
- status &= CXLDEV_EVENT_STATUS_ALL;
+ /* Ignore logs unknown to the driver or owned by BIOS */
+ status &= mask;
if (!status)
break;
cxl_mem_get_event_records(mds, status);
@@ -551,42 +562,62 @@ static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting)
}
static int cxl_event_get_int_policy(struct cxl_memdev_state *mds,
- struct cxl_event_interrupt_policy *policy)
+ struct cxl_event_interrupt_policy *policy,
+ size_t *policy_size)
{
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
struct cxl_mbox_cmd mbox_cmd = {
.opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY,
.payload_out = policy,
.size_out = sizeof(*policy),
+ /* CXL 2.0 firmware omits dcd_settings; accept the shorter reply */
+ .min_out = CXL_EVENT_INT_POLICY_BASE_SIZE,
};
int rc;
rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd);
- if (rc < 0)
+ if (rc < 0) {
dev_err(mds->cxlds.dev,
"Failed to get event interrupt policy : %d", rc);
+ return rc;
+ }
+ if (policy_size)
+ *policy_size = mbox_cmd.size_out;
return rc;
}
static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
- struct cxl_event_interrupt_policy *policy)
+ struct cxl_event_interrupt_policy *policy,
+ bool native_cxl, size_t policy_size)
{
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
struct cxl_mbox_cmd mbox_cmd;
int rc;
- *policy = (struct cxl_event_interrupt_policy) {
- .info_settings = CXL_INT_MSI_MSIX,
- .warn_settings = CXL_INT_MSI_MSIX,
- .failure_settings = CXL_INT_MSI_MSIX,
- .fatal_settings = CXL_INT_MSI_MSIX,
- };
+ /* memory event policy is left if FW has control */
+ if (native_cxl) {
+ *policy = (struct cxl_event_interrupt_policy) {
+ .info_settings = CXL_INT_MSI_MSIX,
+ .warn_settings = CXL_INT_MSI_MSIX,
+ .failure_settings = CXL_INT_MSI_MSIX,
+ .fatal_settings = CXL_INT_MSI_MSIX,
+ .dcd_settings = 0,
+ };
+ }
+
+ /*
+ * A CXL 3.0+ device can carry dcd_settings field without DCD command
+ * support, so size the request by the device's policy_size and only
+ * enable the DCD interrupt when DCD commands are supported.
+ */
+ if (cxl_dcd_supported(mds))
+ policy->dcd_settings = CXL_INT_MSI_MSIX;
mbox_cmd = (struct cxl_mbox_cmd) {
.opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY,
.payload_in = policy,
- .size_in = sizeof(*policy),
+ .size_in = policy_size,
};
rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd);
@@ -597,7 +628,7 @@ static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
}
/* Retrieve final interrupt settings */
- return cxl_event_get_int_policy(mds, policy);
+ return cxl_event_get_int_policy(mds, policy, NULL);
}
static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
@@ -633,6 +664,30 @@ static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
return 0;
}
+static int cxl_irqsetup(struct cxl_memdev_state *mds,
+ struct cxl_event_interrupt_policy *policy,
+ bool native_cxl)
+{
+ struct cxl_dev_state *cxlds = &mds->cxlds;
+ int rc;
+
+ if (native_cxl) {
+ rc = cxl_event_irqsetup(mds, policy);
+ if (rc)
+ return rc;
+ }
+
+ if (cxl_dcd_supported(mds)) {
+ rc = cxl_event_req_irq(cxlds, policy->dcd_settings);
+ if (rc) {
+ dev_err(cxlds->dev, "Failed to get interrupt for DCD event log\n");
+ cxl_disable_dcd(mds);
+ }
+ }
+
+ return 0;
+}
+
static bool cxl_event_int_is_fw(u8 setting)
{
u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting);
@@ -651,46 +706,90 @@ static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy
static int cxl_event_config(struct pci_host_bridge *host_bridge,
struct cxl_memdev_state *mds, bool irq_avail)
{
- struct cxl_event_interrupt_policy policy;
+ struct cxl_event_interrupt_policy policy = { 0 };
+ bool native_cxl = host_bridge->native_cxl_error;
+ size_t policy_size;
+ u32 mask;
int rc;
/*
* When BIOS maintains CXL error reporting control, it will process
* event records. Only one agent can do so.
+ *
+ * If BIOS has control of events and DCD is not supported skip event
+ * configuration.
*/
- if (!host_bridge->native_cxl_error)
+ if (!native_cxl && !cxl_dcd_supported(mds))
return 0;
if (!irq_avail) {
dev_info(mds->cxlds.dev, "No interrupt support, disable event processing.\n");
+ if (cxl_dcd_supported(mds)) {
+ dev_info(mds->cxlds.dev, "DCD requires interrupts, disable DCD\n");
+ cxl_disable_dcd(mds);
+ }
return 0;
}
- rc = cxl_event_get_int_policy(mds, &policy);
+ rc = cxl_event_get_int_policy(mds, &policy, &policy_size);
if (rc)
- return rc;
+ goto err;
+
+ /*
+ * dcd_settings cannot be sent to a device whose policy is too short
+ * to hold it, so the device would never accept the setting
+ * cxl_irqsetup() arms the DCD interrupt with.
+ */
+ if (cxl_dcd_supported(mds) && policy_size < sizeof(policy)) {
+ dev_warn(mds->cxlds.dev,
+ "DCD supported but interrupt policy is only %zu bytes\n",
+ policy_size);
+ cxl_disable_dcd(mds);
+ /* DCD was the only reason to be here */
+ if (!native_cxl)
+ return 0;
+ }
- if (cxl_event_fw_owns_mem_logs(&policy)) {
+ if (native_cxl && cxl_event_fw_owns_mem_logs(&policy)) {
dev_err(mds->cxlds.dev,
"FW still in control of Event Logs despite _OSC settings\n");
return -EBUSY;
}
- rc = cxl_event_config_msgnums(mds, &policy);
+ rc = cxl_event_config_msgnums(mds, &policy, native_cxl, policy_size);
if (rc)
- return rc;
+ goto err;
rc = cxl_mem_alloc_event_buf(mds);
if (rc)
return rc;
- rc = cxl_event_irqsetup(mds, &policy);
+ rc = cxl_irqsetup(mds, &policy, native_cxl);
if (rc)
return rc;
- cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL);
+ mask = cxl_event_drain_mask(host_bridge);
+ if (mask)
+ cxl_mem_get_event_records(mds, mask);
+
+ dev_dbg(mds->cxlds.dev, "Event config : %s DCD %s\n",
+ native_cxl ? "OS" : "BIOS",
+ cxl_dcd_supported(mds) ? "supported" : "not supported");
return 0;
+
+err:
+ /*
+ * Failed to Get/Set interrupt policy for DCD while BIOS owns the
+ * other logs. Disable DCD and continue.
+ */
+ if (!native_cxl) {
+ dev_warn(mds->cxlds.dev,
+ "Event interrupt policy failed (%d), disabling DCD\n", rc);
+ cxl_disable_dcd(mds);
+ return 0;
+ }
+ return rc;
}
static int cxl_pci_type3_init_mailbox(struct cxl_dev_state *cxlds)
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 7b756000a1a6..c740372bdaaa 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -1818,7 +1818,7 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
if (rc)
dev_dbg(dev, "No CXL FWCTL setup\n");
- cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL);
+ cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_STANDARD_LOGS);
cxl_mock_test_feat_init(mdata);
return 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts
2026-10-07 20:16 ` [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
@ 2026-10-07 20:30 ` sashiko-bot
2026-10-07 23:46 ` Alison Schofield
2026-10-08 8:58 ` Richard Cheng
2 siblings, 0 replies; 20+ messages in thread
From: sashiko-bot @ 2026-10-07 20:30 UTC (permalink / raw)
To: Anisa Su; +Cc: linux-cxl, nvdimm
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] cxl: infinite loop in cxl_event_thread() on device surprise removal
--
commit 84b381be3cde0a84228cae787a5be8a35384cffd
Author: Ira Weiny <iweiny@kernel.org>
cxl/mem: Configure dynamic capacity interrupts
Dynamic Capacity Devices (DCD) support extent change notifications
through the event log mechanism. The interrupt mailbox commands were
extended in CXL 3.1 to support these notifications. Firmware can't
configure DCD events to be FW controlled but can retain control of
memory events.
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 7b754af2168d0..d2bed92be30df 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
[ ... ]
> @@ -523,8 +534,8 @@ static irqreturn_t cxl_event_thread(int irq, void *id)
> * ignore the reserved upper 32 bits
> */
> status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET);
> - /* Ignore logs unknown to the driver */
> - status &= CXLDEV_EVENT_STATUS_ALL;
> + /* Ignore logs unknown to the driver or owned by BIOS */
> + status &= mask;
> if (!status)
> break;
> cxl_mem_get_event_records(mds, status);
> cond_resched();
> } while (status);
[Severity: High]
If the CXL device is surprise-removed or its PCIe link goes down, readl()
will return ~0U. Since this is masked with a non-zero bitmask, could
this result in an infinite loop?
If the loop does not break, the IRQ thread could consume 100% of a CPU core
and prevent the PCI removal path from completing. Should there be a check
for status == ~0U to break out of the loop?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261007201828.952-1-anisa.su@samsung.com?part=6
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts
2026-10-07 20:16 ` [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-10-07 20:30 ` sashiko-bot
@ 2026-10-07 23:46 ` Alison Schofield
2026-10-08 8:58 ` Richard Cheng
2 siblings, 0 replies; 20+ messages in thread
From: Alison Schofield @ 2026-10-07 23:46 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dan Williams, Dave Jiang,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
On Wed, Oct 07, 2026 at 01:16:39PM -0700, Anisa Su wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Dynamic Capacity Devices (DCD) support extent change notifications
> through the event log mechanism. The interrupt mailbox commands were
> extended in CXL 3.1 to support these notifications. Firmware can't
> configure DCD events to be FW controlled but can retain control of
> memory events.
>
> Configure DCD event log interrupts on devices supporting dynamic
> capacity. Disable DCD if interrupts are not supported.
>
> The DCD event log is not drained here. cxl_event_drain_mask() reports
> only the logs the driver can service, and the DCD bit is added by
> the patch introducing DCD event handling. Until then a DCD interrupt
> wakes the event thread, which finds no log it owns and returns.
>
> Care is taken to preserve the interrupt policy set by the FW if FW first
> has been selected by the BIOS.
>
> Based on an original patch by Navneet Singh.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts
2026-10-07 20:16 ` [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-10-07 20:30 ` sashiko-bot
2026-10-07 23:46 ` Alison Schofield
@ 2026-10-08 8:58 ` Richard Cheng
2 siblings, 0 replies; 20+ messages in thread
From: Richard Cheng @ 2026-10-08 8:58 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dan Williams, Dave Jiang,
Alison Schofield, Jonathan Cameron, Davidlohr Bueso, Ira Weiny,
Vishal Verma, Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price,
Anisa Su
On Wed, Oct 07, 2026 at 01:16:39PM +0800, Anisa Su wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Dynamic Capacity Devices (DCD) support extent change notifications
> through the event log mechanism. The interrupt mailbox commands were
> extended in CXL 3.1 to support these notifications. Firmware can't
> configure DCD events to be FW controlled but can retain control of
> memory events.
>
> Configure DCD event log interrupts on devices supporting dynamic
> capacity. Disable DCD if interrupts are not supported.
>
> The DCD event log is not drained here. cxl_event_drain_mask() reports
> only the logs the driver can service, and the DCD bit is added by
> the patch introducing DCD event handling. Until then a DCD interrupt
> wakes the event thread, which finds no log it owns and returns.
>
> Care is taken to preserve the interrupt policy set by the FW if FW first
> has been selected by the BIOS.
>
> Based on an original patch by Navneet Singh.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
>
> ---
> Changes:
> 1. cxl.h: add CXLDEV_EVENT_STATUS_STANDARD_LOGS for the four logs whose
> ownership follows native_cxl_error, and use it in
> cxl_event_drain_mask() and the cxl_test mock instead of spelling the
> mask out in both places.
> [Dave, Richard, Jonathan]
> 2. On platforms where BIOS owns the event logs, a failed Get/Set Event
> Interrupt Policy disables DCD instead of failing probe. Before DCD
> this path never reached the mailbox there; now DCD is the only
> reason it does, so its failure costs DCD, not the memdev.
> [Sashiko]
> ---
> drivers/cxl/cxl.h | 14 ++--
> drivers/cxl/cxlmem.h | 2 +
> drivers/cxl/pci.c | 143 +++++++++++++++++++++++++++++------
> tools/testing/cxl/test/mem.c | 2 +-
> 4 files changed, 133 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index cab8ce39f465..15356d25369d 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -192,11 +192,15 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
> #define CXLDEV_EVENT_STATUS_WARN BIT(1)
> #define CXLDEV_EVENT_STATUS_FAIL BIT(2)
> #define CXLDEV_EVENT_STATUS_FATAL BIT(3)
> -
> -#define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
> - CXLDEV_EVENT_STATUS_WARN | \
> - CXLDEV_EVENT_STATUS_FAIL | \
> - CXLDEV_EVENT_STATUS_FATAL)
> +#define CXLDEV_EVENT_STATUS_DCD BIT(4)
> +/*
> + * Logs whose ownership follows native_cxl_error; the DCD log is always
> + * OS owned.
> + */
> +#define CXLDEV_EVENT_STATUS_STANDARD_LOGS (CXLDEV_EVENT_STATUS_INFO | \
> + CXLDEV_EVENT_STATUS_WARN | \
> + CXLDEV_EVENT_STATUS_FAIL | \
> + CXLDEV_EVENT_STATUS_FATAL)
>
> /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
> #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 9fd5af2e41d4..9106affd7c81 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -240,7 +240,9 @@ struct cxl_event_interrupt_policy {
> u8 warn_settings;
> u8 failure_settings;
> u8 fatal_settings;
> + u8 dcd_settings;
> } __packed;
> +#define CXL_EVENT_INT_POLICY_BASE_SIZE 4 /* info, warn, failure, fatal */
>
> /**
> * struct cxl_event_state - Event log driver state
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 7b754af2168d..d2bed92be30d 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -510,11 +510,22 @@ static bool cxl_alloc_irq_vectors(struct pci_dev *pdev)
> return true;
> }
>
> +/* Event logs the driver drains: standard logs when native_cxl */
> +static u32 cxl_event_drain_mask(struct pci_host_bridge *host_bridge)
> +{
> + if (host_bridge->native_cxl_error)
> + return CXLDEV_EVENT_STATUS_STANDARD_LOGS;
> + return 0;
> +}
> +
> static irqreturn_t cxl_event_thread(int irq, void *id)
> {
> struct cxl_dev_id *dev_id = id;
> struct cxl_dev_state *cxlds = dev_id->cxlds;
> struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
> + struct pci_host_bridge *host_bridge =
> + pci_find_host_bridge(to_pci_dev(cxlds->dev)->bus);
> + u32 mask = cxl_event_drain_mask(host_bridge);
> u32 status;
>
> do {
> @@ -523,8 +534,8 @@ static irqreturn_t cxl_event_thread(int irq, void *id)
> * ignore the reserved upper 32 bits
> */
> status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET);
> - /* Ignore logs unknown to the driver */
> - status &= CXLDEV_EVENT_STATUS_ALL;
> + /* Ignore logs unknown to the driver or owned by BIOS */
> + status &= mask;
> if (!status)
> break;
> cxl_mem_get_event_records(mds, status);
> @@ -551,42 +562,62 @@ static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting)
> }
>
> static int cxl_event_get_int_policy(struct cxl_memdev_state *mds,
> - struct cxl_event_interrupt_policy *policy)
> + struct cxl_event_interrupt_policy *policy,
> + size_t *policy_size)
> {
> struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> struct cxl_mbox_cmd mbox_cmd = {
> .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY,
> .payload_out = policy,
> .size_out = sizeof(*policy),
> + /* CXL 2.0 firmware omits dcd_settings; accept the shorter reply */
> + .min_out = CXL_EVENT_INT_POLICY_BASE_SIZE,
> };
> int rc;
>
> rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd);
> - if (rc < 0)
> + if (rc < 0) {
> dev_err(mds->cxlds.dev,
> "Failed to get event interrupt policy : %d", rc);
> + return rc;
> + }
>
> + if (policy_size)
> + *policy_size = mbox_cmd.size_out;
> return rc;
> }
>
> static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
> - struct cxl_event_interrupt_policy *policy)
> + struct cxl_event_interrupt_policy *policy,
> + bool native_cxl, size_t policy_size)
> {
> struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
> struct cxl_mbox_cmd mbox_cmd;
> int rc;
>
> - *policy = (struct cxl_event_interrupt_policy) {
> - .info_settings = CXL_INT_MSI_MSIX,
> - .warn_settings = CXL_INT_MSI_MSIX,
> - .failure_settings = CXL_INT_MSI_MSIX,
> - .fatal_settings = CXL_INT_MSI_MSIX,
> - };
> + /* memory event policy is left if FW has control */
> + if (native_cxl) {
> + *policy = (struct cxl_event_interrupt_policy) {
> + .info_settings = CXL_INT_MSI_MSIX,
> + .warn_settings = CXL_INT_MSI_MSIX,
> + .failure_settings = CXL_INT_MSI_MSIX,
> + .fatal_settings = CXL_INT_MSI_MSIX,
> + .dcd_settings = 0,
> + };
> + }
> +
> + /*
> + * A CXL 3.0+ device can carry dcd_settings field without DCD command
> + * support, so size the request by the device's policy_size and only
> + * enable the DCD interrupt when DCD commands are supported.
> + */
> + if (cxl_dcd_supported(mds))
> + policy->dcd_settings = CXL_INT_MSI_MSIX;
>
> mbox_cmd = (struct cxl_mbox_cmd) {
> .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY,
> .payload_in = policy,
> - .size_in = sizeof(*policy),
> + .size_in = policy_size,
> };
>
> rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd);
> @@ -597,7 +628,7 @@ static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
> }
>
> /* Retrieve final interrupt settings */
> - return cxl_event_get_int_policy(mds, policy);
> + return cxl_event_get_int_policy(mds, policy, NULL);
> }
>
> static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
> @@ -633,6 +664,30 @@ static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
> return 0;
> }
>
> +static int cxl_irqsetup(struct cxl_memdev_state *mds,
> + struct cxl_event_interrupt_policy *policy,
> + bool native_cxl)
> +{
> + struct cxl_dev_state *cxlds = &mds->cxlds;
> + int rc;
> +
> + if (native_cxl) {
> + rc = cxl_event_irqsetup(mds, policy);
> + if (rc)
> + return rc;
> + }
> +
> + if (cxl_dcd_supported(mds)) {
> + rc = cxl_event_req_irq(cxlds, policy->dcd_settings);
> + if (rc) {
> + dev_err(cxlds->dev, "Failed to get interrupt for DCD event log\n");
> + cxl_disable_dcd(mds);
Hi Anisa,
If I didn't understand wrong, the interrupt has devicce half and host half.
When cxl_event_req_irq() fails for DCD log, cxl_irqsetup() disable DCD and
return 0, but still dcd_settings = MSI/MSI-X, so the device keeps signalling
a vector with no handler while driver consider DCD off.
Should we match the state together ?
Best regards,
Richard Cheng.
> + }
> + }
> +
> + return 0;
> +}
> +
> static bool cxl_event_int_is_fw(u8 setting)
> {
> u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting);
> @@ -651,46 +706,90 @@ static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy
> static int cxl_event_config(struct pci_host_bridge *host_bridge,
> struct cxl_memdev_state *mds, bool irq_avail)
> {
> - struct cxl_event_interrupt_policy policy;
> + struct cxl_event_interrupt_policy policy = { 0 };
> + bool native_cxl = host_bridge->native_cxl_error;
> + size_t policy_size;
> + u32 mask;
> int rc;
>
> /*
> * When BIOS maintains CXL error reporting control, it will process
> * event records. Only one agent can do so.
> + *
> + * If BIOS has control of events and DCD is not supported skip event
> + * configuration.
> */
> - if (!host_bridge->native_cxl_error)
> + if (!native_cxl && !cxl_dcd_supported(mds))
> return 0;
>
> if (!irq_avail) {
> dev_info(mds->cxlds.dev, "No interrupt support, disable event processing.\n");
> + if (cxl_dcd_supported(mds)) {
> + dev_info(mds->cxlds.dev, "DCD requires interrupts, disable DCD\n");
> + cxl_disable_dcd(mds);
> + }
> return 0;
> }
>
> - rc = cxl_event_get_int_policy(mds, &policy);
> + rc = cxl_event_get_int_policy(mds, &policy, &policy_size);
> if (rc)
> - return rc;
> + goto err;
> +
> + /*
> + * dcd_settings cannot be sent to a device whose policy is too short
> + * to hold it, so the device would never accept the setting
> + * cxl_irqsetup() arms the DCD interrupt with.
> + */
> + if (cxl_dcd_supported(mds) && policy_size < sizeof(policy)) {
> + dev_warn(mds->cxlds.dev,
> + "DCD supported but interrupt policy is only %zu bytes\n",
> + policy_size);
> + cxl_disable_dcd(mds);
> + /* DCD was the only reason to be here */
> + if (!native_cxl)
> + return 0;
> + }
>
> - if (cxl_event_fw_owns_mem_logs(&policy)) {
> + if (native_cxl && cxl_event_fw_owns_mem_logs(&policy)) {
> dev_err(mds->cxlds.dev,
> "FW still in control of Event Logs despite _OSC settings\n");
> return -EBUSY;
> }
>
> - rc = cxl_event_config_msgnums(mds, &policy);
> + rc = cxl_event_config_msgnums(mds, &policy, native_cxl, policy_size);
> if (rc)
> - return rc;
> + goto err;
>
> rc = cxl_mem_alloc_event_buf(mds);
> if (rc)
> return rc;
>
> - rc = cxl_event_irqsetup(mds, &policy);
> + rc = cxl_irqsetup(mds, &policy, native_cxl);
> if (rc)
> return rc;
>
> - cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL);
> + mask = cxl_event_drain_mask(host_bridge);
> + if (mask)
> + cxl_mem_get_event_records(mds, mask);
> +
> + dev_dbg(mds->cxlds.dev, "Event config : %s DCD %s\n",
> + native_cxl ? "OS" : "BIOS",
> + cxl_dcd_supported(mds) ? "supported" : "not supported");
>
> return 0;
> +
> +err:
> + /*
> + * Failed to Get/Set interrupt policy for DCD while BIOS owns the
> + * other logs. Disable DCD and continue.
> + */
> + if (!native_cxl) {
> + dev_warn(mds->cxlds.dev,
> + "Event interrupt policy failed (%d), disabling DCD\n", rc);
> + cxl_disable_dcd(mds);
> + return 0;
> + }
> + return rc;
> }
>
> static int cxl_pci_type3_init_mailbox(struct cxl_dev_state *cxlds)
> diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
> index 7b756000a1a6..c740372bdaaa 100644
> --- a/tools/testing/cxl/test/mem.c
> +++ b/tools/testing/cxl/test/mem.c
> @@ -1818,7 +1818,7 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
> if (rc)
> dev_dbg(dev, "No CXL FWCTL setup\n");
>
> - cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL);
> + cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_STANDARD_LOGS);
> cxl_mock_test_feat_init(mdata);
>
> return 0;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v15 7/8] cxl/core: Enforce partition order/simplify partition calls
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
` (5 preceding siblings ...)
2026-10-07 20:16 ` [PATCH v15 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-07 20:16 ` [PATCH v15 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
2026-10-08 8:26 ` [PATCH v15 0/8] DCD Prep Series Anisa Su
8 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su, Jonathan Cameron
From: Ira Weiny <iweiny@kernel.org>
Device partitions share one flat DPA space in a fixed order: static
volatile capacity at DPA 0, static persistent capacity immediately above
it, and dynamic capacity above all static capacity. The static pair is
mandated by CXL r4.0 8.2.10.9.2.1 "Get Partition Info", Table 8-310: the
device "shall provide this volatile capacity starting at DPA 0" and
"shall provide this persistent capacity starting at the DPA immediately
following the volatile capacity". Dynamic capacity has no such rule.
Table 8-347 only requires the region base to be 256M aligned, so placing
it directly above static capacity is a Linux requirement,
enforced by cxl_configure_dcd().
DPA 0 end
+---------------+---------------+---------------------------+
| ram | pmem | dynamic_ram_1 |
+---------------+---------------+---------------------------+
part[0] part[1] part[2]
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
drivers/cxl/core/hdm.c | 10 ++++++++++
drivers/cxl/core/memdev.c | 32 +++++++++-----------------------
drivers/cxl/cxlmem.h | 9 +++------
drivers/cxl/mem.c | 2 +-
include/cxl/cxl.h | 20 ++++++++++++++++++++
5 files changed, 43 insertions(+), 30 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 379540246333..ec5742debb52 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -470,6 +470,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
return 0;
}
+ /* Verify partitions are in expected order. */
+ for (int i = 1; i < info->nr_partitions; i++) {
+ if (info->part[i].mode < info->part[i - 1].mode) {
+ dev_err(dev, "Partition order mismatch: %d (%s) follows %d (%s)\n",
+ i, cxl_mode_name(info->part[i].mode),
+ i - 1, cxl_mode_name(info->part[i - 1].mode));
+ return -EINVAL;
+ }
+ }
+
cxlds->dpa_res = DEFINE_RES_MEM(0, info->size);
for (int i = 0; i < info->nr_partitions; i++) {
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index 7aa79a1a53e4..3ad68341d294 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -77,20 +77,12 @@ static ssize_t label_storage_size_show(struct device *dev,
}
static DEVICE_ATTR_RO(label_storage_size);
-static resource_size_t cxl_ram_size(struct cxl_dev_state *cxlds)
-{
- /* Static RAM is only expected at partition 0. */
- if (cxlds->part[0].mode != CXL_PARTMODE_RAM)
- return 0;
- return resource_size(&cxlds->part[0].res);
-}
-
static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- unsigned long long len = cxl_ram_size(cxlds);
+ unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_RAM);
return sysfs_emit(buf, "%#llx\n", len);
}
@@ -103,7 +95,7 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- unsigned long long len = cxl_pmem_size(cxlds);
+ unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_PMEM);
return sysfs_emit(buf, "%#llx\n", len);
}
@@ -426,10 +418,11 @@ static struct attribute *cxl_memdev_attributes[] = {
NULL,
};
-static struct cxl_dpa_perf *to_pmem_perf(struct cxl_dev_state *cxlds)
+static struct cxl_dpa_perf *part_perf(struct cxl_dev_state *cxlds,
+ enum cxl_partition_mode mode)
{
for (int i = 0; i < cxlds->nr_partitions; i++)
- if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
+ if (cxlds->part[i].mode == mode)
return &cxlds->part[i].perf;
return NULL;
}
@@ -440,7 +433,7 @@ static ssize_t pmem_qos_class_show(struct device *dev,
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- return sysfs_emit(buf, "%d\n", to_pmem_perf(cxlds)->qos_class);
+ return sysfs_emit(buf, "%d\n", part_perf(cxlds, CXL_PARTMODE_PMEM)->qos_class);
}
static struct device_attribute dev_attr_pmem_qos_class =
@@ -452,20 +445,13 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
NULL,
};
-static struct cxl_dpa_perf *to_ram_perf(struct cxl_dev_state *cxlds)
-{
- if (cxlds->part[0].mode != CXL_PARTMODE_RAM)
- return NULL;
- return &cxlds->part[0].perf;
-}
-
static ssize_t ram_qos_class_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- return sysfs_emit(buf, "%d\n", to_ram_perf(cxlds)->qos_class);
+ return sysfs_emit(buf, "%d\n", part_perf(cxlds, CXL_PARTMODE_RAM)->qos_class);
}
static struct device_attribute dev_attr_ram_qos_class =
@@ -501,7 +487,7 @@ static umode_t cxl_ram_visible(struct kobject *kobj, struct attribute *a, int n)
{
struct device *dev = kobj_to_dev(kobj);
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
- struct cxl_dpa_perf *perf = to_ram_perf(cxlmd->cxlds);
+ struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_RAM);
if (a == &dev_attr_ram_qos_class.attr &&
(!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
@@ -520,7 +506,7 @@ static umode_t cxl_pmem_visible(struct kobject *kobj, struct attribute *a, int n
{
struct device *dev = kobj_to_dev(kobj);
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
- struct cxl_dpa_perf *perf = to_pmem_perf(cxlmd->cxlds);
+ struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_PMEM);
if (a == &dev_attr_pmem_qos_class.attr &&
(!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 9106affd7c81..35268d1c387c 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -412,14 +412,11 @@ struct cxl_security_state {
#define CXL_MAX_DC_PARTITIONS 8
-static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
+static inline resource_size_t cxl_part_size(struct cxl_dev_state *cxlds,
+ enum cxl_partition_mode mode)
{
- /*
- * Static PMEM may be at partition index 0 when there is no static RAM
- * capacity.
- */
for (int i = 0; i < cxlds->nr_partitions; i++)
- if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
+ if (cxlds->part[i].mode == mode)
return resource_size(&cxlds->part[i].res);
return 0;
}
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 798e5c369cfc..9c4ef401cbad 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -139,7 +139,7 @@ static int cxl_mem_probe(struct device *dev)
return -ENXIO;
}
- if (cxl_pmem_size(cxlds) && IS_ENABLED(CONFIG_CXL_PMEM)) {
+ if (cxl_part_size(cxlds, CXL_PARTMODE_PMEM) && IS_ENABLED(CONFIG_CXL_PMEM)) {
rc = devm_cxl_add_nvdimm(dev, parent_port, cxlmd);
if (rc) {
if (rc == -ENODEV)
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 728decda57fd..1c04a7823f64 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -130,6 +130,26 @@ struct cxl_dpa_perf {
int qos_class;
};
+/*
+ * Partitions share one flat DPA space in a fixed order:
+ *
+ * DPA 0 end
+ * +---------------+---------------+---------------------------+
+ * | ram | pmem | dynamic_ram_1 |
+ * +---------------+---------------+---------------------------+
+ * part[0] part[1] part[2]
+ *
+ * The static ram and pmem partition order is mandated by CXL r4.0
+ * 8.2.10.9.2.1 "Get Partition Info" (opcode 4100h), Table 8-310: volatile
+ * capacity starts at DPA 0 and persistent capacity starts at the DPA
+ * immediately following it. A dynamic partition has no such
+ * requirement -- 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
+ * (opcode 4800h), Table 8-347, only requires the DC Region Base to be
+ * 256MB aligned -- but Linux follows that precedent and requires it to
+ * start at the DPA immediately following static capacity: after pmem,
+ * after ram on a device with no pmem, or at DPA 0 on a device with no
+ * static capacity at all. cxl_configure_dcd() enforces it.
+ */
enum cxl_partition_mode {
CXL_PARTMODE_RAM,
CXL_PARTMODE_PMEM,
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v15 8/8] Documentation/cxl: Document DPA partition layout and ordering rules
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
` (6 preceding siblings ...)
2026-10-07 20:16 ` [PATCH v15 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
@ 2026-10-07 20:16 ` Anisa Su
2026-10-08 8:26 ` [PATCH v15 0/8] DCD Prep Series Anisa Su
8 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-07 20:16 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dan Williams, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su, Jonathan Cameron
DC Partitions complicate DPA ordering. Add a DPA Partitions section to
cxl-driver.rst describing spec-mandated and Linux requirements for the
layout.
maturity-map.rst breaks the DCD entry into sub-items so the map shows
what this series lands: partition enumeration is [1], event handling
and DC-backed DAX regions remain [0] until the follow-on series enables
them. The parent stays [0]; nothing is usable yet.
Suggested-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
.../driver-api/cxl/linux/cxl-driver.rst | 35 +++++++++++++++++++
Documentation/driver-api/cxl/maturity-map.rst | 4 +++
2 files changed, 39 insertions(+)
diff --git a/Documentation/driver-api/cxl/linux/cxl-driver.rst b/Documentation/driver-api/cxl/linux/cxl-driver.rst
index dd6dd17dc536..212df4fb8d63 100644
--- a/Documentation/driver-api/cxl/linux/cxl-driver.rst
+++ b/Documentation/driver-api/cxl/linux/cxl-driver.rst
@@ -181,6 +181,41 @@ A Memory Device is a discrete base object that is not a port. While the
physical device it belongs to may also host an `endpoint`, the relationship
between an `endpoint` and a `memdev` is not captured in sysfs.
+DPA Partitions
+~~~~~~~~~~~~~~
+A memory device presents its capacity as one flat `Device Physical Address`
+(DPA) space divided into `partitions`, which Linux lays out in a fixed
+order::
+
+ DPA 0 end
+ +---------------+---------------+---------------------------+
+ | ram | pmem | dynamic_ram_1 |
+ +---------------+---------------+---------------------------+
+ part[0] part[1] part[2]
+
+Part of that order is required by the CXL specification and part of it is a
+Linux choice.
+
+The `ram` and `pmem` order is mandated. CXL r4.0 section 8.2.10.9.2.1 "Get
+Partition Info" (4100h), Table 8-310, mandates that volatile capacity starts
+at DPA 0 and pmem starts at the DPA immediately following it.
+
+Dynamic Capacity partitions only need to be 256MB aligned according to
+CXL r4.0 section 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
+(opcode 4800h), Table 8-347. So a device could leave a gap between ram/pmem
+(static) capacity and its first DC partition, or between one DC partition
+and the next.
+
+Linux chooses not to support gaps between static and dynamic capacity: the
+first DC partition must begin at the DPA immediately following static
+capacity -- after pmem, after ram on a device with no pmem, or at DPA 0 on
+a device with no static capacity at all.
+
+Currently, only one dynamic partition is supported. A device may report up
+to eight (CXL r4.0 Table 8-346); Linux configures the first as its
+`dynamic_ram_1` partition. Gaps between DC partitions are not checked, since
+only the first is used.
+
Port Relationships
~~~~~~~~~~~~~~~~~~
In our example described above, there are four host bridges attached to the
diff --git a/Documentation/driver-api/cxl/maturity-map.rst b/Documentation/driver-api/cxl/maturity-map.rst
index 282c1102dd81..fefd31899229 100644
--- a/Documentation/driver-api/cxl/maturity-map.rst
+++ b/Documentation/driver-api/cxl/maturity-map.rst
@@ -150,6 +150,10 @@ Memory-pooling
* [1] Hotplug of LDs (via PCI hotplug)
* [0] Dynamic Capacity Device (DCD) Support
+ * [1] DC partition enumeration / configuration (Get DC Config, CDAT DSMAS, event interrupts)
+ * [0] Extent add / release event handling
+ * [0] DC-backed DAX regions
+
Multi-host sharing
------------------
--
2.43.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v15 0/8] DCD Prep Series
2026-10-07 20:16 [PATCH v15 0/8] DCD Prep Series Anisa Su
` (7 preceding siblings ...)
2026-10-07 20:16 ` [PATCH v15 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
@ 2026-10-08 8:26 ` Anisa Su
8 siblings, 0 replies; 20+ messages in thread
From: Anisa Su @ 2026-10-08 8:26 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dan Williams, Dave Jiang,
Alison Schofield, Jonathan Cameron, Davidlohr Bueso, Ira Weiny,
Vishal Verma, Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price,
Richard Cheng
On Wed, Oct 07, 2026 at 01:16:33PM -0700, Anisa Su wrote:
> These are the first eight patches of the Dynamic Capacity Device (DCD)
> series. They set up: DCD enumeration, CDAT handling for DC partitions,
> the event interrupt plumbing, a preparatory refactor, and
> documentation of the DPA partition layout. They stand alone and keep DCD
> disabled. They are not dependent on the rest of the series.
>
> Patch 1 detects the 48h command set and then leaves mds->dcd_supported
> false. The flag is only turned on by the series that adds DCD event
> handling, so every DCD specific path added here is shut off at runtime:
> cxl_configure_dcd() never runs, no DC partition is created, no DCD
> interrupt is armed, and the CXL_PARTMODE_DYNAMIC_RAM paths are
> unreachable. The intent is to land the enumeration and plumbing while
> the extent to DAX pipeline is still under review.
>
> Based on v7.3-rc6
>
> v14: https://lore.kernel.org/linux-cxl/20260918203049.7273-1-anisa.su@samsung.com/T/#m0b6ade9da2d4fefa8aab3bb7db7c29516bc3f955
>
[snip]
> Testing
> =======
> This series leaves mds->dcd_supported false on purpose, so
> cxl_configure_dcd(), cxl_dev_dc_identify() and cxl_dc_check() are
> unreachable at runtime as posted. The tests below are done with the rest
> of the series on top, otherwise testing would not yield any meaningful
> results.
>
> HW:
> Waiting on results from partner team.
>
For the series:
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Test adding 1 extent/release to ensure interrupt configuration and DSMAS are
read properly.
FMAPI Add command is issued from BMC:
busctl call xyz.openbmc_project.MCTP_SMBus_PCIe_slot \
/xyz/openbmc_project/mctp xyz.openbmc_project.MCTP.Base \
SendReceiveMctpMessagePayload yayq \
9 101 \
8 0 72 0 0 0x53 88 0 0 0 0 0 0 \
0 1 84 0 0 72 0 4 0x56 72 0 0 0 0 0 0 \
0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \
1 0 0 0 \
0 0 0 0 1 0 0 0 \
0 0 0 0x80 0 0 0 0 \
0x7a 0x1d 0x4e 0x90 0xc3 0xb2 0x4f 0x57 0x8e 0x6d 0x21 0x5f 0x9a 0xb0 0xc4 0xd3 \
0 0 \
0 0 0 0 0 0 \
100
To add 1 extent with 2GB size, tag=7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3 and
shared sequence num = 0.
The device is shareable, so adding fails without any tag or seq num.
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_mem_get_event_records:1875: cxl_pci 0000:0b:00.0: Reading event logs: 10
[Thu Oct 8 16:59:57 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x0100
[Thu Oct 8 16:59:57 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_handle_dcd_event_records:1779: cxl_pci 0000:0b:00.0: DCD event add : DPA:0x100000000 LEN:0x80000000
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_extent_dc_partition:230: cxl_pci 0000:0b:00.0: DC extent DPA [range 0x0000000100000000-0x000000017fffffff] (DCR:[range 0x0000000000000000-0x0000001fffffffff])(7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3)
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_extent_dc_partition:230: cxl_pci 0000:0b:00.0: DC extent DPA [range 0x0000000100000000-0x000000017fffffff] (DCR:[range 0x0000000000000000-0x0000001fffffffff])(7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3)
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_extent_dc_partition:230: cxl_pci 0000:0b:00.0: DC extent DPA [range 0x0000000100000000-0x000000017fffffff] (DCR:[range 0x0000000000000000-0x0000001fffffffff])(7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3)
[Thu Oct 8 16:59:57 2026] cxl_core:__cxl_dpa_to_region:3100: cxl decoder9.0: dpa:0x100000000 mapped in region:region0
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_add_extent:517: cxl decoder9.0: Add extent [range 0x0000000100000000-0x000000017fffffff] (7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3)
[Thu Oct 8 16:59:57 2026] cxl_core:cxlr_add_extent:444: cxl_dax_region dax_region0: Alloc new tag group
[Thu Oct 8 16:59:57 2026] cxl_core:online_tag_group:732: extent0.3: dc_extent HPA [range 0x0000000100000000-0x000000017fffffff] (7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3)
[Thu Oct 8 16:59:57 2026] cxl_core:__cxlr_notify_extent:394: cxl_dax_region dax_region0: Trying notify: type 0 tag 7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3
[Thu Oct 8 16:59:57 2026] cxl_core:__cxlr_notify_extent:411: cxl_dax_region dax_region0: Notify: type 0 tag 7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3
[Thu Oct 8 16:59:57 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x4802
[Thu Oct 8 16:59:57 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 1ms
[Thu Oct 8 16:59:57 2026] cxl_core:cxl_clear_event_record:1080: cxl_pci 0000:0b:00.0: Event log '4': Clearing 9
[Thu Oct 8 16:59:57 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x0101
[Thu Oct 8 16:59:57 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
[Thu Oct 8 16:59:57 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x0100
[Thu Oct 8 16:59:57 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
[Thu Oct 8 17:00:07 2026] cxl_core:cxl_mem_get_event_records:1875: cxl_pci 0000:0b:00.0: Reading event logs: 10
[Thu Oct 8 17:00:07 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x0100
[Thu Oct 8 17:00:07 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
[Thu Oct 8 17:00:07 2026] cxl_core:cxl_handle_dcd_event_records:1779: cxl_pci 0000:0b:00.0: DCD event release : DPA:0x100000000 LEN:0x80000000
[Thu Oct 8 17:00:07 2026] cxl_core:__cxl_dpa_to_region:3100: cxl decoder9.0: dpa:0x100000000 mapped in region:region0
[Thu Oct 8 17:00:08 2026] cxl_core:__cxlr_notify_extent:394: cxl_dax_region dax_region0: Trying notify: type 1 tag 7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3
[Thu Oct 8 17:00:08 2026] cxl_core:__cxlr_notify_extent:411: cxl_dax_region dax_region0: Notify: type 1 tag 7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3
[Thu Oct 8 17:00:08 2026] cxl_core:dc_extent_unregister:528: extent0.3: DAX region rm extent HPA [range 0x0000000100000000-0x000000017fffffff]
[Thu Oct 8 17:00:08 2026] cxl_core:cxled_release_extent:70: cxl decoder9.0: Remove extent [range 0x0000000100000000-0x000000017fffffff] (7a1d4e90-c3b2-4f57-8e6d-215f9ab0c4d3)
[Thu Oct 8 17:00:08 2026] cxl_core:memdev_release_extent:1201: cxl_pci 0000:0b:00.0: Release response dpa [range 0x0000000100000000-0x000000017fffffff]
[Thu Oct 8 17:00:08 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x4803
[Thu Oct 8 17:00:08 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
[Thu Oct 8 17:00:08 2026] cxl_core:cxl_clear_event_record:1080: cxl_pci 0000:0b:00.0: Event log '4': Clearing 11
[Thu Oct 8 17:00:08 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x0101
[Thu Oct 8 17:00:08 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
[Thu Oct 8 17:00:08 2026] cxl_pci:__cxl_pci_mbox_send_cmd:264: cxl_pci 0000:0b:00.0: Sending command: 0x0100
[Thu Oct 8 17:00:08 2026] cxl_pci:cxl_pci_mbox_wait_for_doorbell:75: cxl_pci 0000:0b:00.0: Doorbell wait took 0ms
> cxl_test:
> ndctl's cxl suite against cxl_test (7.3.0-rc6, CXL as modules)
> 16 of 17 pass, cxl-features.sh skips for lack of FWCTL, and
> cxl-dcd.sh passes.
>
> QEMU:
> Tested extent add/release and DAX device create/destroy.
> Tested that expected errors are printed from malformed Get DC Configuration
> payload.
>
> Anisa Su (1):
> Documentation/cxl: Document DPA partition layout and ordering rules
>
> Ira Weiny (7):
> cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
> cxl/mem: Read dynamic capacity configuration from the device
> cxl/cdat: Gather DSMAS data for DCD partitions
> cxl/events: Split event msgnum configuration from irq setup
> cxl/pci: Factor out interrupt policy check
> cxl/mem: Configure dynamic capacity interrupts
> cxl/core: Enforce partition order/simplify partition calls
>
> .../driver-api/cxl/linux/cxl-driver.rst | 35 +++
> Documentation/driver-api/cxl/maturity-map.rst | 4 +
> drivers/cxl/core/cdat.c | 97 +++++-
> drivers/cxl/core/hdm.c | 24 +-
> drivers/cxl/core/mbox.c | 285 ++++++++++++++++++
> drivers/cxl/core/memdev.c | 94 ++++--
> drivers/cxl/cxl.h | 14 +-
> drivers/cxl/cxlmem.h | 88 +++++-
> drivers/cxl/mem.c | 2 +-
> drivers/cxl/pci.c | 176 +++++++++--
> include/cxl/cxl.h | 29 +-
> tools/testing/cxl/test/mem.c | 2 +-
> 12 files changed, 761 insertions(+), 89 deletions(-)
>
>
> base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
> --
> 2.43.0
>
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