From: Karol Wachowski <karol.wachowski@linux.intel.com>
To: dri-devel@lists.freedesktop.org
Cc: oded.gabbay@gmail.com, jeff.hugo@oss.qualcomm.com,
lizhi.hou@amd.com, andrzej.kacprowski@linux.intel.com,
dawid.osuchowski@linux.intel.com,
Karol Wachowski <karol.wachowski@linux.intel.com>
Subject: [PATCH 4/5] accel/ivpu: Merge buttress register headers
Date: Mon, 12 Oct 2026 10:38:01 +0200 [thread overview]
Message-ID: <20261012083802.2778448-5-karol.wachowski@linux.intel.com> (raw)
In-Reply-To: <20261012083802.2778448-1-karol.wachowski@linux.intel.com>
Put the MTL and LNL buttress registers in a single header, like the IP
registers. No register shares its offset between MTL and LNL, so the
MTL ones are simply followed by the LNL ones.
Also fix the DUP_IDLE typo (should be DPU_IDLE).
No functional change.
Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
---
drivers/accel/ivpu/ivpu_hw_btrs.c | 3 +-
drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h | 83 -------------------
...u_hw_btrs_lnl_reg.h => ivpu_hw_btrs_reg.h} | 82 ++++++++++++++++--
3 files changed, 78 insertions(+), 90 deletions(-)
delete mode 100644 drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
rename drivers/accel/ivpu/{ivpu_hw_btrs_lnl_reg.h => ivpu_hw_btrs_reg.h} (59%)
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c
index dce6e9d41ea9..5851d83dc36e 100644
--- a/drivers/accel/ivpu/ivpu_hw_btrs.c
+++ b/drivers/accel/ivpu/ivpu_hw_btrs.c
@@ -8,8 +8,7 @@
#include "ivpu_drv.h"
#include "ivpu_hw.h"
#include "ivpu_hw_btrs.h"
-#include "ivpu_hw_btrs_lnl_reg.h"
-#include "ivpu_hw_btrs_mtl_reg.h"
+#include "ivpu_hw_btrs_reg.h"
#include "ivpu_hw_reg_io.h"
#include "ivpu_jsm_msg.h"
#include "ivpu_pm.h"
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
deleted file mode 100644
index e93d539e066f..000000000000
--- a/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020-2023 Intel Corporation
- */
-
-#ifndef __IVPU_HW_BTRS_MTL_REG_H__
-#define __IVPU_HW_BTRS_MTL_REG_H__
-
-#include <linux/bits.h>
-
-#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u
-
-#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u
-#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
-#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
-#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
-
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
-
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
-
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u
-#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
-
-#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u
-#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
-
-#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u
-#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
-
-#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu
-#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
-
-#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u
-
-#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u
-#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
-#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
-
-#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u
-#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
-
-#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu
-#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0)
-#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2)
-
-#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u
-#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u
-
-#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u
-#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1)
-
-#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u
-#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0)
-#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
-
-#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u
-#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
-#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
-
-#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u
-#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
-
-#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u
-#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u
-#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u
-
-#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u
-#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u
-#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u
-
-#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u
-#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
-#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
-#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
-
-#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u
-
-#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_reg.h
similarity index 59%
rename from drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h
rename to drivers/accel/ivpu/ivpu_hw_btrs_reg.h
index a81a9ba540fa..8e20eed15967 100644
--- a/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h
+++ b/drivers/accel/ivpu/ivpu_hw_btrs_reg.h
@@ -1,13 +1,85 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (C) 2020-2024 Intel Corporation
+ * Copyright (C) 2020-2026 Intel Corporation
*/
-#ifndef __IVPU_HW_BTRS_LNL_REG_H__
-#define __IVPU_HW_BTRS_LNL_REG_H__
+#ifndef __IVPU_HW_BTRS_REG_H__
+#define __IVPU_HW_BTRS_REG_H__
#include <linux/bits.h>
+#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u
+
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u
+#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
+
+#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u
+#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
+
+#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu
+#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
+
+#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u
+
+#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u
+#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
+#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
+
+#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u
+#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
+
+#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu
+#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2)
+
+#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u
+#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u
+
+#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u
+#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1)
+
+#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u
+#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
+
+#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u
+#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
+
+#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u
+#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
+
+#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u
+#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u
+#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u
+
+#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u
+#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u
+#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u
+
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
+
+#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u
+
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
@@ -84,7 +156,7 @@
#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u
#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0)
#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
-#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_DPU_IDLE_MASK BIT_MASK(2)
#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
@@ -109,4 +181,4 @@
#define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u
#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
-#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */
+#endif /* __IVPU_HW_BTRS_REG_H__ */
--
2.43.0
next prev parent reply other threads:[~2026-10-12 8:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-12 8:37 [PATCH 0/5] accel/ivpu: Merge register headers and extend tile fuse config Karol Wachowski
2026-10-12 8:37 ` [PATCH 1/5] accel/ivpu: Add test mode to enable the FREQ_CHANGE interrupt Karol Wachowski
2026-10-12 8:37 ` [PATCH 2/5] accel/ivpu: Merge NPU IP register headers Karol Wachowski
2026-10-12 8:38 ` [PATCH 3/5] accel/ivpu: Merge identical 37xx and 40xx IP functions Karol Wachowski
2026-10-12 8:38 ` Karol Wachowski [this message]
2026-10-12 8:38 ` [PATCH 5/5] accel/ivpu: Extend tile fuse config to 7 bits Karol Wachowski
2026-10-12 10:44 ` [PATCH 0/5] accel/ivpu: Merge register headers and extend tile fuse config Dawid Osuchowski
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