[PATCH 5/5] accel/ivpu: Extend tile fuse config to 7 bits

[Karol Wachowski <karol.wachowski@linux.intel.com>]

The buttress code that reads the tile fuse register is shared by all
generations, so the register field definition should not differ between
them. Extend the TILE_CONFIG mask from [6:1] to [7:1] and use it
everywhere, instead of having a different field width per generation.

The tile count range check in tile_disable_check() depended on the
previous field width. It only logs a warning, and it would now warn on a
valid value, so drop it together with the tile count defines it used.

Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_hw_btrs.c     | 7 -------
 drivers/accel/ivpu/ivpu_hw_btrs_reg.h | 2 +-
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c
index 5851d83dc36e..840983a618ca 100644
--- a/drivers/accel/ivpu/ivpu_hw_btrs.c
+++ b/drivers/accel/ivpu/ivpu_hw_btrs.c
@@ -45,9 +45,6 @@
 #define BTRS_MTL_TILE_FUSE_ENABLE_BOTH 0x0
 #define BTRS_MTL_TILE_SKU_BOTH         0x3630
 
-#define BTRS_LNL_TILE_MAX_NUM          6
-#define BTRS_LNL_TILE_MAX_MASK         0x3f
-
 #define WEIGHTS_DEFAULT                0xf711f711u
 #define WEIGHTS_ATS_DEFAULT            0x0000f711u
 
@@ -99,13 +96,9 @@ void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev)
 
 static bool tile_disable_check(u32 config)
 {
-	/* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
 	if (config == 0)
 		return true;
 
-	if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1))
-		return false;
-
 	if ((config & (config - 1)) == 0)
 		return true;
 
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_reg.h
index 8e20eed15967..b9628bd9cb56 100644
--- a/drivers/accel/ivpu/ivpu_hw_btrs_reg.h
+++ b/drivers/accel/ivpu/ivpu_hw_btrs_reg.h
@@ -151,7 +151,7 @@
 
 #define VPU_HW_BTRS_LNL_TILE_FUSE				0x00000150u
 #define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK			BIT_MASK(0)
-#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK			GENMASK(6, 1)
+#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK			GENMASK(7, 1)
 
 #define VPU_HW_BTRS_LNL_VPU_STATUS				0x00000154u
 #define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK			BIT_MASK(0)
-- 
2.43.0