[PATCH 0/9] Add support for MIPS P8700

* [PATCH 0/9] Add support for MIPS P8700
@ 2026-09-14 13:55 ` Aleksa Paunovic via B4 Relay
  0 siblings, 0 replies; 65+ messages in thread
From: Aleksa Paunovic @ 2026-09-14 13:55 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
	Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Djordje Todorovic,
	Anup Patel, Thomas Gleixner, Radu Rendec, Inochi Amaoto,
	Daniel Lezcano
  Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
	Conor Dooley, linux-riscv, Vladimir Kondratiev, Aleksa Paunovic

The MIPS P8700 is a multi-core RISC-V microprocessor system, supporting
both single-cluster and multi-cluster configurations. [1]
This series adds full description of the platform,
including the Boston FPGA board configured with a P8700 bitfile.

The P8700 cores support the RV64GCZba_Zbb (G = IMAFD) Standard ISA,
with a caveat: the A extension is only partially supported, and all ZAAMO
extension instructions are emulated on the SBI level. The device tree
intentionally does not reflect this fact.

GlobalFoundries has acquired MIPS [2] and the vendor prefix
for all MIPS RISC-V hardware has been updated to reflect that fact.

All my series so far have used the dts the current one was based on,
with mostly cosmetic changes. Nevertheless, I tested this series
both on QEMU and a Boston board configured with a single P8700 CPU,
after applying the necessary U-Boot and OpenSBI changes
to match the 'compatible' strings. We are planning to upstream these
as well.

Links:
[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf
[2] https://gf.com/news-and-events/news/globalfoundries-completes-acquisition-of-mips/

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
Aleksa Paunovic (9):
      dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.
      dt-bindings: riscv: cpus: add gf,mips-p8700
      dt-bindings: riscv: Add MIPS Boston board compatible
      dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
      dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
      dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
      dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add MIPS P8700 gf compatible
      riscv: dts: gf: Initial support for the P8700 Boston board
      riscv: defconfig: Enable GF SoCs

 .../bindings/interrupt-controller/riscv,aplic.yaml |   1 +
 .../thead,c900-aclint-mswi.yaml                    |  34 +++
 .../thead,c900-aclint-sswi.yaml                    |   3 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 Documentation/devicetree/bindings/riscv/gf.yaml    |  27 +++
 .../bindings/timer/thead,c900-aclint-mtimer.yaml   |  43 +++-
 .../devicetree/bindings/vendor-prefixes.yaml       |   4 +-
 arch/riscv/Kconfig.socs                            |   6 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/gf/Makefile                    |   2 +
 arch/riscv/boot/dts/gf/p8700-boston.dts            | 135 ++++++++++++
 arch/riscv/boot/dts/gf/p8700.dtsi                  | 241 +++++++++++++++++++++
 arch/riscv/configs/defconfig                       |   1 +
 13 files changed, 494 insertions(+), 5 deletions(-)
---
base-commit: fd73f4a6659897191fa0d40695fe370925dd3780
change-id: 20260325-p8700-dts-41788f014227

Best regards,
-- 
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

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