From: Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Conor Dooley <conor@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Borislav Petkov <bp@alien8.de>, Tony Luck <tony.luck@intel.com>,
Conor Dooley <conor+dt@kernel.org>,
Abel Vesa <abelvesa@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com>
Subject: [PATCH 4/4] arm64: dts: qcom: shikra: add LCP/SRP ECC interrupt to LLCC node
Date: Wed, 14 Oct 2026 21:26:19 +0530 [thread overview]
Message-ID: <20261014-master-v1-4-aba3cfcfbac9@oss.qualcomm.com> (raw)
In-Reply-To: <20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com>
Add a second interrupt for LCP/SRP DDR DRAM ECC reporting and
interrupt-names ("llcc-ecc", "llcc-lcp-ecc") to the Shikra LLCC node,
as required by the updated DT binding.
Signed-off-by: Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 2623e139196f..ff572c003b39 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1108,7 +1108,9 @@ llcc: system-cache-controller@e00000 {
reg-names = "llcc0_base",
"llcc1_base",
"llcc_broadcast_base";
- interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "llcc-ecc", "llcc-lcp-ecc";
};
gcc: clock-controller@1400000 {
--
2.34.1
next prev parent reply other threads:[~2026-10-14 15:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 15:56 [PATCH 0/4] edac: qcom: add DDR DRAM ECC reporting for Shikra (QCM2390) Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: allow optional second interrupt for LCP/SRP ECC Faiyaz Mohammed
2026-10-14 16:05 ` sashiko-bot
2026-10-14 15:56 ` [PATCH 2/4] soc: qcom: llcc: add LCP/SRP DDR DRAM ECC register offsets Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 3/4] edac: qcom: add LCP/SRP DDR DRAM ECC support for Shikra Faiyaz Mohammed
2026-10-14 16:09 ` sashiko-bot
2026-10-14 15:56 ` Faiyaz Mohammed [this message]
2026-10-14 16:08 ` [PATCH 4/4] arm64: dts: qcom: shikra: add LCP/SRP ECC interrupt to LLCC node sashiko-bot
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