From: sashiko-bot@kernel.org
To: "Faiyaz Mohammed" <faiyaz.mohammed@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: cache: qcom,llcc: allow optional second interrupt for LCP/SRP ECC
Date: Wed, 14 Oct 2026 16:05:54 +0000 [thread overview]
Message-ID: <sashiko-outbox-171513@kernel.org> (raw)
In-Reply-To: <20261014-master-v1-1-aba3cfcfbac9@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: missing maxItems constraint for legacy interrupts
--
commit 50febfa0c04f4bae15f676db2e6662c8855b0e3c
Author: Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com>
dt-bindings: cache: qcom,llcc: allow optional second interrupt for LCP/SRP ECC
QCM2390 (Shikra) has an LCP/SRP block that signals DDR DRAM ECC errors
on a dedicated interrupt line separate from the existing TRP/DRP cache
ECC interrupt. This commit allows an optional second interrupt in the
LLCC binding and enforces both are present for qcom,shikra-llcc.
> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> index 2141e5d4de63b..3546cf7c25195 100644
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> @@ -64,7 +64,17 @@ properties:
> maxItems: 18
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: TRP/DRP LLCC cache ECC (ddrss_apps_interrupt[2])
> + - description: LCP/SRP DDR DRAM ECC (ddrss_apps_interrupt[1]), present
> + on platforms with an LCP/SRP block such as QCM2390
[Severity: Low]
Does this implicitly raise the maximum number of interrupts to 2 for all
compatible strings?
Since maxItems: 1 was removed globally, a device tree for older hardware
could erroneously define two interrupts without failing schema validation.
> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: llcc-ecc
> + - const: llcc-lcp-ecc
>
> memory-region:
> maxItems: 1
[ ... ]
> @@ -234,6 +244,20 @@ allOf:
> - const: llcc1_base
> - const: llcc_broadcast_base
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,shikra-llcc
> + then:
> + properties:
> + interrupts:
> + minItems: 2
> + interrupt-names:
> + minItems: 2
> + required:
> + - interrupt-names
> +
[Severity: Low]
Should there be an else clause here to restrict legacy platforms back to
maxItems: 1 for interrupts and interrupt-names?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com?part=1
next prev parent reply other threads:[~2026-10-14 16:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 15:56 [PATCH 0/4] edac: qcom: add DDR DRAM ECC reporting for Shikra (QCM2390) Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: allow optional second interrupt for LCP/SRP ECC Faiyaz Mohammed
2026-10-14 16:05 ` sashiko-bot [this message]
2026-10-14 15:56 ` [PATCH 2/4] soc: qcom: llcc: add LCP/SRP DDR DRAM ECC register offsets Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 3/4] edac: qcom: add LCP/SRP DDR DRAM ECC support for Shikra Faiyaz Mohammed
2026-10-14 16:09 ` sashiko-bot
2026-10-14 15:56 ` [PATCH 4/4] arm64: dts: qcom: shikra: add LCP/SRP ECC interrupt to LLCC node Faiyaz Mohammed
2026-10-14 16:08 ` sashiko-bot
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