Re: [PATCH v2 2/3] mmc: k1: let the SPL read SD cards more than one block at a time

[Yixun Lan <dlan@kernel.org>]

Hi Kathpalia, Dave,

On 19:59 Wed 14 Oct     , Dave Klotz wrote:
> On 12-10-2026 19:30, Kathpalia, Tanmay wrote:
> > Dave, I hope you are aligned with the changes discussed and tested.
> > Could you please post a new version incorporating them?
> 
> Hi Tanmay,
> 
> Sorry for the slow reply. I'm moving my K1 boards to a different boot
> chain, oreboot plus EDK2, so I won't be respinning this series. Thanks
> to you, Zixian, Yixun and Anand for the testing and the careful review.
> 
> Where things stand, for whoever picks it up:
> 
> - 1/3: Yixun suggested a sane default max-frequency when the DT has
I changed my mind of the idea to set a default in driver code level..

>   none, rather than trusting what an earlier stage left behind, and
Still don't like "what an earlier stage left", and expect to avoid

>   asked for a clearer explanation than "happens to return 0".
>   Hung-Chun's RFC, "[RFC PATCH 0/2] mmc: k1: do not require
>   max-frequency in the device tree", covers the same ground.
> 
Spent a few more time looking into this, and to understand the idea
of why setting max-frequency, turn out its goal is trying to set a
particular clock parent/frequency for the io clock.

I'd suggest we try to see if able to go with setting DT property,
 assigned-clock-parents or assigned-clock-rates
the advantage is it will also work on Linux kernel side

I've actually tested assigned-clock-rates on kernel, it worked well

If above idea is doable, then I'd suggest to drop patch 1/3 for now,
"mmc: k1: handle a missing max-frequency and clk_set_rate()'s return value"
leave the driver as current state which will keep using "max-frequency",
and I'm fine with new boards added still using "max-frequency" before
new solution landed, as it will take longer time..

BTW, the optimal emmc io clock for K1 is 375MHz(parent pll2_d8),
setting to 204.8MHz may work but runs in lower speed.
while for SD card, it's 204.8MHz(parent pll1_d6_409p6).

-- 
Yixun Lan (dlan)