Re: [PATCH v3 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology

["Michael S. Tsirkin" <mst@redhat.com>]

On Thu, Oct 15, 2026 at 02:41:55PM +0100, David Vrabel wrote:
> 
> ping?
> On 28/09/2026 16:24, David Vrabel wrote:
> > When a VM has been assigned a number of PCIe devices behind a common
> > PCIe switch and the VM intends to use peer-to-peer (P2P) transfers
> > between the devices, it is useful to be able to more report the
> > apparent PCIe bandwidth so it reflects the real handwidth of the
> > underlying hardware. This allows software in the VM (such as NCCL[1])
> > to make better decisions about whether to use P2P or not.
> > 
> > The existing emulated PCIe switch is a vintage TI XIO3130 and only
> > support 2.5 GT/s and x1, so we introduces new generic upstream and
> > downstream port devices (pcie-upstream-port and pcie-downstream-port),
> > inspired by the existing generic pcie-root-port device.
> > 
> > The existing experimental "x-speed" and "x-width" options are made
> > non-experimental, allowing the pcie-root-port and pcie-downstream-port
> > capabilities to be configured to match the hardware.
> > 
> > The pcie-root-port device is updated to default to a Gen6 capable
> > device.
> > 
> > Finally, where a root or upstream port's bandwidth has been limited,
> > we also ensure the other end of the link reports the same link status.


will merge, thanks!