From: Vishwaroop A <va@nvidia.com>
To: Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Mark Brown <broonie@kernel.org>
Cc: Sowjanya Komatineni <skomatineni@nvidia.com>,
Laxman Dewangan <ldewangan@nvidia.com>,
Breno Leitao <leitao@debian.org>,
Aaron Kling <webgeek1234@gmail.com>,
Carol Soto <csoto@nvidia.com>,
Suresh Mangipudi <smangipudi@nvidia.com>,
Vishwaroop A <va@nvidia.com>, <linux-tegra@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/2] spi: tegra210-quad: don't overwrite refreshed status with lost-IRQ snapshot
Date: Fri, 16 Oct 2026 13:25:19 +0000 [thread overview]
Message-ID: <20261016132520.3723412-2-va@nvidia.com> (raw)
In-Reply-To: <20261016132520.3723412-1-va@nvidia.com>
tegra_qspi_handle_timeout() captures a "lost IRQ" FIFO status snapshot
when the ISR cache is empty on entry but QSPI_TRANS_STATUS shows the
transfer completed. After masking the controller IRQ and draining the
workqueue with cancel_work_sync(), it re-loads the ISR cache with
smp_load_acquire(): if the drain observed a real ISR completion, the
refreshed cache holds ISR-published status_reg, tx_status and rx_status
that reflect the true hardware error state at IRQ time.
However, when both cache and snapshot are set, the code keeps the
refreshed value in the local status variable but then unconditionally
publishes the pre-drain lost_fifo_status / lost_tx_status /
lost_rx_status snapshot into tqspi->status_reg / tx_status / rx_status
via the lost_irq_snapshot branch. That snapshot is racy: if the ISR
fires on another CPU between our live QSPI_TRANS_STATUS read and our
live QSPI_FIFO_STATUS snapshot, the ISR W1Cs the hardware error bits
before we sample them, so the snapshot may contain zeroed error
fields. Overwriting the ISR-published values with these zeros makes
the manual completion handler downstream silently accept a transfer
that actually reported a FIFO error.
Clear lost_irq_snapshot when the refreshed cache is non-zero, so the
ISR-published status wins over the pre-drain snapshot in that case.
The lost-IRQ path (refreshed == 0 && live QSPI_RDY set) is unaffected.
Fixes: 1ff82c13ea94 ("spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler")
Reported-by: Carol Soto <csoto@nvidia.com>
Link: https://github.com/NVIDIA/NV-Kernels/pull/579
Signed-off-by: Vishwaroop A <va@nvidia.com>
---
drivers/spi/spi-tegra210-quad.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index d8cca3aa276b..4a5933d8112c 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -1260,8 +1260,17 @@ static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi)
* loaded the cache but before we masked).
*/
refreshed = smp_load_acquire(&tqspi->trans_status);
- if (refreshed)
+ if (refreshed) {
status = refreshed;
+ /*
+ * The drain observed a real ISR completion. Prefer the
+ * ISR-published status_reg / tx_status / rx_status over
+ * the pre-drain lost-IRQ snapshot, which may have been
+ * taken after the ISR W1C-ed the hardware error bits and
+ * therefore holds cleared values.
+ */
+ lost_irq_snapshot = false;
+ }
if (!(status & QSPI_RDY)) {
retval = -ETIMEDOUT;
--
2.17.1
next prev parent reply other threads:[~2026-10-16 13:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 13:25 [PATCH 0/2] spi: tegra210-quad: Fix timeout path status handling and DMA leak Vishwaroop A
2026-10-16 13:25 ` Vishwaroop A [this message]
2026-10-16 14:45 ` [PATCH 1/2] spi: tegra210-quad: don't overwrite refreshed status with lost-IRQ snapshot Breno Leitao
2026-10-16 13:25 ` [PATCH 2/2] spi: tegra210-quad: Unmap DMA buffers on transfer timeout Vishwaroop A
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