Re: [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

From: Yixun Lan <dlan@kernel.org>
To: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
Cc: E Shattow <e@freeshell.de>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram
Date: Wed, 21 Oct 2026 08:34:25 +0000	[thread overview]
Message-ID: <20261021083425-GKA125937@kernel.org> (raw)
In-Reply-To: <20261019141752.2077207-1-alan.tseng.cs@gmail.com>

Hi Hung-Chun,

On 22:17 Mon 19 Oct     , Hung-Chun Tseng wrote:
> Hi E,
> 
> E Shattow wrote:
> > Does BootROM configure the EEPROM peripheral for access? If not, I
> > think the justification is weak here to include this.
> 
> As far as I know it does not. The EEPROM is only read to tell the
> boards apart, so I will drop the i2c2 and EEPROM tags in v3 and keep
> the PMIC, whose rails are set before DRAM can be brought up, and the
> SPI NOR flash, which the BootROM can boot from.
> 
I've confirmed with vendor, the EEPROM isn't configured or accessed in
BootROM phase

> Yixun, is there a public description of the BootROM boot flows, or of
> which peripherals it sets up in each? That would give a clear basis
> for which nodes to tag.
> 
The ever closest docs is 
https://spacemit.com/community/document/info?lang=zh&nodepath=software/SDK/buildroot/k3_buildroot/device/boot.md

but for bootph-pre-ram, isn't it about the DT nodes which needed before DDR
initialization in SPL stage, and should have nothing to do with BootROM?
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/bootph.yaml#L70

-- 
Yixun Lan (dlan)