* [PATCH] drm/amdgpu: add DCN36 OPTC RSMU underflow registers
@ 2026-10-22 2:56 Wayne Lin
2026-10-22 4:59 ` Chung, ChiaHsuan (Tom)
0 siblings, 1 reply; 2+ messages in thread
From: Wayne Lin @ 2026-10-22 2:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander Deucher, Harry Wentland, Leo Li, Tom Chung, Wayne Lin
Expose OPTC RSMU underflow registers of dcn36 for later usage.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Assisted-by: Cursor:Grok 4.7
---
.../include/asic_reg/dcn/dcn_3_6_0_offset.h | 8 +++++
.../include/asic_reg/dcn/dcn_3_6_0_sh_mask.h | 36 +++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
index b070f9b91f17..90d624d22b3a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
@@ -8329,6 +8329,8 @@
#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+#define regODM0_OPTC_RSMU_UNDERFLOW 0x1ad4
+#define regODM0_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
#define regODM0_OPTC_UNDERFLOW_THRESHOLD 0x1ad5
#define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
@@ -8351,6 +8353,8 @@
#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+#define regODM1_OPTC_RSMU_UNDERFLOW 0x1ae4
+#define regODM1_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
#define regODM1_OPTC_UNDERFLOW_THRESHOLD 0x1ae5
#define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
@@ -8373,6 +8377,8 @@
#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+#define regODM2_OPTC_RSMU_UNDERFLOW 0x1af4
+#define regODM2_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
#define regODM2_OPTC_UNDERFLOW_THRESHOLD 0x1af5
#define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
@@ -8395,6 +8401,8 @@
#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+#define regODM3_OPTC_RSMU_UNDERFLOW 0x1b04
+#define regODM3_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
#define regODM3_OPTC_UNDERFLOW_THRESHOLD 0x1b05
#define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
index 3ffb6ec8b40a..390b164fba5e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
@@ -27326,6 +27326,15 @@
//ODM0_OPTC_INPUT_SPARE_REGISTER
#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+//ODM0_OPTC_RSMU_UNDERFLOW
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
+#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
//ODM0_OPTC_UNDERFLOW_THRESHOLD
#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
@@ -27388,6 +27397,15 @@
//ODM1_OPTC_INPUT_SPARE_REGISTER
#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+//ODM1_OPTC_RSMU_UNDERFLOW
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
+#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
//ODM1_OPTC_UNDERFLOW_THRESHOLD
#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
@@ -27450,6 +27468,15 @@
//ODM2_OPTC_INPUT_SPARE_REGISTER
#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+//ODM2_OPTC_RSMU_UNDERFLOW
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
+#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
//ODM2_OPTC_UNDERFLOW_THRESHOLD
#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
@@ -27512,6 +27539,15 @@
//ODM3_OPTC_INPUT_SPARE_REGISTER
#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+//ODM3_OPTC_RSMU_UNDERFLOW
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
+#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
//ODM3_OPTC_UNDERFLOW_THRESHOLD
#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
--
2.43.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amdgpu: add DCN36 OPTC RSMU underflow registers
2026-10-22 2:56 [PATCH] drm/amdgpu: add DCN36 OPTC RSMU underflow registers Wayne Lin
@ 2026-10-22 4:59 ` Chung, ChiaHsuan (Tom)
0 siblings, 0 replies; 2+ messages in thread
From: Chung, ChiaHsuan (Tom) @ 2026-10-22 4:59 UTC (permalink / raw)
To: Wayne Lin, amd-gfx; +Cc: Alexander Deucher, Harry Wentland, Leo Li
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
On 10/22/2026 10:56 AM, Wayne Lin wrote:
> Expose OPTC RSMU underflow registers of dcn36 for later usage.
>
> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
> Assisted-by: Cursor:Grok 4.7
> ---
> .../include/asic_reg/dcn/dcn_3_6_0_offset.h | 8 +++++
> .../include/asic_reg/dcn/dcn_3_6_0_sh_mask.h | 36 +++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
> index b070f9b91f17..90d624d22b3a 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
> @@ -8329,6 +8329,8 @@
> #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
> #define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
> #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
> +#define regODM0_OPTC_RSMU_UNDERFLOW 0x1ad4
> +#define regODM0_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
> #define regODM0_OPTC_UNDERFLOW_THRESHOLD 0x1ad5
> #define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
>
> @@ -8351,6 +8353,8 @@
> #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
> #define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
> #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
> +#define regODM1_OPTC_RSMU_UNDERFLOW 0x1ae4
> +#define regODM1_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
> #define regODM1_OPTC_UNDERFLOW_THRESHOLD 0x1ae5
> #define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
>
> @@ -8373,6 +8377,8 @@
> #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
> #define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
> #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
> +#define regODM2_OPTC_RSMU_UNDERFLOW 0x1af4
> +#define regODM2_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
> #define regODM2_OPTC_UNDERFLOW_THRESHOLD 0x1af5
> #define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
>
> @@ -8395,6 +8401,8 @@
> #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
> #define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
> #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
> +#define regODM3_OPTC_RSMU_UNDERFLOW 0x1b04
> +#define regODM3_OPTC_RSMU_UNDERFLOW_BASE_IDX 2
> #define regODM3_OPTC_UNDERFLOW_THRESHOLD 0x1b05
> #define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
> index 3ffb6ec8b40a..390b164fba5e 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
> @@ -27326,6 +27326,15 @@
> //ODM0_OPTC_INPUT_SPARE_REGISTER
> #define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
> #define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
> +//ODM0_OPTC_RSMU_UNDERFLOW
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
> +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
> //ODM0_OPTC_UNDERFLOW_THRESHOLD
> #define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
> #define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
> @@ -27388,6 +27397,15 @@
> //ODM1_OPTC_INPUT_SPARE_REGISTER
> #define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
> #define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
> +//ODM1_OPTC_RSMU_UNDERFLOW
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
> +#define ODM1_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
> //ODM1_OPTC_UNDERFLOW_THRESHOLD
> #define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
> #define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
> @@ -27450,6 +27468,15 @@
> //ODM2_OPTC_INPUT_SPARE_REGISTER
> #define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
> #define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
> +//ODM2_OPTC_RSMU_UNDERFLOW
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
> +#define ODM2_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
> //ODM2_OPTC_UNDERFLOW_THRESHOLD
> #define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
> #define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
> @@ -27512,6 +27539,15 @@
> //ODM3_OPTC_INPUT_SPARE_REGISTER
> #define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
> #define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
> +//ODM3_OPTC_RSMU_UNDERFLOW
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L
> +#define ODM3_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L
> //ODM3_OPTC_UNDERFLOW_THRESHOLD
> #define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0
> #define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL
^ permalink raw reply [flat|nested] 2+ messages in thread
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2026-10-22 2:56 [PATCH] drm/amdgpu: add DCN36 OPTC RSMU underflow registers Wayne Lin
2026-10-22 4:59 ` Chung, ChiaHsuan (Tom)
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