[PATCH v11 0/3] arm64: dts: rockchip: add RK3568 XPCS nodes and enable SGMII on Photonicat

[PATCH v11 0/3] arm64: dts: rockchip: add RK3568 XPCS nodes and enable SGMII on Photonicat

[Coia Prant]

This series adds the RK3568 XPCS and fixed-clock nodes, describes the
RGMII PHY LEDs on the Ariaboard Photonicat, and enables the SGMII LAN
port on the same board.

Changes since v10:

- The rockchip,sgmii-mac-sel property on combphy2 is no longer set in
  the Photonicat DTS. The property is tri-state: when absent, the
  driver leaves the routing unchanged. If the bootloader has already
  routed combphy2 SGMII to GMAC0, the link works without the explicit
  property. A follow-up will add it once the PHY binding lands in
  linux-next.

- The RGMII PHY LED configuration is now a separate patch (patch 2).

- The SGMII PHY LED configuration on mdio0 stays in the Photonicat
  patch (patch 3), since it belongs to the port being enabled.

Dependencies:
- XPCS binding and driver (rockchip,rk3568-xpcs, XPCS glue, dwmac-rk
  SGMII, pcs-handle binding): merged in net-next and present in
  linux-next.
  https://git.kernel.org/netdev/net-next/c/5e91edfb0e45

- PHY binding+driver (rockchip,sgmii-mac-sel): still in review on
  linux-phy. Not required for this version to compile or pass
  dtbs_check; only needed for the follow-up that sets the property
  explicitly.

- Generic PM domain (genpd) changes: runtime-only, not a DTS
  dependency.

The XPCS node is disabled by default and only enabled on boards that
use SGMII. The fixed-clock nodes are always present, as they are
static clock sources.

dtbs_check passes with the current linux-next, since the XPCS binding
is already merged.
---
Coia Prant (3):
  arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes
  arm64: dts: rockchip: rk3568-photonicat: add RGMII PHY LEDs
  arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

 .../boot/dts/rockchip/rk3568-photonicat.dts   | 68 ++++++++++++++++++-
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      | 23 +++++++
 2 files changed, 89 insertions(+), 2 deletions(-)

-- 
2.47.3


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[PATCH v11 0/3] arm64: dts: rockchip: add RK3568 XPCS nodes and enable SGMII on Photonicat

[Coia Prant]

This series adds the RK3568 XPCS and fixed-clock nodes, describes the
RGMII PHY LEDs on the Ariaboard Photonicat, and enables the SGMII LAN
port on the same board.

Changes since v10:

- The rockchip,sgmii-mac-sel property on combphy2 is no longer set in
  the Photonicat DTS. The property is tri-state: when absent, the
  driver leaves the routing unchanged. If the bootloader has already
  routed combphy2 SGMII to GMAC0, the link works without the explicit
  property. A follow-up will add it once the PHY binding lands in
  linux-next.

- The RGMII PHY LED configuration is now a separate patch (patch 2).

- The SGMII PHY LED configuration on mdio0 stays in the Photonicat
  patch (patch 3), since it belongs to the port being enabled.

Dependencies:
- XPCS binding and driver (rockchip,rk3568-xpcs, XPCS glue, dwmac-rk
  SGMII, pcs-handle binding): merged in net-next and present in
  linux-next.
  https://git.kernel.org/netdev/net-next/c/5e91edfb0e45

- PHY binding+driver (rockchip,sgmii-mac-sel): still in review on
  linux-phy. Not required for this version to compile or pass
  dtbs_check; only needed for the follow-up that sets the property
  explicitly.

- Generic PM domain (genpd) changes: runtime-only, not a DTS
  dependency.

The XPCS node is disabled by default and only enabled on boards that
use SGMII. The fixed-clock nodes are always present, as they are
static clock sources.

dtbs_check passes with the current linux-next, since the XPCS binding
is already merged.
---
Coia Prant (3):
  arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes
  arm64: dts: rockchip: rk3568-photonicat: add RGMII PHY LEDs
  arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

 .../boot/dts/rockchip/rk3568-photonicat.dts   | 68 ++++++++++++++++++-
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      | 23 +++++++
 2 files changed, 89 insertions(+), 2 deletions(-)

-- 
2.47.3

[PATCH v11 1/3] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes

[Coia Prant]

The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides
the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII
interfaces via its four MII ports.  Add the XPCS device node to the
SoC device tree.

The XPCS device is accessed via the APB3 bus at 0xfda00000 and
requires the CSR clock (PCLK_XPCS) for register access and the EEE
clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation.  The
PD_PIPE power domain must be enabled before any register access.

Also add two fixed-clock nodes (clock-xpcs-gmac0 and clock-xpcs-gmac1,
labelled clk_gmac0_xpcs_mii and clk_gmac1_xpcs_mii) providing the
125 MHz reference clock for the GMACs when operating with XPCS.  Their
clock-output-names match the CRU mux parent names in clk-rk3568.c, so
boards can reparent SCLK_GMAC0_RX_TX / SCLK_GMAC1_RX_TX through
assigned-clock-parents.

The XPCS node is disabled by default and must be enabled at the board
level when 1000BASE-X/SGMII/QSGMII is in use.  The fixed-clock nodes
are always present and do not have a status property, as they are
static clock sources.

The XPCS node requires a reference to the appropriate Naneng Combo PHY
via the phys property.  dtbs_check only validates required properties
for enabled nodes, so the SoC dtsi does not provide phys: boards that
enable the XPCS must supply it, since the SerDes link is a board-level
design choice (combphy1 on some boards, combphy2 on others).

Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 3bc653f027f1f..20a72785adbc2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,20 @@
 / {
 	compatible = "rockchip,rk3568";
 
+	clk_gmac0_xpcs_mii: clock-xpcs-gmac0 {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac0_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	clk_gmac1_xpcs_mii: clock-xpcs-gmac1 {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac1_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
 	cpu0_opp_table: opp-table-0 {
 		compatible = "operating-points-v2";
 		opp-shared;
@@ -110,6 +124,15 @@ sata0: sata@fc000000 {
 		status = "disabled";
 	};
 
+	xpcs: ethernet-pcs@fda00000 {
+		compatible = "rockchip,rk3568-xpcs";
+		reg = <0x0 0xfda00000 0x0 0x200000>;
+		clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
+		clock-names = "csr", "eee";
+		power-domains = <&power RK3568_PD_PIPE>;
+		status = "disabled";
+	};
+
 	pipe_phy_grf0: syscon@fdc70000 {
 		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfdc70000 0x0 0x1000>;
-- 
2.47.3

[PATCH v11 1/3] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes

[Coia Prant]

The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides
the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII
interfaces via its four MII ports.  Add the XPCS device node to the
SoC device tree.

The XPCS device is accessed via the APB3 bus at 0xfda00000 and
requires the CSR clock (PCLK_XPCS) for register access and the EEE
clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation.  The
PD_PIPE power domain must be enabled before any register access.

Also add two fixed-clock nodes (clock-xpcs-gmac0 and clock-xpcs-gmac1,
labelled clk_gmac0_xpcs_mii and clk_gmac1_xpcs_mii) providing the
125 MHz reference clock for the GMACs when operating with XPCS.  Their
clock-output-names match the CRU mux parent names in clk-rk3568.c, so
boards can reparent SCLK_GMAC0_RX_TX / SCLK_GMAC1_RX_TX through
assigned-clock-parents.

The XPCS node is disabled by default and must be enabled at the board
level when 1000BASE-X/SGMII/QSGMII is in use.  The fixed-clock nodes
are always present and do not have a status property, as they are
static clock sources.

The XPCS node requires a reference to the appropriate Naneng Combo PHY
via the phys property.  dtbs_check only validates required properties
for enabled nodes, so the SoC dtsi does not provide phys: boards that
enable the XPCS must supply it, since the SerDes link is a board-level
design choice (combphy1 on some boards, combphy2 on others).

Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 3bc653f027f1f..20a72785adbc2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,20 @@
 / {
 	compatible = "rockchip,rk3568";
 
+	clk_gmac0_xpcs_mii: clock-xpcs-gmac0 {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac0_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	clk_gmac1_xpcs_mii: clock-xpcs-gmac1 {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac1_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
 	cpu0_opp_table: opp-table-0 {
 		compatible = "operating-points-v2";
 		opp-shared;
@@ -110,6 +124,15 @@ sata0: sata@fc000000 {
 		status = "disabled";
 	};
 
+	xpcs: ethernet-pcs@fda00000 {
+		compatible = "rockchip,rk3568-xpcs";
+		reg = <0x0 0xfda00000 0x0 0x200000>;
+		clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
+		clock-names = "csr", "eee";
+		power-domains = <&power RK3568_PD_PIPE>;
+		status = "disabled";
+	};
+
 	pipe_phy_grf0: syscon@fdc70000 {
 		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfdc70000 0x0 0x1000>;
-- 
2.47.3


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[PATCH v11 2/3] arm64: dts: rockchip: rk3568-photonicat: add RGMII PHY LEDs

[Coia Prant]

The Motorcomm YT8521SC RGMII PHY on the Ariaboard Photonicat has two
front-panel LEDs wired to it. Describe them in the device tree so that
userspace can control and monitor them through the LED class.

Both LEDs use the "keep" default state, so the PHY's built-in LED
behaviour is preserved until userspace overrides the trigger.

Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
 .../boot/dts/rockchip/rk3568-photonicat.dts   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
index 58c1052ba8ef3..12ae9159bea87 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
@@ -350,6 +351,25 @@ rgmii_phy: ethernet-phy@3 {
 		reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
 		rx-internal-delay-ps = <1500>;
 		tx-internal-delay-ps = <1500>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_AMBER>;
+				function = LED_FUNCTION_WAN;
+				default-state = "keep";
+			};
+
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_WAN;
+				default-state = "keep";
+			};
+		};
 	};
 };
 
-- 
2.47.3


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[PATCH v11 2/3] arm64: dts: rockchip: rk3568-photonicat: add RGMII PHY LEDs

[Coia Prant]

The Motorcomm YT8521SC RGMII PHY on the Ariaboard Photonicat has two
front-panel LEDs wired to it. Describe them in the device tree so that
userspace can control and monitor them through the LED class.

Both LEDs use the "keep" default state, so the PHY's built-in LED
behaviour is preserved until userspace overrides the trigger.

Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
 .../boot/dts/rockchip/rk3568-photonicat.dts   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
index 58c1052ba8ef3..12ae9159bea87 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
@@ -350,6 +351,25 @@ rgmii_phy: ethernet-phy@3 {
 		reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
 		rx-internal-delay-ps = <1500>;
 		tx-internal-delay-ps = <1500>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_AMBER>;
+				function = LED_FUNCTION_WAN;
+				default-state = "keep";
+			};
+
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_WAN;
+				default-state = "keep";
+			};
+		};
 	};
 };
 
-- 
2.47.3

[PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Coia Prant]

The Ariaboard Photonicat has a Motorcomm YT8521SC Gigabit Ethernet PHY
connected to GMAC0 via XPCS SGMII.  Enable the necessary nodes to make
this port functional.

Enable the xpcs node, referencing combphy2 as the SerDes PHY.

The rockchip,sgmii-mac-sel property on combphy2 is not set here.  The
property is tri-state: when absent, the driver leaves the routing
unchanged.  If the bootloader has already routed combphy2 SGMII to
GMAC0, the link works without the explicit property.  A follow-up will
add rockchip,sgmii-mac-sel = <0> once the PHY binding lands in
linux-next, removing the dependency on the bootloader default.

RK3568 has three Combo PHYs that can carry SGMII; which one is wired
to the XPCS is a board-level choice, and Photonicat uses combphy2.

Add the mdio0 node with the YT8521SC PHY at address 3, including its
reset GPIO and LED configuration.

Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
 .../boot/dts/rockchip/rk3568-photonicat.dts   | 48 ++++++++++++++++++-
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
index 12ae9159bea87..d9015dbfb9f5c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
@@ -261,9 +261,18 @@ &cpu3 {
 	cpu-supply = <&vdd_cpu>;
 };
 
-/* Motorcomm YT8521SC LAN port (require SGMII) */
+/* Motorcomm YT8521SC LAN port */
 &gmac0 {
-	status = "disabled";
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
+	assigned-clock-parents = <&clk_gmac0_xpcs_mii>;
+	managed = "in-band-status";
+	pcs-handle = <&xpcs>;
+	phy-handle = <&sgmii_phy>;
+	phy-mode = "sgmii";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim>;
+	status = "okay";
 };
 
 /* Motorcomm YT8521SC WAN port */
@@ -342,6 +351,36 @@ &i2s0_8ch {
 	status = "okay";
 };
 
+&mdio0 {
+	sgmii_phy: ethernet-phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x3>;
+		max-speed = <1000>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_AMBER>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+		};
+	};
+};
+
 &mdio1 {
 	rgmii_phy: ethernet-phy@3 {
 		compatible = "ethernet-phy-ieee802.3-c22";
@@ -606,3 +645,8 @@ &xin32k {
 	pinctrl-names = "default";
 	pinctrl-0 = <&clk32k_out1>;
 };
+
+&xpcs {
+	phys = <&combphy2 PHY_TYPE_SGMII>;
+	status = "okay";
+};
-- 
2.47.3


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[PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Coia Prant]

The Ariaboard Photonicat has a Motorcomm YT8521SC Gigabit Ethernet PHY
connected to GMAC0 via XPCS SGMII.  Enable the necessary nodes to make
this port functional.

Enable the xpcs node, referencing combphy2 as the SerDes PHY.

The rockchip,sgmii-mac-sel property on combphy2 is not set here.  The
property is tri-state: when absent, the driver leaves the routing
unchanged.  If the bootloader has already routed combphy2 SGMII to
GMAC0, the link works without the explicit property.  A follow-up will
add rockchip,sgmii-mac-sel = <0> once the PHY binding lands in
linux-next, removing the dependency on the bootloader default.

RK3568 has three Combo PHYs that can carry SGMII; which one is wired
to the XPCS is a board-level choice, and Photonicat uses combphy2.

Add the mdio0 node with the YT8521SC PHY at address 3, including its
reset GPIO and LED configuration.

Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
 .../boot/dts/rockchip/rk3568-photonicat.dts   | 48 ++++++++++++++++++-
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
index 12ae9159bea87..d9015dbfb9f5c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
@@ -261,9 +261,18 @@ &cpu3 {
 	cpu-supply = <&vdd_cpu>;
 };
 
-/* Motorcomm YT8521SC LAN port (require SGMII) */
+/* Motorcomm YT8521SC LAN port */
 &gmac0 {
-	status = "disabled";
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
+	assigned-clock-parents = <&clk_gmac0_xpcs_mii>;
+	managed = "in-band-status";
+	pcs-handle = <&xpcs>;
+	phy-handle = <&sgmii_phy>;
+	phy-mode = "sgmii";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim>;
+	status = "okay";
 };
 
 /* Motorcomm YT8521SC WAN port */
@@ -342,6 +351,36 @@ &i2s0_8ch {
 	status = "okay";
 };
 
+&mdio0 {
+	sgmii_phy: ethernet-phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x3>;
+		max-speed = <1000>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_AMBER>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+		};
+	};
+};
+
 &mdio1 {
 	rgmii_phy: ethernet-phy@3 {
 		compatible = "ethernet-phy-ieee802.3-c22";
@@ -606,3 +645,8 @@ &xin32k {
 	pinctrl-names = "default";
 	pinctrl-0 = <&clk32k_out1>;
 };
+
+&xpcs {
+	phys = <&combphy2 PHY_TYPE_SGMII>;
+	status = "okay";
+};
-- 
2.47.3

Re: [PATCH v11 1/3] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: rockchip: undocumented rockchip,rk3568-xpcs compatible in rk3568.dtsi
--

commit b8b1e0bef5d9409b92ce95305440fbc54a7eeb87
Author: Coia Prant <coiaprant@gmail.com>

arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes

This commit adds the Synopsys DesignWare xpcs node and two 125 MHz fixed-clock
nodes for the gmac interfaces to the rk3568 SoC device tree.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2f42bf26fd9bf..b1ea84ba86e40 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi

[ ... ]

> @@ -110,6 +124,15 @@ sata0: sata@fc000000 {
>  		status = "disabled";
>  	};
>  
> +	xpcs: ethernet-pcs@fda00000 {
> +		compatible = "rockchip,rk3568-xpcs";
> +		reg = <0x0 0xfda00000 0x0 0x200000>;
> +		clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
> +		clock-names = "csr", "eee";
> +		power-domains = <&power RK3568_PD_PIPE>;
> +		status = "disabled";
> +	};

[Severity: Medium]
Does adding the xpcs node (ethernet-pcs@fda00000) with compatible =
"rockchip,rk3568-xpcs" in arch/arm64/boot/dts/rockchip/rk3568.dtsi cause a
dtbs_check regression for rk3568 device trees?

While the commit message notes that dtbs_check skips required property checks
for disabled nodes, scripts/Makefile.dtbs invokes dt-validate with -m by
default:

scripts/Makefile.dtbs:
    DT_CHECKER ?= dt-validate
    DT_CHECKER_FLAGS ?= $(if $(DT_SCHEMA_FILES),-l $(DT_SCHEMA_FILES),-m)

When running dtbs_check on any rk3568 target, dt-validate checks compatible
strings on all nodes regardless of status = "disabled" and fails because
"rockchip,rk3568-xpcs" is not documented under
Documentation/devicetree/bindings/.

In addition, the upstream DesignWare xpcs binding in
Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml and platform
driver in drivers/net/pcs/pcs-xpcs-plat.c (xpcs_of_ids[]) only match the
snps,dw-xpcs* compatibles:

drivers/net/pcs/pcs-xpcs-plat.c:
    static const struct of_device_id xpcs_of_ids[] = {
        { .compatible = "snps,dw-xpcs", .data = &xpcs_generic },
        { .compatible = "snps,dw-xpcs-gen1-3g", .data = &xpcs_pma_gen1_3g },
        ...
    };

Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml also restricts
clock-names to "csr", "core", and "pad" (without "eee"), requires reg-names
("direct" or "indirect") for memory-mapped instances, sets
additionalProperties: false, and does not define power-domains or phys, nor
does drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c handle pcs-handle.

Should the "rockchip,rk3568-xpcs" binding schema and driver support be added
before introducing this node and enabling it on boards such as
rk3568-photonicat.dts?

> +
>  	pipe_phy_grf0: syscon@fdc70000 {
>  		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
>  		reg = <0x0 0xfdc70000 0x0 0x1000>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022025844.150320-1-coiaprant@gmail.com?part=1

Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] arm64: dts: rockchip: gmac0 SGMII probe failure in rk_gmac_powerup()
- [High] arm64: dts: rockchip: missing driver and DT binding for rk3568-xpcs
--

commit aa6d6fc31ff0de23e03fbaf6018d2105111972d7
Author: Coia Prant <coiaprant@gmail.com>

arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

This commit enables the gmac0 and xpcs nodes on the Ariaboard Photonicat
board to support its Motorcomm YT8521SC Ethernet PHY over SGMII via
combphy2, and adds the PHY and LED definitions under mdio0.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
> index 12ae9159bea87..d9015dbfb9f5c 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
> @@ -261,9 +261,18 @@ &cpu3 {
>  	cpu-supply = <&vdd_cpu>;
>  };
>  
> -/* Motorcomm YT8521SC LAN port (require SGMII) */
> +/* Motorcomm YT8521SC LAN port */
>  &gmac0 {
> -	status = "disabled";
> +	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
> +	assigned-clock-parents = <&clk_gmac0_xpcs_mii>;
> +	managed = "in-band-status";
> +	pcs-handle = <&xpcs>;
> +	phy-handle = <&sgmii_phy>;
> +	phy-mode = "sgmii";
> +	phy-supply = <&vcc_3v3>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac0_miim>;
> +	status = "okay";
>  };

[Severity: High]
When gmac0 probes with phy-mode = "sgmii", the call chain
rk_gmac_probe() -> devm_stmmac_pltfr_probe() -> stmmac_dvr_probe() ->
rk_gmac_init() -> rk_gmac_powerup() in
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c validates the PHY interface
through rk_gmac_check_ops() and rk_get_phy_intf_sel():

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c:rk_gmac_check_ops() {
	switch (bsp_priv->phy_iface) {
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		if (!bsp_priv->supports_rgmii)
			return -EINVAL;
		break;
	case PHY_INTERFACE_MODE_RMII:
		if (!bsp_priv->supports_rmii)
			return -EINVAL;
		break;
	default:
		dev_err(bsp_priv->dev,
			"unsupported interface %d", bsp_priv->phy_iface);
	}
	return 0;
}

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c:rk_get_phy_intf_sel() {
	int ret = stmmac_get_phy_intf_sel(interface);

	/* Only RGMII and RMII are supported */
	if (ret != PHY_INTF_SEL_RGMII && ret != PHY_INTF_SEL_RMII)
		ret = -EINVAL;

	return ret;
}

In addition, rk_get_interfaces() only sets RGMII and RMII in phylink's
supported_interfaces, and dwmac-rk.c does not parse pcs-handle or populate
plat_dat->pcs_init / plat_dat->select_pcs to attach an XPCS instance.

Will enabling gmac0 with phy-mode = "sgmii" and pcs-handle = <&xpcs> cause
rk_gmac_powerup() to fail probe with -EINVAL before mdio0 or the network
interface can be registered?

[ ... ]

> @@ -606,3 +645,8 @@ &xin32k {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&clk32k_out1>;
>  };
> +
> +&xpcs {
> +	phys = <&combphy2 PHY_TYPE_SGMII>;
> +	status = "okay";
> +};

[Severity: High]
In arch/arm64/boot/dts/rockchip/rk3568.dtsi, the xpcs node is defined as:

	xpcs: ethernet-pcs@fda00000 {
		compatible = "rockchip,rk3568-xpcs";
		reg = <0x0 0xfda00000 0x0 0x200000>;
		clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
		clock-names = "csr", "eee";
		power-domains = <&power RK3568_PD_PIPE>;
		status = "disabled";
	};

Looking at xpcs_of_ids[] in drivers/net/pcs/pcs-xpcs-plat.c, only
"snps,dw-xpcs*" compatibles are matched, and no driver in the tree matches
"rockchip,rk3568-xpcs" or handles its "eee" clock and phys properties.

When rockchip_combphy_probe() in
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c probes combphy2, it
asserts the PHY reset line:

	ret = reset_control_assert(priv->phy_rst);
	if (ret) {
		dev_err(dev, "failed to reset phy\n");
		return ret;
	}

That reset is only deasserted when a consumer driver calls phy_init() ->
rockchip_combphy_init(). Furthermore, Documentation/devicetree/bindings/
(including Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml)
does not document "rockchip,rk3568-xpcs" or the phys, power-domains, and
"eee" clock properties on this node.

Could enabling &xpcs before the driver and binding schema for
"rockchip,rk3568-xpcs" are present leave combphy2 held in hardware reset and
introduce dtbs_check regressions?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022025844.150320-1-coiaprant@gmail.com?part=3

Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Andrew Lunn]

> +	sgmii_phy: ethernet-phy@3 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0x3>;
> +		max-speed = <1000>;

Pointless. SGMII cannot do faster, so there is no need to limit it.

	Andrew

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Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Andrew Lunn]

> +	sgmii_phy: ethernet-phy@3 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0x3>;
> +		max-speed = <1000>;

Pointless. SGMII cannot do faster, so there is no need to limit it.

	Andrew

Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Coia Prant]

Andrew Lunn <andrew@lunn.ch> 于2026年10月23日周五 00:58写道：
>
> > +     sgmii_phy: ethernet-phy@3 {
> > +             compatible = "ethernet-phy-ieee802.3-c22";
> > +             reg = <0x3>;
> > +             max-speed = <1000>;
>
> Pointless. SGMII cannot do faster, so there is no need to limit it.
>
>         Andrew

Hi Andrew,

Right, SGMII tops out at 1000Mbps anyway. Dropping max-speed.

Coia

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Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Coia Prant]

Andrew Lunn <andrew@lunn.ch> 于2026年10月23日周五 00:58写道：
>
> > +     sgmii_phy: ethernet-phy@3 {
> > +             compatible = "ethernet-phy-ieee802.3-c22";
> > +             reg = <0x3>;
> > +             max-speed = <1000>;
>
> Pointless. SGMII cannot do faster, so there is no need to limit it.
>
>         Andrew

Hi Andrew,

Right, SGMII tops out at 1000Mbps anyway. Dropping max-speed.

Coia

Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[David Heidelberg]

On 22/10/2026 18:58, Andrew Lunn wrote:
>> +	sgmii_phy: ethernet-phy@3 {
>> +		compatible = "ethernet-phy-ieee802.3-c22";
>> +		reg = <0x3>;
>> +		max-speed = <1000>;
> 
> Pointless. SGMII cannot do faster, so there is no need to limit it.

device-tree is a description. whatever the device can do should be there,

"Maximum PHY supported speed in Mbits / seconds." thus 1000 is correct value.

thus max-speed <1000>; LGTM

David

> 
> 	Andrew


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Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[David Heidelberg]

On 22/10/2026 18:58, Andrew Lunn wrote:
>> +	sgmii_phy: ethernet-phy@3 {
>> +		compatible = "ethernet-phy-ieee802.3-c22";
>> +		reg = <0x3>;
>> +		max-speed = <1000>;
> 
> Pointless. SGMII cannot do faster, so there is no need to limit it.

device-tree is a description. whatever the device can do should be there,

"Maximum PHY supported speed in Mbits / seconds." thus 1000 is correct value.

thus max-speed <1000>; LGTM

David

> 
> 	Andrew

Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Andrew Lunn]

On Thu, Oct 22, 2026 at 07:13:06PM +0200, David Heidelberg wrote:
> On 22/10/2026 18:58, Andrew Lunn wrote:
> > > +	sgmii_phy: ethernet-phy@3 {
> > > +		compatible = "ethernet-phy-ieee802.3-c22";
> > > +		reg = <0x3>;
> > > +		max-speed = <1000>;
> > 
> > Pointless. SGMII cannot do faster, so there is no need to limit it.
> 
> device-tree is a description. whatever the device can do should be there,
> 
> "Maximum PHY supported speed in Mbits / seconds." thus 1000 is correct value.
> 
> thus max-speed <1000>; LGTM

I did not say it was wrong. I said it was pointless. The PHY will
report what it can support, which will be speeds up to 1G for an SGMII
PHY. The max-speed property will then be applied, and does nothing,
making it pointless.

max-speed is interesting when you have an odd design, like only 2 of
the 4 pairs are actually connect to the RJ-45 socket, limiting the
media to 100Mbps. Using max-speed in this situation will remove the 1G
speeds from the supported list, and so it will not try to negotiate
such a link, which will probably be successful, but then data transfer
will fail. If the PHY supports downshift, it will then drop to
100Mbps, but it can be confusing because everything says it should be
doing 1G, but in practice it does 100MBs, or nothing.

      Andrew

Re: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port

[Andrew Lunn]

On Thu, Oct 22, 2026 at 07:13:06PM +0200, David Heidelberg wrote:
> On 22/10/2026 18:58, Andrew Lunn wrote:
> > > +	sgmii_phy: ethernet-phy@3 {
> > > +		compatible = "ethernet-phy-ieee802.3-c22";
> > > +		reg = <0x3>;
> > > +		max-speed = <1000>;
> > 
> > Pointless. SGMII cannot do faster, so there is no need to limit it.
> 
> device-tree is a description. whatever the device can do should be there,
> 
> "Maximum PHY supported speed in Mbits / seconds." thus 1000 is correct value.
> 
> thus max-speed <1000>; LGTM

I did not say it was wrong. I said it was pointless. The PHY will
report what it can support, which will be speeds up to 1G for an SGMII
PHY. The max-speed property will then be applied, and does nothing,
making it pointless.

max-speed is interesting when you have an odd design, like only 2 of
the 4 pairs are actually connect to the RJ-45 socket, limiting the
media to 100Mbps. Using max-speed in this situation will remove the 1G
speeds from the supported list, and so it will not try to negotiate
such a link, which will probably be successful, but then data transfer
will fail. If the PHY supports downshift, it will then drop to
100Mbps, but it can be confusing because everything says it should be
doing 1G, but in practice it does 100MBs, or nothing.

      Andrew

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