[PATCH v2 01/15] drm/amdgpu/gfx: add a reset_engine callback

[Jesse Zhang <Jesse.Zhang@amd.com>]

Some gfx hangs can't be recovered by a queue or a pipe reset, eg. a CP
front-end stuck in the middle of a packet. They currently end in a full
GPU reset, and VRAM is lost. Resetting only the graphics engine is
enough for them, and leaves the compute engine running.

Add an optional reset_engine callback to amdgpu_gfx_funcs that resets
only the graphics or only the compute engine. The split is specific to
the GFX IP, eg. CP_SOFT_RESET_CNTL has GFX_ONLY_SOFT_RESET and
CMP_ONLY_SOFT_RESET, so it doesn't belong in the amd_ip_funcs that all
IP blocks share.

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 5939e1fb3b24..8dc669e89db5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -345,6 +345,13 @@ struct amdgpu_gfx_shadow_info {
 	u32 eop_alignment;
 };
 
+/* The engines of the GFX IP that can be reset on their own. */
+enum amdgpu_gfx_engine {
+	AMDGPU_GFX_ENGINE_GFX,
+	AMDGPU_GFX_ENGINE_COMPUTE,
+	AMDGPU_GFX_ENGINE_NUM,
+};
+
 struct amdgpu_gfx_funcs {
 	/* get the gpu clock counter */
 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
@@ -376,6 +383,9 @@ struct amdgpu_gfx_funcs {
 	/* find the gfx HQD slot (me/pipe/queue) for a doorbell */
 	bool (*detect_hung_queue)(struct amdgpu_device *adev, u32 doorbell_index,
 				  u32 *me, u32 *pipe, u32 *queue);
+	/* reset one engine, leaving the other one running */
+	int (*reset_engine)(struct amdgpu_device *adev,
+			    enum amdgpu_gfx_engine engine);
 };
 
 struct sq_work {
-- 
2.50.1