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From: Andrew Jones <andrew.jones@linux.dev>
To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev
Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com,
	fangyu.yu@linux.alibaba.com, nutty.liu@hotmail.com
Subject: [PATCH v7 2/5] iommu/dma: Introduce iommu_dma_prepare_msi_list()
Date: Thu, 22 Oct 2026 17:46:00 +0200	[thread overview]
Message-ID: <20261022154603.1374754-3-andrew.jones@linux.dev> (raw)
In-Reply-To: <20261022154603.1374754-1-andrew.jones@linux.dev>

IMSIC needs an interface to prepare all MSI targets before an IRQ
affinity change can select one in atomic context.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
---
 drivers/iommu/iommu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/iommu.h |  9 +++++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index b486b8bbd1fc..b8d4d601efd4 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -4266,4 +4266,47 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
 	mutex_unlock(&group->mutex);
 	return ret;
 }
+
+/**
+ * iommu_dma_prepare_msi_list() - Map the complete list of MSI targets
+ * @desc: MSI descriptor to receive the base IOVA and granule shift
+ * @phys_addrs: Ordered array of target physical addresses
+ * @nr_addrs: Number of targets in the array
+ * @granule: Size and alignment of each target mapping
+ *
+ * Every call for a DMA domain must supply the same complete list, order and
+ * granule. The first call maps the targets into one contiguous IOVA range;
+ * subsequent calls use the cached base. The array is consumed synchronously
+ * and is not retained.
+ *
+ * Each target must be aligned to @granule, which must match the DMA domain's
+ * granule and be at least PAGE_SIZE.
+ *
+ * Without a translated domain, @desc is left unchanged. Only DMA-IOMMU
+ * domains currently support translated MSI target lists.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *phys_addrs,
+			       unsigned int nr_addrs, size_t granule)
+{
+	struct device *dev = msi_desc_to_dev(desc);
+	struct iommu_group *group = dev->iommu_group;
+	struct iommu_domain *domain;
+	int ret;
+
+	if (!group)
+		return 0;
+
+	ret = iommu_deferred_attach(dev, iommu_get_domain_for_dev(dev));
+	if (ret)
+		return ret;
+
+	guard(mutex)(&group->mutex);
+	domain = group->domain;
+	if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
+		return 0;
+
+	return iommu_dma_sw_msi_list(domain, desc, phys_addrs, nr_addrs, granule);
+}
 #endif /* CONFIG_IRQ_MSI_IOMMU */
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 95e32c78dcb7..cf33169ec3e3 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -1560,12 +1560,21 @@ static inline void pci_dev_reset_iommu_done(struct pci_dev *pdev)
 #ifdef CONFIG_IRQ_MSI_IOMMU
 #ifdef CONFIG_IOMMU_API
 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
+int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *phys_addrs,
+			       unsigned int nr_addrs, size_t granule);
 #else
 static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
 					phys_addr_t msi_addr)
 {
 	return 0;
 }
+
+static inline int iommu_dma_prepare_msi_list(struct msi_desc *desc,
+					     const phys_addr_t *phys_addrs,
+					     unsigned int nr_addrs, size_t granule)
+{
+	return 0;
+}
 #endif /* CONFIG_IOMMU_API */
 #endif /* CONFIG_IRQ_MSI_IOMMU */
 
-- 
2.56.0


WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <andrew.jones@linux.dev>
To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev
Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com,
	fangyu.yu@linux.alibaba.com, nutty.liu@hotmail.com
Subject: [PATCH v7 2/5] iommu/dma: Introduce iommu_dma_prepare_msi_list()
Date: Thu, 22 Oct 2026 17:46:00 +0200	[thread overview]
Message-ID: <20261022154603.1374754-3-andrew.jones@linux.dev> (raw)
In-Reply-To: <20261022154603.1374754-1-andrew.jones@linux.dev>

IMSIC needs an interface to prepare all MSI targets before an IRQ
affinity change can select one in atomic context.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
---
 drivers/iommu/iommu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/iommu.h |  9 +++++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index b486b8bbd1fc..b8d4d601efd4 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -4266,4 +4266,47 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
 	mutex_unlock(&group->mutex);
 	return ret;
 }
+
+/**
+ * iommu_dma_prepare_msi_list() - Map the complete list of MSI targets
+ * @desc: MSI descriptor to receive the base IOVA and granule shift
+ * @phys_addrs: Ordered array of target physical addresses
+ * @nr_addrs: Number of targets in the array
+ * @granule: Size and alignment of each target mapping
+ *
+ * Every call for a DMA domain must supply the same complete list, order and
+ * granule. The first call maps the targets into one contiguous IOVA range;
+ * subsequent calls use the cached base. The array is consumed synchronously
+ * and is not retained.
+ *
+ * Each target must be aligned to @granule, which must match the DMA domain's
+ * granule and be at least PAGE_SIZE.
+ *
+ * Without a translated domain, @desc is left unchanged. Only DMA-IOMMU
+ * domains currently support translated MSI target lists.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *phys_addrs,
+			       unsigned int nr_addrs, size_t granule)
+{
+	struct device *dev = msi_desc_to_dev(desc);
+	struct iommu_group *group = dev->iommu_group;
+	struct iommu_domain *domain;
+	int ret;
+
+	if (!group)
+		return 0;
+
+	ret = iommu_deferred_attach(dev, iommu_get_domain_for_dev(dev));
+	if (ret)
+		return ret;
+
+	guard(mutex)(&group->mutex);
+	domain = group->domain;
+	if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
+		return 0;
+
+	return iommu_dma_sw_msi_list(domain, desc, phys_addrs, nr_addrs, granule);
+}
 #endif /* CONFIG_IRQ_MSI_IOMMU */
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 95e32c78dcb7..cf33169ec3e3 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -1560,12 +1560,21 @@ static inline void pci_dev_reset_iommu_done(struct pci_dev *pdev)
 #ifdef CONFIG_IRQ_MSI_IOMMU
 #ifdef CONFIG_IOMMU_API
 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
+int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *phys_addrs,
+			       unsigned int nr_addrs, size_t granule);
 #else
 static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
 					phys_addr_t msi_addr)
 {
 	return 0;
 }
+
+static inline int iommu_dma_prepare_msi_list(struct msi_desc *desc,
+					     const phys_addr_t *phys_addrs,
+					     unsigned int nr_addrs, size_t granule)
+{
+	return 0;
+}
 #endif /* CONFIG_IOMMU_API */
 #endif /* CONFIG_IRQ_MSI_IOMMU */
 
-- 
2.56.0


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  parent reply	other threads:[~2026-10-22 15:46 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-22 15:45 [PATCH v7 0/5] iommu/riscv: Enable MSI remapping and IOMMU_DMA Andrew Jones
2026-10-22 15:45 ` Andrew Jones
2026-10-22 15:45 ` [PATCH v7 1/5] iommu/dma: Prepare MSI physical address lists Andrew Jones
2026-10-22 15:45   ` Andrew Jones
2026-10-22 15:46 ` Andrew Jones [this message]
2026-10-22 15:46   ` [PATCH v7 2/5] iommu/dma: Introduce iommu_dma_prepare_msi_list() Andrew Jones
2026-10-22 15:46 ` [PATCH v7 3/5] irqchip/riscv-imsic: Add MSI address list Andrew Jones
2026-10-22 15:46   ` Andrew Jones
2026-10-22 15:46 ` [PATCH v7 4/5] irqchip/riscv-imsic: Support IOMMU MSI address lists Andrew Jones
2026-10-22 15:46   ` Andrew Jones
2026-10-22 15:46 ` [PATCH v7 5/5] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Andrew Jones
2026-10-22 15:46   ` Andrew Jones

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