[cilium:jit-arm64 16/26] arch/arm64/net/bpf_jit_comp.c:140:22: sparse: sparse: cast truncates bits from constant value (ffff0000 becomes 0)

[cilium:jit-arm64 16/26] arch/arm64/net/bpf_jit_comp.c:140:22: sparse: sparse: cast truncates bits from constant value (ffff0000 becomes 0)

[kernel test robot]

tree:   https://github.com/cilium/linux.git jit-arm64
head:   7392504323b30f65cc4558a1580250a11ee5dafd
commit: b1a0a44fcf6d15126bfa547f85cd9c98b1b8b8d1 [16/26] bpf, arm64: Use a move or mvn for the and and xor with all ones
config: arm64-randconfig-r2305-20261027 (https://download.01.org/0day-ci/archive/20261027/202610270444.263OivX5-lkp@intel.com/config)
compiler: clang version 24.0.0git (https://github.com/llvm/llvm-project 42d4451d86c175b745d6ea1c4081787994c7259b)
rustc: rustc 1.96.0 (ac68faa20 2026-05-25)
sparse: v0.6.5-rc1-1-gc4640450
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261027/202610270444.263OivX5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202610270444.263OivX5-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> arch/arm64/net/bpf_jit_comp.c:140:22: sparse: sparse: cast truncates bits from constant value (ffff0000 becomes 0)
   arch/arm64/net/bpf_jit_comp.c:153:22: sparse: sparse: cast truncates bits from constant value (ffff0000 becomes 0)
   arch/arm64/net/bpf_jit_comp.c:164:22: sparse: sparse: cast truncates bits from constant value (ffff0000 becomes 0)

vim +140 arch/arm64/net/bpf_jit_comp.c

710618c760c0a32 Puranjay Mohan  2025-08-01  125  
cac96d79e60eec8 Daniel Borkmann 2026-10-17  126  /*
cac96d79e60eec8 Daniel Borkmann 2026-10-17  127   * A 32-bit immediate, sign extended for the 64-bit variant: a single movz
cac96d79e60eec8 Daniel Borkmann 2026-10-17  128   * or movn when one half is zero or all ones and the other half agrees with
cac96d79e60eec8 Daniel Borkmann 2026-10-17  129   * the sign the 64-bit variant extends, a single orr when it is a bitmask
cac96d79e60eec8 Daniel Borkmann 2026-10-17  130   * immediate, and the pair of a movz or movn with a movk otherwise.
cac96d79e60eec8 Daniel Borkmann 2026-10-17  131   */
e54bcde3d69d400 Zi Shen Lim     2014-08-26  132  static inline void emit_a64_mov_i(const int is64, const int reg,
e54bcde3d69d400 Zi Shen Lim     2014-08-26  133  				  const s32 val, struct jit_ctx *ctx)
e54bcde3d69d400 Zi Shen Lim     2014-08-26  134  {
e54bcde3d69d400 Zi Shen Lim     2014-08-26  135  	u16 hi = val >> 16;
e54bcde3d69d400 Zi Shen Lim     2014-08-26  136  	u16 lo = val & 0xffff;
cac96d79e60eec8 Daniel Borkmann 2026-10-17  137  	u32 insn;
e54bcde3d69d400 Zi Shen Lim     2014-08-26  138  
e54bcde3d69d400 Zi Shen Lim     2014-08-26  139  	if (hi == 0xffff) {
e54bcde3d69d400 Zi Shen Lim     2014-08-26 @140  		emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  141  		return;
cac96d79e60eec8 Daniel Borkmann 2026-10-17  142  	}
cac96d79e60eec8 Daniel Borkmann 2026-10-17  143  	if (!hi) {
cac96d79e60eec8 Daniel Borkmann 2026-10-17  144  		emit(A64_MOVZ(is64, reg, lo, 0), ctx);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  145  		return;
cac96d79e60eec8 Daniel Borkmann 2026-10-17  146  	}
cac96d79e60eec8 Daniel Borkmann 2026-10-17  147  	/* The 64-bit variant has the upper half set or clear with the sign */
cac96d79e60eec8 Daniel Borkmann 2026-10-17  148  	if (!lo && (!is64 || !(hi & 0x8000))) {
cac96d79e60eec8 Daniel Borkmann 2026-10-17  149  		emit(A64_MOVZ(is64, reg, hi, 16), ctx);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  150  		return;
cac96d79e60eec8 Daniel Borkmann 2026-10-17  151  	}
cac96d79e60eec8 Daniel Borkmann 2026-10-17  152  	if (lo == 0xffff && (!is64 || (hi & 0x8000))) {
e54bcde3d69d400 Zi Shen Lim     2014-08-26  153  		emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  154  		return;
cac96d79e60eec8 Daniel Borkmann 2026-10-17  155  	}
cac96d79e60eec8 Daniel Borkmann 2026-10-17  156  
cac96d79e60eec8 Daniel Borkmann 2026-10-17  157  	insn = A64_ORR_I(is64, reg, A64_ZR, val);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  158  	if (insn != AARCH64_BREAK_FAULT) {
cac96d79e60eec8 Daniel Borkmann 2026-10-17  159  		emit(insn, ctx);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  160  		return;
e54bcde3d69d400 Zi Shen Lim     2014-08-26  161  	}
cac96d79e60eec8 Daniel Borkmann 2026-10-17  162  
cac96d79e60eec8 Daniel Borkmann 2026-10-17  163  	if (hi & 0x8000) {
cac96d79e60eec8 Daniel Borkmann 2026-10-17  164  		emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx);
cac96d79e60eec8 Daniel Borkmann 2026-10-17  165  		emit(A64_MOVK(is64, reg, lo, 0), ctx);
e54bcde3d69d400 Zi Shen Lim     2014-08-26  166  	} else {
e54bcde3d69d400 Zi Shen Lim     2014-08-26  167  		emit(A64_MOVZ(is64, reg, lo, 0), ctx);
e54bcde3d69d400 Zi Shen Lim     2014-08-26  168  		emit(A64_MOVK(is64, reg, hi, 16), ctx);
e54bcde3d69d400 Zi Shen Lim     2014-08-26  169  	}
e54bcde3d69d400 Zi Shen Lim     2014-08-26  170  }
e54bcde3d69d400 Zi Shen Lim     2014-08-26  171  

:::::: The code at line 140 was first introduced by commit
:::::: e54bcde3d69d40023ae77727213d14f920eb264a arm64: eBPF JIT compiler

:::::: TO: Zi Shen Lim <zlim.lnx@gmail.com>
:::::: CC: Will Deacon <will.deacon@arm.com>

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki